261 lines
8.2 KiB
C++
261 lines
8.2 KiB
C++
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//===-- BPFInstrInfo.cpp - BPF Instruction Information ----------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the BPF implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "BPFInstrInfo.h"
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#include "BPF.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/IR/DebugLoc.h"
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#include "llvm/Support/ErrorHandling.h"
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#include <cassert>
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#include <iterator>
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#define GET_INSTRINFO_CTOR_DTOR
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#include "BPFGenInstrInfo.inc"
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using namespace llvm;
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BPFInstrInfo::BPFInstrInfo()
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: BPFGenInstrInfo(BPF::ADJCALLSTACKDOWN, BPF::ADJCALLSTACKUP) {}
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void BPFInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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const DebugLoc &DL, MCRegister DestReg,
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MCRegister SrcReg, bool KillSrc) const {
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if (BPF::GPRRegClass.contains(DestReg, SrcReg))
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BuildMI(MBB, I, DL, get(BPF::MOV_rr), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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else if (BPF::GPR32RegClass.contains(DestReg, SrcReg))
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BuildMI(MBB, I, DL, get(BPF::MOV_rr_32), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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else
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llvm_unreachable("Impossible reg-to-reg copy");
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}
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void BPFInstrInfo::expandMEMCPY(MachineBasicBlock::iterator MI) const {
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Register DstReg = MI->getOperand(0).getReg();
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Register SrcReg = MI->getOperand(1).getReg();
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uint64_t CopyLen = MI->getOperand(2).getImm();
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uint64_t Alignment = MI->getOperand(3).getImm();
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Register ScratchReg = MI->getOperand(4).getReg();
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MachineBasicBlock *BB = MI->getParent();
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DebugLoc dl = MI->getDebugLoc();
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unsigned LdOpc, StOpc;
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switch (Alignment) {
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case 1:
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LdOpc = BPF::LDB;
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StOpc = BPF::STB;
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break;
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case 2:
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LdOpc = BPF::LDH;
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StOpc = BPF::STH;
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break;
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case 4:
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LdOpc = BPF::LDW;
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StOpc = BPF::STW;
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break;
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case 8:
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LdOpc = BPF::LDD;
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StOpc = BPF::STD;
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break;
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default:
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llvm_unreachable("unsupported memcpy alignment");
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}
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unsigned IterationNum = CopyLen >> Log2_64(Alignment);
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for(unsigned I = 0; I < IterationNum; ++I) {
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BuildMI(*BB, MI, dl, get(LdOpc))
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.addReg(ScratchReg, RegState::Define).addReg(SrcReg)
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.addImm(I * Alignment);
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BuildMI(*BB, MI, dl, get(StOpc))
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.addReg(ScratchReg, RegState::Kill).addReg(DstReg)
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.addImm(I * Alignment);
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}
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unsigned BytesLeft = CopyLen & (Alignment - 1);
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unsigned Offset = IterationNum * Alignment;
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bool Hanging4Byte = BytesLeft & 0x4;
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bool Hanging2Byte = BytesLeft & 0x2;
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bool Hanging1Byte = BytesLeft & 0x1;
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if (Hanging4Byte) {
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BuildMI(*BB, MI, dl, get(BPF::LDW))
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.addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset);
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BuildMI(*BB, MI, dl, get(BPF::STW))
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.addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset);
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Offset += 4;
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}
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if (Hanging2Byte) {
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BuildMI(*BB, MI, dl, get(BPF::LDH))
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.addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset);
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BuildMI(*BB, MI, dl, get(BPF::STH))
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.addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset);
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Offset += 2;
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}
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if (Hanging1Byte) {
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BuildMI(*BB, MI, dl, get(BPF::LDB))
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.addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset);
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BuildMI(*BB, MI, dl, get(BPF::STB))
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.addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset);
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}
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BB->erase(MI);
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}
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bool BPFInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
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if (MI.getOpcode() == BPF::MEMCPY) {
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expandMEMCPY(MI);
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return true;
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}
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return false;
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}
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void BPFInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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Register SrcReg, bool IsKill, int FI,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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DebugLoc DL;
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if (I != MBB.end())
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DL = I->getDebugLoc();
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if (RC == &BPF::GPRRegClass)
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BuildMI(MBB, I, DL, get(BPF::STD))
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.addReg(SrcReg, getKillRegState(IsKill))
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.addFrameIndex(FI)
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.addImm(0);
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else if (RC == &BPF::GPR32RegClass)
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BuildMI(MBB, I, DL, get(BPF::STW32))
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.addReg(SrcReg, getKillRegState(IsKill))
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.addFrameIndex(FI)
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.addImm(0);
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else
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llvm_unreachable("Can't store this register to stack slot");
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}
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void BPFInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I,
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Register DestReg, int FI,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const {
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DebugLoc DL;
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if (I != MBB.end())
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DL = I->getDebugLoc();
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if (RC == &BPF::GPRRegClass)
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BuildMI(MBB, I, DL, get(BPF::LDD), DestReg).addFrameIndex(FI).addImm(0);
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else if (RC == &BPF::GPR32RegClass)
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BuildMI(MBB, I, DL, get(BPF::LDW32), DestReg).addFrameIndex(FI).addImm(0);
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else
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llvm_unreachable("Can't load this register from stack slot");
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}
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bool BPFInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const {
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// Start from the bottom of the block and work up, examining the
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// terminator instructions.
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MachineBasicBlock::iterator I = MBB.end();
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while (I != MBB.begin()) {
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--I;
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if (I->isDebugInstr())
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continue;
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// Working from the bottom, when we see a non-terminator
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// instruction, we're done.
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if (!isUnpredicatedTerminator(*I))
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break;
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// A terminator that isn't a branch can't easily be handled
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// by this analysis.
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if (!I->isBranch())
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return true;
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// Handle unconditional branches.
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if (I->getOpcode() == BPF::JMP) {
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if (!AllowModify) {
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TBB = I->getOperand(0).getMBB();
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continue;
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}
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// If the block has any instructions after a J, delete them.
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while (std::next(I) != MBB.end())
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std::next(I)->eraseFromParent();
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Cond.clear();
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FBB = nullptr;
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// Delete the J if it's equivalent to a fall-through.
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if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
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TBB = nullptr;
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I->eraseFromParent();
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I = MBB.end();
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continue;
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}
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// TBB is used to indicate the unconditinal destination.
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TBB = I->getOperand(0).getMBB();
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continue;
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}
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// Cannot handle conditional branches
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return true;
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}
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return false;
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}
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unsigned BPFInstrInfo::insertBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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ArrayRef<MachineOperand> Cond,
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const DebugLoc &DL,
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int *BytesAdded) const {
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assert(!BytesAdded && "code size not handled");
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// Shouldn't be a fall through.
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assert(TBB && "insertBranch must not be told to insert a fallthrough");
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if (Cond.empty()) {
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// Unconditional branch
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assert(!FBB && "Unconditional branch with multiple successors!");
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BuildMI(&MBB, DL, get(BPF::JMP)).addMBB(TBB);
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return 1;
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}
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llvm_unreachable("Unexpected conditional branch");
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}
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unsigned BPFInstrInfo::removeBranch(MachineBasicBlock &MBB,
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int *BytesRemoved) const {
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assert(!BytesRemoved && "code size not handled");
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MachineBasicBlock::iterator I = MBB.end();
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unsigned Count = 0;
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while (I != MBB.begin()) {
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--I;
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if (I->isDebugInstr())
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continue;
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if (I->getOpcode() != BPF::JMP)
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break;
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// Remove the branch.
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I->eraseFromParent();
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I = MBB.end();
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++Count;
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}
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return Count;
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}
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