447 lines
14 KiB
C++
447 lines
14 KiB
C++
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//===-- SIOptimizeExecMaskingPreRA.cpp ------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// This pass performs exec mask handling peephole optimizations which needs
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/// to be done before register allocation to reduce register pressure.
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///
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "GCNSubtarget.h"
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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#include "llvm/CodeGen/LiveIntervals.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/InitializePasses.h"
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using namespace llvm;
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#define DEBUG_TYPE "si-optimize-exec-masking-pre-ra"
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namespace {
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class SIOptimizeExecMaskingPreRA : public MachineFunctionPass {
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private:
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const SIRegisterInfo *TRI;
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const SIInstrInfo *TII;
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MachineRegisterInfo *MRI;
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LiveIntervals *LIS;
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unsigned AndOpc;
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unsigned Andn2Opc;
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unsigned OrSaveExecOpc;
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unsigned XorTermrOpc;
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MCRegister CondReg;
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MCRegister ExecReg;
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Register optimizeVcndVcmpPair(MachineBasicBlock &MBB);
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bool optimizeElseBranch(MachineBasicBlock &MBB);
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public:
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static char ID;
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SIOptimizeExecMaskingPreRA() : MachineFunctionPass(ID) {
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initializeSIOptimizeExecMaskingPreRAPass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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StringRef getPassName() const override {
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return "SI optimize exec mask operations pre-RA";
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.addRequired<LiveIntervals>();
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AU.setPreservesAll();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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};
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} // End anonymous namespace.
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INITIALIZE_PASS_BEGIN(SIOptimizeExecMaskingPreRA, DEBUG_TYPE,
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"SI optimize exec mask operations pre-RA", false, false)
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INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
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INITIALIZE_PASS_END(SIOptimizeExecMaskingPreRA, DEBUG_TYPE,
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"SI optimize exec mask operations pre-RA", false, false)
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char SIOptimizeExecMaskingPreRA::ID = 0;
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char &llvm::SIOptimizeExecMaskingPreRAID = SIOptimizeExecMaskingPreRA::ID;
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FunctionPass *llvm::createSIOptimizeExecMaskingPreRAPass() {
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return new SIOptimizeExecMaskingPreRA();
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}
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// See if there is a def between \p AndIdx and \p SelIdx that needs to live
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// beyond \p AndIdx.
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static bool isDefBetween(const LiveRange &LR, SlotIndex AndIdx,
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SlotIndex SelIdx) {
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LiveQueryResult AndLRQ = LR.Query(AndIdx);
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return (!AndLRQ.isKill() && AndLRQ.valueIn() != LR.Query(SelIdx).valueOut());
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}
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// FIXME: Why do we bother trying to handle physical registers here?
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static bool isDefBetween(const SIRegisterInfo &TRI,
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LiveIntervals *LIS, Register Reg,
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const MachineInstr &Sel, const MachineInstr &And) {
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SlotIndex AndIdx = LIS->getInstructionIndex(And);
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SlotIndex SelIdx = LIS->getInstructionIndex(Sel);
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if (Reg.isVirtual())
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return isDefBetween(LIS->getInterval(Reg), AndIdx, SelIdx);
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for (MCRegUnitIterator UI(Reg.asMCReg(), &TRI); UI.isValid(); ++UI) {
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if (isDefBetween(LIS->getRegUnit(*UI), AndIdx, SelIdx))
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return true;
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}
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return false;
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}
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// Optimize sequence
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// %sel = V_CNDMASK_B32_e64 0, 1, %cc
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// %cmp = V_CMP_NE_U32 1, %1
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// $vcc = S_AND_B64 $exec, %cmp
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// S_CBRANCH_VCC[N]Z
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// =>
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// $vcc = S_ANDN2_B64 $exec, %cc
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// S_CBRANCH_VCC[N]Z
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//
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// It is the negation pattern inserted by DAGCombiner::visitBRCOND() in the
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// rebuildSetCC(). We start with S_CBRANCH to avoid exhaustive search, but
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// only 3 first instructions are really needed. S_AND_B64 with exec is a
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// required part of the pattern since V_CNDMASK_B32 writes zeroes for inactive
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// lanes.
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//
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// Returns %cc register on success.
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Register
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SIOptimizeExecMaskingPreRA::optimizeVcndVcmpPair(MachineBasicBlock &MBB) {
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auto I = llvm::find_if(MBB.terminators(), [](const MachineInstr &MI) {
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unsigned Opc = MI.getOpcode();
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return Opc == AMDGPU::S_CBRANCH_VCCZ ||
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Opc == AMDGPU::S_CBRANCH_VCCNZ; });
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if (I == MBB.terminators().end())
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return Register();
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auto *And =
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TRI->findReachingDef(CondReg, AMDGPU::NoSubRegister, *I, *MRI, LIS);
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if (!And || And->getOpcode() != AndOpc ||
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!And->getOperand(1).isReg() || !And->getOperand(2).isReg())
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return Register();
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MachineOperand *AndCC = &And->getOperand(1);
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Register CmpReg = AndCC->getReg();
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unsigned CmpSubReg = AndCC->getSubReg();
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if (CmpReg == Register(ExecReg)) {
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AndCC = &And->getOperand(2);
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CmpReg = AndCC->getReg();
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CmpSubReg = AndCC->getSubReg();
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} else if (And->getOperand(2).getReg() != Register(ExecReg)) {
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return Register();
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}
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auto *Cmp = TRI->findReachingDef(CmpReg, CmpSubReg, *And, *MRI, LIS);
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if (!Cmp || !(Cmp->getOpcode() == AMDGPU::V_CMP_NE_U32_e32 ||
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Cmp->getOpcode() == AMDGPU::V_CMP_NE_U32_e64) ||
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Cmp->getParent() != And->getParent())
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return Register();
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MachineOperand *Op1 = TII->getNamedOperand(*Cmp, AMDGPU::OpName::src0);
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MachineOperand *Op2 = TII->getNamedOperand(*Cmp, AMDGPU::OpName::src1);
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if (Op1->isImm() && Op2->isReg())
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std::swap(Op1, Op2);
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if (!Op1->isReg() || !Op2->isImm() || Op2->getImm() != 1)
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return Register();
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Register SelReg = Op1->getReg();
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auto *Sel = TRI->findReachingDef(SelReg, Op1->getSubReg(), *Cmp, *MRI, LIS);
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if (!Sel || Sel->getOpcode() != AMDGPU::V_CNDMASK_B32_e64)
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return Register();
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if (TII->hasModifiersSet(*Sel, AMDGPU::OpName::src0_modifiers) ||
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TII->hasModifiersSet(*Sel, AMDGPU::OpName::src1_modifiers))
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return Register();
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Op1 = TII->getNamedOperand(*Sel, AMDGPU::OpName::src0);
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Op2 = TII->getNamedOperand(*Sel, AMDGPU::OpName::src1);
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MachineOperand *CC = TII->getNamedOperand(*Sel, AMDGPU::OpName::src2);
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if (!Op1->isImm() || !Op2->isImm() || !CC->isReg() ||
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Op1->getImm() != 0 || Op2->getImm() != 1)
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return Register();
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Register CCReg = CC->getReg();
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// If there was a def between the select and the and, we would need to move it
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// to fold this.
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if (isDefBetween(*TRI, LIS, CCReg, *Sel, *And))
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return Register();
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LLVM_DEBUG(dbgs() << "Folding sequence:\n\t" << *Sel << '\t' << *Cmp << '\t'
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<< *And);
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LIS->RemoveMachineInstrFromMaps(*And);
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MachineInstr *Andn2 =
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BuildMI(MBB, *And, And->getDebugLoc(), TII->get(Andn2Opc),
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And->getOperand(0).getReg())
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.addReg(ExecReg)
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.addReg(CCReg, getUndefRegState(CC->isUndef()), CC->getSubReg());
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MachineOperand &AndSCC = And->getOperand(3);
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assert(AndSCC.getReg() == AMDGPU::SCC);
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MachineOperand &Andn2SCC = Andn2->getOperand(3);
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assert(Andn2SCC.getReg() == AMDGPU::SCC);
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Andn2SCC.setIsDead(AndSCC.isDead());
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And->eraseFromParent();
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LIS->InsertMachineInstrInMaps(*Andn2);
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LLVM_DEBUG(dbgs() << "=>\n\t" << *Andn2 << '\n');
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// Try to remove compare. Cmp value should not used in between of cmp
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// and s_and_b64 if VCC or just unused if any other register.
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if ((CmpReg.isVirtual() && MRI->use_nodbg_empty(CmpReg)) ||
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(CmpReg == Register(CondReg) &&
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std::none_of(std::next(Cmp->getIterator()), Andn2->getIterator(),
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[&](const MachineInstr &MI) {
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return MI.readsRegister(CondReg, TRI);
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}))) {
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LLVM_DEBUG(dbgs() << "Erasing: " << *Cmp << '\n');
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LIS->RemoveMachineInstrFromMaps(*Cmp);
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Cmp->eraseFromParent();
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// Try to remove v_cndmask_b32.
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if (SelReg.isVirtual() && MRI->use_nodbg_empty(SelReg)) {
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LLVM_DEBUG(dbgs() << "Erasing: " << *Sel << '\n');
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LIS->RemoveMachineInstrFromMaps(*Sel);
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Sel->eraseFromParent();
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}
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}
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return CCReg;
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}
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// Optimize sequence
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// %dst = S_OR_SAVEEXEC %src
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// ... instructions not modifying exec ...
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// %tmp = S_AND $exec, %dst
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// $exec = S_XOR_term $exec, %tmp
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// =>
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// %dst = S_OR_SAVEEXEC %src
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// ... instructions not modifying exec ...
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// $exec = S_XOR_term $exec, %dst
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//
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// Clean up potentially unnecessary code added for safety during
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// control flow lowering.
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//
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// Return whether any changes were made to MBB.
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bool SIOptimizeExecMaskingPreRA::optimizeElseBranch(MachineBasicBlock &MBB) {
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if (MBB.empty())
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return false;
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// Check this is an else block.
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auto First = MBB.begin();
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MachineInstr &SaveExecMI = *First;
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if (SaveExecMI.getOpcode() != OrSaveExecOpc)
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return false;
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auto I = llvm::find_if(MBB.terminators(), [this](const MachineInstr &MI) {
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return MI.getOpcode() == XorTermrOpc;
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});
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if (I == MBB.terminators().end())
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return false;
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MachineInstr &XorTermMI = *I;
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if (XorTermMI.getOperand(1).getReg() != Register(ExecReg))
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return false;
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Register SavedExecReg = SaveExecMI.getOperand(0).getReg();
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Register DstReg = XorTermMI.getOperand(2).getReg();
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// Find potentially unnecessary S_AND
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MachineInstr *AndExecMI = nullptr;
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I--;
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while (I != First && !AndExecMI) {
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if (I->getOpcode() == AndOpc && I->getOperand(0).getReg() == DstReg &&
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I->getOperand(1).getReg() == Register(ExecReg))
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AndExecMI = &*I;
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I--;
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}
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if (!AndExecMI)
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return false;
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// Check for exec modifying instructions.
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// Note: exec defs do not create live ranges beyond the
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// instruction so isDefBetween cannot be used.
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// Instead just check that the def segments are adjacent.
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SlotIndex StartIdx = LIS->getInstructionIndex(SaveExecMI);
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SlotIndex EndIdx = LIS->getInstructionIndex(*AndExecMI);
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for (MCRegUnitIterator UI(ExecReg, TRI); UI.isValid(); ++UI) {
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LiveRange &RegUnit = LIS->getRegUnit(*UI);
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if (RegUnit.find(StartIdx) != std::prev(RegUnit.find(EndIdx)))
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return false;
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}
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// Remove unnecessary S_AND
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LIS->removeInterval(SavedExecReg);
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LIS->removeInterval(DstReg);
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SaveExecMI.getOperand(0).setReg(DstReg);
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LIS->RemoveMachineInstrFromMaps(*AndExecMI);
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AndExecMI->eraseFromParent();
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LIS->createAndComputeVirtRegInterval(DstReg);
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return true;
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}
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bool SIOptimizeExecMaskingPreRA::runOnMachineFunction(MachineFunction &MF) {
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if (skipFunction(MF.getFunction()))
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return false;
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const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
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TRI = ST.getRegisterInfo();
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TII = ST.getInstrInfo();
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MRI = &MF.getRegInfo();
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LIS = &getAnalysis<LiveIntervals>();
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const bool Wave32 = ST.isWave32();
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AndOpc = Wave32 ? AMDGPU::S_AND_B32 : AMDGPU::S_AND_B64;
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Andn2Opc = Wave32 ? AMDGPU::S_ANDN2_B32 : AMDGPU::S_ANDN2_B64;
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OrSaveExecOpc =
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Wave32 ? AMDGPU::S_OR_SAVEEXEC_B32 : AMDGPU::S_OR_SAVEEXEC_B64;
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XorTermrOpc = Wave32 ? AMDGPU::S_XOR_B32_term : AMDGPU::S_XOR_B64_term;
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CondReg = MCRegister::from(Wave32 ? AMDGPU::VCC_LO : AMDGPU::VCC);
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ExecReg = MCRegister::from(Wave32 ? AMDGPU::EXEC_LO : AMDGPU::EXEC);
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DenseSet<Register> RecalcRegs({AMDGPU::EXEC_LO, AMDGPU::EXEC_HI});
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bool Changed = false;
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for (MachineBasicBlock &MBB : MF) {
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if (optimizeElseBranch(MBB)) {
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RecalcRegs.insert(AMDGPU::SCC);
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Changed = true;
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}
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if (Register Reg = optimizeVcndVcmpPair(MBB)) {
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RecalcRegs.insert(Reg);
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RecalcRegs.insert(AMDGPU::VCC_LO);
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RecalcRegs.insert(AMDGPU::VCC_HI);
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RecalcRegs.insert(AMDGPU::SCC);
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Changed = true;
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}
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// Try to remove unneeded instructions before s_endpgm.
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if (MBB.succ_empty()) {
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|
if (MBB.empty())
|
||
|
|
continue;
|
||
|
|
|
||
|
|
// Skip this if the endpgm has any implicit uses, otherwise we would need
|
||
|
|
// to be careful to update / remove them.
|
||
|
|
// S_ENDPGM always has a single imm operand that is not used other than to
|
||
|
|
// end up in the encoding
|
||
|
|
MachineInstr &Term = MBB.back();
|
||
|
|
if (Term.getOpcode() != AMDGPU::S_ENDPGM || Term.getNumOperands() != 1)
|
||
|
|
continue;
|
||
|
|
|
||
|
|
SmallVector<MachineBasicBlock*, 4> Blocks({&MBB});
|
||
|
|
|
||
|
|
while (!Blocks.empty()) {
|
||
|
|
auto CurBB = Blocks.pop_back_val();
|
||
|
|
auto I = CurBB->rbegin(), E = CurBB->rend();
|
||
|
|
if (I != E) {
|
||
|
|
if (I->isUnconditionalBranch() || I->getOpcode() == AMDGPU::S_ENDPGM)
|
||
|
|
++I;
|
||
|
|
else if (I->isBranch())
|
||
|
|
continue;
|
||
|
|
}
|
||
|
|
|
||
|
|
while (I != E) {
|
||
|
|
if (I->isDebugInstr()) {
|
||
|
|
I = std::next(I);
|
||
|
|
continue;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (I->mayStore() || I->isBarrier() || I->isCall() ||
|
||
|
|
I->hasUnmodeledSideEffects() || I->hasOrderedMemoryRef())
|
||
|
|
break;
|
||
|
|
|
||
|
|
LLVM_DEBUG(dbgs()
|
||
|
|
<< "Removing no effect instruction: " << *I << '\n');
|
||
|
|
|
||
|
|
for (auto &Op : I->operands()) {
|
||
|
|
if (Op.isReg())
|
||
|
|
RecalcRegs.insert(Op.getReg());
|
||
|
|
}
|
||
|
|
|
||
|
|
auto Next = std::next(I);
|
||
|
|
LIS->RemoveMachineInstrFromMaps(*I);
|
||
|
|
I->eraseFromParent();
|
||
|
|
I = Next;
|
||
|
|
|
||
|
|
Changed = true;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (I != E)
|
||
|
|
continue;
|
||
|
|
|
||
|
|
// Try to ascend predecessors.
|
||
|
|
for (auto *Pred : CurBB->predecessors()) {
|
||
|
|
if (Pred->succ_size() == 1)
|
||
|
|
Blocks.push_back(Pred);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
continue;
|
||
|
|
}
|
||
|
|
|
||
|
|
// If the only user of a logical operation is move to exec, fold it now
|
||
|
|
// to prevent forming of saveexec. I.e:
|
||
|
|
//
|
||
|
|
// %0:sreg_64 = COPY $exec
|
||
|
|
// %1:sreg_64 = S_AND_B64 %0:sreg_64, %2:sreg_64
|
||
|
|
// =>
|
||
|
|
// %1 = S_AND_B64 $exec, %2:sreg_64
|
||
|
|
unsigned ScanThreshold = 10;
|
||
|
|
for (auto I = MBB.rbegin(), E = MBB.rend(); I != E
|
||
|
|
&& ScanThreshold--; ++I) {
|
||
|
|
// Continue scanning if this is not a full exec copy
|
||
|
|
if (!(I->isFullCopy() && I->getOperand(1).getReg() == Register(ExecReg)))
|
||
|
|
continue;
|
||
|
|
|
||
|
|
Register SavedExec = I->getOperand(0).getReg();
|
||
|
|
if (SavedExec.isVirtual() && MRI->hasOneNonDBGUse(SavedExec) &&
|
||
|
|
MRI->use_instr_nodbg_begin(SavedExec)->getParent() ==
|
||
|
|
I->getParent()) {
|
||
|
|
LLVM_DEBUG(dbgs() << "Redundant EXEC COPY: " << *I << '\n');
|
||
|
|
LIS->RemoveMachineInstrFromMaps(*I);
|
||
|
|
I->eraseFromParent();
|
||
|
|
MRI->replaceRegWith(SavedExec, ExecReg);
|
||
|
|
LIS->removeInterval(SavedExec);
|
||
|
|
Changed = true;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
if (Changed) {
|
||
|
|
for (auto Reg : RecalcRegs) {
|
||
|
|
if (Reg.isVirtual()) {
|
||
|
|
LIS->removeInterval(Reg);
|
||
|
|
if (!MRI->reg_empty(Reg))
|
||
|
|
LIS->createAndComputeVirtRegInterval(Reg);
|
||
|
|
} else {
|
||
|
|
LIS->removeAllRegUnitsForPhysReg(Reg);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return Changed;
|
||
|
|
}
|