414 lines
13 KiB
C++
414 lines
13 KiB
C++
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//===----- R600Packetizer.cpp - VLIW packetizer ---------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// This pass implements instructions packetization for R600. It unsets isLast
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/// bit of instructions inside a bundle and substitutes src register with
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/// PreviousVector when applicable.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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#include "R600Subtarget.h"
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#include "llvm/CodeGen/DFAPacketizer.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/ScheduleDAG.h"
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using namespace llvm;
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#define DEBUG_TYPE "packets"
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namespace {
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class R600Packetizer : public MachineFunctionPass {
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public:
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static char ID;
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R600Packetizer() : MachineFunctionPass(ID) {}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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AU.addRequired<MachineDominatorTree>();
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AU.addPreserved<MachineDominatorTree>();
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AU.addRequired<MachineLoopInfo>();
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AU.addPreserved<MachineLoopInfo>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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StringRef getPassName() const override { return "R600 Packetizer"; }
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bool runOnMachineFunction(MachineFunction &Fn) override;
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};
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class R600PacketizerList : public VLIWPacketizerList {
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private:
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const R600InstrInfo *TII;
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const R600RegisterInfo &TRI;
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bool VLIW5;
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bool ConsideredInstUsesAlreadyWrittenVectorElement;
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unsigned getSlot(const MachineInstr &MI) const {
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return TRI.getHWRegChan(MI.getOperand(0).getReg());
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}
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/// \returns register to PV chan mapping for bundle/single instructions that
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/// immediately precedes I.
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DenseMap<unsigned, unsigned> getPreviousVector(MachineBasicBlock::iterator I)
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const {
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DenseMap<unsigned, unsigned> Result;
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I--;
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if (!TII->isALUInstr(I->getOpcode()) && !I->isBundle())
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return Result;
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MachineBasicBlock::instr_iterator BI = I.getInstrIterator();
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if (I->isBundle())
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BI++;
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int LastDstChan = -1;
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do {
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bool isTrans = false;
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int BISlot = getSlot(*BI);
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if (LastDstChan >= BISlot)
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isTrans = true;
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LastDstChan = BISlot;
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if (TII->isPredicated(*BI))
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continue;
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int OperandIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::write);
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if (OperandIdx > -1 && BI->getOperand(OperandIdx).getImm() == 0)
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continue;
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int DstIdx = TII->getOperandIdx(BI->getOpcode(), R600::OpName::dst);
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if (DstIdx == -1) {
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continue;
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}
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Register Dst = BI->getOperand(DstIdx).getReg();
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if (isTrans || TII->isTransOnly(*BI)) {
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Result[Dst] = R600::PS;
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continue;
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}
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if (BI->getOpcode() == R600::DOT4_r600 ||
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BI->getOpcode() == R600::DOT4_eg) {
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Result[Dst] = R600::PV_X;
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continue;
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}
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if (Dst == R600::OQAP) {
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continue;
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}
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unsigned PVReg = 0;
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switch (TRI.getHWRegChan(Dst)) {
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case 0:
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PVReg = R600::PV_X;
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break;
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case 1:
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PVReg = R600::PV_Y;
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break;
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case 2:
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PVReg = R600::PV_Z;
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break;
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case 3:
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PVReg = R600::PV_W;
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break;
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default:
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llvm_unreachable("Invalid Chan");
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}
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Result[Dst] = PVReg;
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} while ((++BI)->isBundledWithPred());
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return Result;
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}
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void substitutePV(MachineInstr &MI, const DenseMap<unsigned, unsigned> &PVs)
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const {
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unsigned Ops[] = {
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R600::OpName::src0,
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R600::OpName::src1,
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R600::OpName::src2
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};
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for (unsigned i = 0; i < 3; i++) {
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int OperandIdx = TII->getOperandIdx(MI.getOpcode(), Ops[i]);
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if (OperandIdx < 0)
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continue;
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Register Src = MI.getOperand(OperandIdx).getReg();
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const DenseMap<unsigned, unsigned>::const_iterator It = PVs.find(Src);
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if (It != PVs.end())
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MI.getOperand(OperandIdx).setReg(It->second);
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}
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}
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public:
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// Ctor.
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R600PacketizerList(MachineFunction &MF, const R600Subtarget &ST,
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MachineLoopInfo &MLI)
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: VLIWPacketizerList(MF, MLI, nullptr),
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TII(ST.getInstrInfo()),
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TRI(TII->getRegisterInfo()) {
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VLIW5 = !ST.hasCaymanISA();
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}
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// initPacketizerState - initialize some internal flags.
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void initPacketizerState() override {
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ConsideredInstUsesAlreadyWrittenVectorElement = false;
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}
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// ignorePseudoInstruction - Ignore bundling of pseudo instructions.
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bool ignorePseudoInstruction(const MachineInstr &MI,
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const MachineBasicBlock *MBB) override {
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return false;
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}
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// isSoloInstruction - return true if instruction MI can not be packetized
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// with any other instruction, which means that MI itself is a packet.
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bool isSoloInstruction(const MachineInstr &MI) override {
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if (TII->isVector(MI))
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return true;
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if (!TII->isALUInstr(MI.getOpcode()))
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return true;
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if (MI.getOpcode() == R600::GROUP_BARRIER)
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return true;
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// XXX: This can be removed once the packetizer properly handles all the
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// LDS instruction group restrictions.
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return TII->isLDSInstr(MI.getOpcode());
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}
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// isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ
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// together.
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bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) override {
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MachineInstr *MII = SUI->getInstr(), *MIJ = SUJ->getInstr();
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if (getSlot(*MII) == getSlot(*MIJ))
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ConsideredInstUsesAlreadyWrittenVectorElement = true;
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// Does MII and MIJ share the same pred_sel ?
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int OpI = TII->getOperandIdx(MII->getOpcode(), R600::OpName::pred_sel),
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OpJ = TII->getOperandIdx(MIJ->getOpcode(), R600::OpName::pred_sel);
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Register PredI = (OpI > -1)?MII->getOperand(OpI).getReg() : Register(),
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PredJ = (OpJ > -1)?MIJ->getOperand(OpJ).getReg() : Register();
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if (PredI != PredJ)
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return false;
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if (SUJ->isSucc(SUI)) {
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for (unsigned i = 0, e = SUJ->Succs.size(); i < e; ++i) {
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const SDep &Dep = SUJ->Succs[i];
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if (Dep.getSUnit() != SUI)
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continue;
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if (Dep.getKind() == SDep::Anti)
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continue;
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if (Dep.getKind() == SDep::Output)
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if (MII->getOperand(0).getReg() != MIJ->getOperand(0).getReg())
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continue;
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return false;
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}
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}
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bool ARDef =
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TII->definesAddressRegister(*MII) || TII->definesAddressRegister(*MIJ);
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bool ARUse =
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TII->usesAddressRegister(*MII) || TII->usesAddressRegister(*MIJ);
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return !ARDef || !ARUse;
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}
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// isLegalToPruneDependencies - Is it legal to prune dependece between SUI
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// and SUJ.
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bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) override {
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return false;
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}
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void setIsLastBit(MachineInstr *MI, unsigned Bit) const {
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unsigned LastOp = TII->getOperandIdx(MI->getOpcode(), R600::OpName::last);
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MI->getOperand(LastOp).setImm(Bit);
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}
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bool isBundlableWithCurrentPMI(MachineInstr &MI,
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const DenseMap<unsigned, unsigned> &PV,
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std::vector<R600InstrInfo::BankSwizzle> &BS,
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bool &isTransSlot) {
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isTransSlot = TII->isTransOnly(MI);
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assert (!isTransSlot || VLIW5);
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// Is the dst reg sequence legal ?
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if (!isTransSlot && !CurrentPacketMIs.empty()) {
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if (getSlot(MI) <= getSlot(*CurrentPacketMIs.back())) {
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if (ConsideredInstUsesAlreadyWrittenVectorElement &&
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!TII->isVectorOnly(MI) && VLIW5) {
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isTransSlot = true;
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LLVM_DEBUG({
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dbgs() << "Considering as Trans Inst :";
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MI.dump();
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});
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}
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else
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return false;
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}
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}
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// Are the Constants limitations met ?
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CurrentPacketMIs.push_back(&MI);
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if (!TII->fitsConstReadLimitations(CurrentPacketMIs)) {
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LLVM_DEBUG({
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dbgs() << "Couldn't pack :\n";
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MI.dump();
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dbgs() << "with the following packets :\n";
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for (unsigned i = 0, e = CurrentPacketMIs.size() - 1; i < e; i++) {
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CurrentPacketMIs[i]->dump();
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dbgs() << "\n";
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}
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dbgs() << "because of Consts read limitations\n";
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});
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CurrentPacketMIs.pop_back();
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return false;
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}
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// Is there a BankSwizzle set that meet Read Port limitations ?
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if (!TII->fitsReadPortLimitations(CurrentPacketMIs,
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PV, BS, isTransSlot)) {
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LLVM_DEBUG({
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dbgs() << "Couldn't pack :\n";
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MI.dump();
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dbgs() << "with the following packets :\n";
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for (unsigned i = 0, e = CurrentPacketMIs.size() - 1; i < e; i++) {
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CurrentPacketMIs[i]->dump();
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dbgs() << "\n";
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}
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dbgs() << "because of Read port limitations\n";
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});
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CurrentPacketMIs.pop_back();
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return false;
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}
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// We cannot read LDS source registers from the Trans slot.
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if (isTransSlot && TII->readsLDSSrcReg(MI))
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return false;
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CurrentPacketMIs.pop_back();
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return true;
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}
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MachineBasicBlock::iterator addToPacket(MachineInstr &MI) override {
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MachineBasicBlock::iterator FirstInBundle =
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CurrentPacketMIs.empty() ? &MI : CurrentPacketMIs.front();
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const DenseMap<unsigned, unsigned> &PV =
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getPreviousVector(FirstInBundle);
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std::vector<R600InstrInfo::BankSwizzle> BS;
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bool isTransSlot;
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if (isBundlableWithCurrentPMI(MI, PV, BS, isTransSlot)) {
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for (unsigned i = 0, e = CurrentPacketMIs.size(); i < e; i++) {
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MachineInstr *MI = CurrentPacketMIs[i];
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unsigned Op = TII->getOperandIdx(MI->getOpcode(),
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R600::OpName::bank_swizzle);
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MI->getOperand(Op).setImm(BS[i]);
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}
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unsigned Op =
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TII->getOperandIdx(MI.getOpcode(), R600::OpName::bank_swizzle);
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MI.getOperand(Op).setImm(BS.back());
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if (!CurrentPacketMIs.empty())
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setIsLastBit(CurrentPacketMIs.back(), 0);
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substitutePV(MI, PV);
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MachineBasicBlock::iterator It = VLIWPacketizerList::addToPacket(MI);
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if (isTransSlot) {
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endPacket(std::next(It)->getParent(), std::next(It));
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}
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return It;
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}
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endPacket(MI.getParent(), MI);
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if (TII->isTransOnly(MI))
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return MI;
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return VLIWPacketizerList::addToPacket(MI);
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}
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};
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bool R600Packetizer::runOnMachineFunction(MachineFunction &Fn) {
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const R600Subtarget &ST = Fn.getSubtarget<R600Subtarget>();
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const R600InstrInfo *TII = ST.getInstrInfo();
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MachineLoopInfo &MLI = getAnalysis<MachineLoopInfo>();
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// Instantiate the packetizer.
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R600PacketizerList Packetizer(Fn, ST, MLI);
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// DFA state table should not be empty.
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assert(Packetizer.getResourceTracker() && "Empty DFA table!");
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assert(Packetizer.getResourceTracker()->getInstrItins());
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if (Packetizer.getResourceTracker()->getInstrItins()->isEmpty())
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return false;
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//
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// Loop over all basic blocks and remove KILL pseudo-instructions
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// These instructions confuse the dependence analysis. Consider:
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// D0 = ... (Insn 0)
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// R0 = KILL R0, D0 (Insn 1)
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// R0 = ... (Insn 2)
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// Here, Insn 1 will result in the dependence graph not emitting an output
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// dependence between Insn 0 and Insn 2. This can lead to incorrect
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// packetization
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//
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for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
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MBB != MBBe; ++MBB) {
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MachineBasicBlock::iterator End = MBB->end();
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MachineBasicBlock::iterator MI = MBB->begin();
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while (MI != End) {
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if (MI->isKill() || MI->getOpcode() == R600::IMPLICIT_DEF ||
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(MI->getOpcode() == R600::CF_ALU && !MI->getOperand(8).getImm())) {
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MachineBasicBlock::iterator DeleteMI = MI;
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++MI;
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MBB->erase(DeleteMI);
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End = MBB->end();
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continue;
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}
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++MI;
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}
|
||
|
|
}
|
||
|
|
|
||
|
|
// Loop over all of the basic blocks.
|
||
|
|
for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
|
||
|
|
MBB != MBBe; ++MBB) {
|
||
|
|
// Find scheduling regions and schedule / packetize each region.
|
||
|
|
unsigned RemainingCount = MBB->size();
|
||
|
|
for(MachineBasicBlock::iterator RegionEnd = MBB->end();
|
||
|
|
RegionEnd != MBB->begin();) {
|
||
|
|
// The next region starts above the previous region. Look backward in the
|
||
|
|
// instruction stream until we find the nearest boundary.
|
||
|
|
MachineBasicBlock::iterator I = RegionEnd;
|
||
|
|
for(;I != MBB->begin(); --I, --RemainingCount) {
|
||
|
|
if (TII->isSchedulingBoundary(*std::prev(I), &*MBB, Fn))
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
I = MBB->begin();
|
||
|
|
|
||
|
|
// Skip empty scheduling regions.
|
||
|
|
if (I == RegionEnd) {
|
||
|
|
RegionEnd = std::prev(RegionEnd);
|
||
|
|
--RemainingCount;
|
||
|
|
continue;
|
||
|
|
}
|
||
|
|
// Skip regions with one instruction.
|
||
|
|
if (I == std::prev(RegionEnd)) {
|
||
|
|
RegionEnd = std::prev(RegionEnd);
|
||
|
|
continue;
|
||
|
|
}
|
||
|
|
|
||
|
|
Packetizer.PacketizeMIs(&*MBB, &*I, RegionEnd);
|
||
|
|
RegionEnd = I;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return true;
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
} // end anonymous namespace
|
||
|
|
|
||
|
|
INITIALIZE_PASS_BEGIN(R600Packetizer, DEBUG_TYPE,
|
||
|
|
"R600 Packetizer", false, false)
|
||
|
|
INITIALIZE_PASS_END(R600Packetizer, DEBUG_TYPE,
|
||
|
|
"R600 Packetizer", false, false)
|
||
|
|
|
||
|
|
char R600Packetizer::ID = 0;
|
||
|
|
|
||
|
|
char &llvm::R600PacketizerID = R600Packetizer::ID;
|
||
|
|
|
||
|
|
llvm::FunctionPass *llvm::createR600Packetizer() {
|
||
|
|
return new R600Packetizer();
|
||
|
|
}
|