55 lines
1.7 KiB
C++
55 lines
1.7 KiB
C++
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//===- AMDGPUGlobalISelUtils.cpp ---------------------------------*- C++ -*-==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPUGlobalISelUtils.h"
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#include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
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#include "llvm/IR/Constants.h"
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using namespace llvm;
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using namespace MIPatternMatch;
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std::pair<Register, unsigned>
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AMDGPU::getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg) {
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MachineInstr *Def = getDefIgnoringCopies(Reg, MRI);
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if (!Def)
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return std::make_pair(Reg, 0);
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if (Def->getOpcode() == TargetOpcode::G_CONSTANT) {
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unsigned Offset;
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const MachineOperand &Op = Def->getOperand(1);
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if (Op.isImm())
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Offset = Op.getImm();
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else
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Offset = Op.getCImm()->getZExtValue();
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return std::make_pair(Register(), Offset);
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}
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int64_t Offset;
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if (Def->getOpcode() == TargetOpcode::G_ADD) {
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// TODO: Handle G_OR used for add case
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if (mi_match(Def->getOperand(2).getReg(), MRI, m_ICst(Offset)))
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return std::make_pair(Def->getOperand(1).getReg(), Offset);
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// FIXME: matcher should ignore copies
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if (mi_match(Def->getOperand(2).getReg(), MRI, m_Copy(m_ICst(Offset))))
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return std::make_pair(Def->getOperand(1).getReg(), Offset);
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}
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return std::make_pair(Reg, 0);
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}
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bool AMDGPU::isLegalVOP3PShuffleMask(ArrayRef<int> Mask) {
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assert(Mask.size() == 2);
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// If one half is undef, the other is trivially in the same reg.
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if (Mask[0] == -1 || Mask[1] == -1)
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return true;
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return (Mask[0] & 2) == (Mask[1] & 2);
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}
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