355 lines
13 KiB
C++
355 lines
13 KiB
C++
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//=== AArch64PostLegalizerCombiner.cpp --------------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// Post-legalization combines on generic MachineInstrs.
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///
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/// The combines here must preserve instruction legality.
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///
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/// Lowering combines (e.g. pseudo matching) should be handled by
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/// AArch64PostLegalizerLowering.
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///
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/// Combines which don't rely on instruction legality should go in the
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/// AArch64PreLegalizerCombiner.
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///
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//===----------------------------------------------------------------------===//
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#include "AArch64TargetMachine.h"
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#include "llvm/CodeGen/GlobalISel/Combiner.h"
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#include "llvm/CodeGen/GlobalISel/CombinerHelper.h"
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#include "llvm/CodeGen/GlobalISel/CombinerInfo.h"
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#include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
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#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
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#include "llvm/CodeGen/GlobalISel/Utils.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetOpcodes.h"
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#include "llvm/CodeGen/TargetPassConfig.h"
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#include "llvm/Support/Debug.h"
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#define DEBUG_TYPE "aarch64-postlegalizer-combiner"
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using namespace llvm;
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/// This combine tries do what performExtractVectorEltCombine does in SDAG.
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/// Rewrite for pairwise fadd pattern
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/// (s32 (g_extract_vector_elt
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/// (g_fadd (vXs32 Other)
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/// (g_vector_shuffle (vXs32 Other) undef <1,X,...> )) 0))
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/// ->
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/// (s32 (g_fadd (g_extract_vector_elt (vXs32 Other) 0)
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/// (g_extract_vector_elt (vXs32 Other) 1))
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bool matchExtractVecEltPairwiseAdd(
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MachineInstr &MI, MachineRegisterInfo &MRI,
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std::tuple<unsigned, LLT, Register> &MatchInfo) {
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Register Src1 = MI.getOperand(1).getReg();
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Register Src2 = MI.getOperand(2).getReg();
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LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
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auto Cst = getConstantVRegValWithLookThrough(Src2, MRI);
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if (!Cst || Cst->Value != 0)
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return false;
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// SDAG also checks for FullFP16, but this looks to be beneficial anyway.
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// Now check for an fadd operation. TODO: expand this for integer add?
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auto *FAddMI = getOpcodeDef(TargetOpcode::G_FADD, Src1, MRI);
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if (!FAddMI)
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return false;
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// If we add support for integer add, must restrict these types to just s64.
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unsigned DstSize = DstTy.getSizeInBits();
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if (DstSize != 16 && DstSize != 32 && DstSize != 64)
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return false;
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Register Src1Op1 = FAddMI->getOperand(1).getReg();
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Register Src1Op2 = FAddMI->getOperand(2).getReg();
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MachineInstr *Shuffle =
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getOpcodeDef(TargetOpcode::G_SHUFFLE_VECTOR, Src1Op2, MRI);
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MachineInstr *Other = MRI.getVRegDef(Src1Op1);
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if (!Shuffle) {
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Shuffle = getOpcodeDef(TargetOpcode::G_SHUFFLE_VECTOR, Src1Op1, MRI);
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Other = MRI.getVRegDef(Src1Op2);
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}
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// We're looking for a shuffle that moves the second element to index 0.
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if (Shuffle && Shuffle->getOperand(3).getShuffleMask()[0] == 1 &&
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Other == MRI.getVRegDef(Shuffle->getOperand(1).getReg())) {
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std::get<0>(MatchInfo) = TargetOpcode::G_FADD;
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std::get<1>(MatchInfo) = DstTy;
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std::get<2>(MatchInfo) = Other->getOperand(0).getReg();
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return true;
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}
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return false;
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}
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bool applyExtractVecEltPairwiseAdd(
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MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B,
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std::tuple<unsigned, LLT, Register> &MatchInfo) {
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unsigned Opc = std::get<0>(MatchInfo);
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assert(Opc == TargetOpcode::G_FADD && "Unexpected opcode!");
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// We want to generate two extracts of elements 0 and 1, and add them.
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LLT Ty = std::get<1>(MatchInfo);
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Register Src = std::get<2>(MatchInfo);
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LLT s64 = LLT::scalar(64);
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B.setInstrAndDebugLoc(MI);
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auto Elt0 = B.buildExtractVectorElement(Ty, Src, B.buildConstant(s64, 0));
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auto Elt1 = B.buildExtractVectorElement(Ty, Src, B.buildConstant(s64, 1));
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B.buildInstr(Opc, {MI.getOperand(0).getReg()}, {Elt0, Elt1});
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MI.eraseFromParent();
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return true;
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}
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static bool isSignExtended(Register R, MachineRegisterInfo &MRI) {
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// TODO: check if extended build vector as well.
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unsigned Opc = MRI.getVRegDef(R)->getOpcode();
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return Opc == TargetOpcode::G_SEXT || Opc == TargetOpcode::G_SEXT_INREG;
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}
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static bool isZeroExtended(Register R, MachineRegisterInfo &MRI) {
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// TODO: check if extended build vector as well.
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return MRI.getVRegDef(R)->getOpcode() == TargetOpcode::G_ZEXT;
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}
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bool matchAArch64MulConstCombine(
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MachineInstr &MI, MachineRegisterInfo &MRI,
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std::function<void(MachineIRBuilder &B, Register DstReg)> &ApplyFn) {
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assert(MI.getOpcode() == TargetOpcode::G_MUL);
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Register LHS = MI.getOperand(1).getReg();
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Register RHS = MI.getOperand(2).getReg();
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Register Dst = MI.getOperand(0).getReg();
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const LLT Ty = MRI.getType(LHS);
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// The below optimizations require a constant RHS.
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auto Const = getConstantVRegValWithLookThrough(RHS, MRI);
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if (!Const)
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return false;
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const APInt ConstValue = Const->Value.sextOrSelf(Ty.getSizeInBits());
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// The following code is ported from AArch64ISelLowering.
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// Multiplication of a power of two plus/minus one can be done more
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// cheaply as as shift+add/sub. For now, this is true unilaterally. If
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// future CPUs have a cheaper MADD instruction, this may need to be
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// gated on a subtarget feature. For Cyclone, 32-bit MADD is 4 cycles and
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// 64-bit is 5 cycles, so this is always a win.
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// More aggressively, some multiplications N0 * C can be lowered to
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// shift+add+shift if the constant C = A * B where A = 2^N + 1 and B = 2^M,
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// e.g. 6=3*2=(2+1)*2.
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// TODO: consider lowering more cases, e.g. C = 14, -6, -14 or even 45
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// which equals to (1+2)*16-(1+2).
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// TrailingZeroes is used to test if the mul can be lowered to
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// shift+add+shift.
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unsigned TrailingZeroes = ConstValue.countTrailingZeros();
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if (TrailingZeroes) {
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// Conservatively do not lower to shift+add+shift if the mul might be
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// folded into smul or umul.
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if (MRI.hasOneNonDBGUse(LHS) &&
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(isSignExtended(LHS, MRI) || isZeroExtended(LHS, MRI)))
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return false;
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// Conservatively do not lower to shift+add+shift if the mul might be
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// folded into madd or msub.
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if (MRI.hasOneNonDBGUse(Dst)) {
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MachineInstr &UseMI = *MRI.use_instr_begin(Dst);
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if (UseMI.getOpcode() == TargetOpcode::G_ADD ||
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UseMI.getOpcode() == TargetOpcode::G_SUB)
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return false;
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}
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}
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// Use ShiftedConstValue instead of ConstValue to support both shift+add/sub
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// and shift+add+shift.
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APInt ShiftedConstValue = ConstValue.ashr(TrailingZeroes);
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unsigned ShiftAmt, AddSubOpc;
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// Is the shifted value the LHS operand of the add/sub?
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bool ShiftValUseIsLHS = true;
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// Do we need to negate the result?
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bool NegateResult = false;
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if (ConstValue.isNonNegative()) {
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// (mul x, 2^N + 1) => (add (shl x, N), x)
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// (mul x, 2^N - 1) => (sub (shl x, N), x)
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// (mul x, (2^N + 1) * 2^M) => (shl (add (shl x, N), x), M)
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APInt SCVMinus1 = ShiftedConstValue - 1;
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APInt CVPlus1 = ConstValue + 1;
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if (SCVMinus1.isPowerOf2()) {
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ShiftAmt = SCVMinus1.logBase2();
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AddSubOpc = TargetOpcode::G_ADD;
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} else if (CVPlus1.isPowerOf2()) {
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ShiftAmt = CVPlus1.logBase2();
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AddSubOpc = TargetOpcode::G_SUB;
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} else
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return false;
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} else {
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// (mul x, -(2^N - 1)) => (sub x, (shl x, N))
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// (mul x, -(2^N + 1)) => - (add (shl x, N), x)
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APInt CVNegPlus1 = -ConstValue + 1;
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APInt CVNegMinus1 = -ConstValue - 1;
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if (CVNegPlus1.isPowerOf2()) {
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ShiftAmt = CVNegPlus1.logBase2();
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AddSubOpc = TargetOpcode::G_SUB;
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ShiftValUseIsLHS = false;
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} else if (CVNegMinus1.isPowerOf2()) {
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ShiftAmt = CVNegMinus1.logBase2();
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AddSubOpc = TargetOpcode::G_ADD;
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NegateResult = true;
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} else
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return false;
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}
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if (NegateResult && TrailingZeroes)
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return false;
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ApplyFn = [=](MachineIRBuilder &B, Register DstReg) {
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auto Shift = B.buildConstant(LLT::scalar(64), ShiftAmt);
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auto ShiftedVal = B.buildShl(Ty, LHS, Shift);
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Register AddSubLHS = ShiftValUseIsLHS ? ShiftedVal.getReg(0) : LHS;
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Register AddSubRHS = ShiftValUseIsLHS ? LHS : ShiftedVal.getReg(0);
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auto Res = B.buildInstr(AddSubOpc, {Ty}, {AddSubLHS, AddSubRHS});
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assert(!(NegateResult && TrailingZeroes) &&
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"NegateResult and TrailingZeroes cannot both be true for now.");
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// Negate the result.
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if (NegateResult) {
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B.buildSub(DstReg, B.buildConstant(Ty, 0), Res);
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return;
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}
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// Shift the result.
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if (TrailingZeroes) {
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B.buildShl(DstReg, Res, B.buildConstant(LLT::scalar(64), TrailingZeroes));
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return;
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}
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B.buildCopy(DstReg, Res.getReg(0));
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};
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return true;
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}
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bool applyAArch64MulConstCombine(
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MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B,
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std::function<void(MachineIRBuilder &B, Register DstReg)> &ApplyFn) {
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B.setInstrAndDebugLoc(MI);
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ApplyFn(B, MI.getOperand(0).getReg());
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MI.eraseFromParent();
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return true;
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}
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#define AARCH64POSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS
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#include "AArch64GenPostLegalizeGICombiner.inc"
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#undef AARCH64POSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS
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namespace {
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#define AARCH64POSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_H
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#include "AArch64GenPostLegalizeGICombiner.inc"
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#undef AARCH64POSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_H
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class AArch64PostLegalizerCombinerInfo : public CombinerInfo {
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GISelKnownBits *KB;
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MachineDominatorTree *MDT;
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public:
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AArch64GenPostLegalizerCombinerHelperRuleConfig GeneratedRuleCfg;
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AArch64PostLegalizerCombinerInfo(bool EnableOpt, bool OptSize, bool MinSize,
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GISelKnownBits *KB,
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MachineDominatorTree *MDT)
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: CombinerInfo(/*AllowIllegalOps*/ true, /*ShouldLegalizeIllegal*/ false,
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/*LegalizerInfo*/ nullptr, EnableOpt, OptSize, MinSize),
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KB(KB), MDT(MDT) {
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if (!GeneratedRuleCfg.parseCommandLineOption())
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report_fatal_error("Invalid rule identifier");
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}
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virtual bool combine(GISelChangeObserver &Observer, MachineInstr &MI,
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MachineIRBuilder &B) const override;
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};
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bool AArch64PostLegalizerCombinerInfo::combine(GISelChangeObserver &Observer,
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MachineInstr &MI,
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MachineIRBuilder &B) const {
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const auto *LI =
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MI.getParent()->getParent()->getSubtarget().getLegalizerInfo();
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CombinerHelper Helper(Observer, B, KB, MDT, LI);
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AArch64GenPostLegalizerCombinerHelper Generated(GeneratedRuleCfg);
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return Generated.tryCombineAll(Observer, MI, B, Helper);
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}
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#define AARCH64POSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_CPP
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#include "AArch64GenPostLegalizeGICombiner.inc"
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#undef AARCH64POSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_CPP
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class AArch64PostLegalizerCombiner : public MachineFunctionPass {
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public:
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static char ID;
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AArch64PostLegalizerCombiner(bool IsOptNone = false);
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StringRef getPassName() const override {
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return "AArch64PostLegalizerCombiner";
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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void getAnalysisUsage(AnalysisUsage &AU) const override;
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private:
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bool IsOptNone;
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};
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} // end anonymous namespace
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void AArch64PostLegalizerCombiner::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<TargetPassConfig>();
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AU.setPreservesCFG();
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getSelectionDAGFallbackAnalysisUsage(AU);
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AU.addRequired<GISelKnownBitsAnalysis>();
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AU.addPreserved<GISelKnownBitsAnalysis>();
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if (!IsOptNone) {
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AU.addRequired<MachineDominatorTree>();
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AU.addPreserved<MachineDominatorTree>();
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}
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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AArch64PostLegalizerCombiner::AArch64PostLegalizerCombiner(bool IsOptNone)
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: MachineFunctionPass(ID), IsOptNone(IsOptNone) {
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initializeAArch64PostLegalizerCombinerPass(*PassRegistry::getPassRegistry());
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}
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bool AArch64PostLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
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if (MF.getProperties().hasProperty(
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MachineFunctionProperties::Property::FailedISel))
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return false;
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assert(MF.getProperties().hasProperty(
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MachineFunctionProperties::Property::Legalized) &&
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|
"Expected a legalized function?");
|
||
|
|
auto *TPC = &getAnalysis<TargetPassConfig>();
|
||
|
|
const Function &F = MF.getFunction();
|
||
|
|
bool EnableOpt =
|
||
|
|
MF.getTarget().getOptLevel() != CodeGenOpt::None && !skipFunction(F);
|
||
|
|
GISelKnownBits *KB = &getAnalysis<GISelKnownBitsAnalysis>().get(MF);
|
||
|
|
MachineDominatorTree *MDT =
|
||
|
|
IsOptNone ? nullptr : &getAnalysis<MachineDominatorTree>();
|
||
|
|
AArch64PostLegalizerCombinerInfo PCInfo(EnableOpt, F.hasOptSize(),
|
||
|
|
F.hasMinSize(), KB, MDT);
|
||
|
|
Combiner C(PCInfo, TPC);
|
||
|
|
return C.combineMachineInstrs(MF, /*CSEInfo*/ nullptr);
|
||
|
|
}
|
||
|
|
|
||
|
|
char AArch64PostLegalizerCombiner::ID = 0;
|
||
|
|
INITIALIZE_PASS_BEGIN(AArch64PostLegalizerCombiner, DEBUG_TYPE,
|
||
|
|
"Combine AArch64 MachineInstrs after legalization", false,
|
||
|
|
false)
|
||
|
|
INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
|
||
|
|
INITIALIZE_PASS_DEPENDENCY(GISelKnownBitsAnalysis)
|
||
|
|
INITIALIZE_PASS_END(AArch64PostLegalizerCombiner, DEBUG_TYPE,
|
||
|
|
"Combine AArch64 MachineInstrs after legalization", false,
|
||
|
|
false)
|
||
|
|
|
||
|
|
namespace llvm {
|
||
|
|
FunctionPass *createAArch64PostLegalizerCombiner(bool IsOptNone) {
|
||
|
|
return new AArch64PostLegalizerCombiner(IsOptNone);
|
||
|
|
}
|
||
|
|
} // end namespace llvm
|