340 lines
19 KiB
TableGen
340 lines
19 KiB
TableGen
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//==- AArch64SchedCortexA55.td - ARM Cortex-A55 Scheduling Definitions -*- tablegen -*-=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the machine model for the ARM Cortex-A55 processors.
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//
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//===----------------------------------------------------------------------===//
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// ===---------------------------------------------------------------------===//
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// The following definitions describe the per-operand machine model.
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// This works with MachineScheduler. See MCSchedModel.h for details.
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// Cortex-A55 machine model for scheduling and other instruction cost heuristics.
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def CortexA55Model : SchedMachineModel {
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let MicroOpBufferSize = 0; // The Cortex-A55 is an in-order processor
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let IssueWidth = 2; // It dual-issues under most circumstances
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let LoadLatency = 4; // Cycles for loads to access the cache. The
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// optimisation guide shows that most loads have
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// a latency of 3, but some have a latency of 4
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// or 5. Setting it 4 looked to be good trade-off.
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let MispredictPenalty = 8; // A branch direction mispredict.
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let PostRAScheduler = 1; // Enable PostRA scheduler pass.
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let CompleteModel = 0; // Covers instructions applicable to Cortex-A55.
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list<Predicate> UnsupportedFeatures = [HasSVE];
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// FIXME: Remove when all errors have been fixed.
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let FullInstRWOverlapCheck = 0;
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}
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//===----------------------------------------------------------------------===//
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// Define each kind of processor resource and number available.
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// Modeling each pipeline as a ProcResource using the BufferSize = 0 since the
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// Cortex-A55 is in-order.
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def CortexA55UnitALU : ProcResource<2> { let BufferSize = 0; } // Int ALU
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def CortexA55UnitMAC : ProcResource<1> { let BufferSize = 0; } // Int MAC, 64-bi wide
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def CortexA55UnitDiv : ProcResource<1> { let BufferSize = 0; } // Int Division, not pipelined
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def CortexA55UnitLd : ProcResource<1> { let BufferSize = 0; } // Load pipe
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def CortexA55UnitSt : ProcResource<1> { let BufferSize = 0; } // Store pipe
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def CortexA55UnitB : ProcResource<1> { let BufferSize = 0; } // Branch
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// The FP DIV/SQRT instructions execute totally differently from the FP ALU
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// instructions, which can mostly be dual-issued; that's why for now we model
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// them with 2 resources.
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def CortexA55UnitFPALU : ProcResource<2> { let BufferSize = 0; } // FP ALU
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def CortexA55UnitFPMAC : ProcResource<2> { let BufferSize = 0; } // FP MAC
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def CortexA55UnitFPDIV : ProcResource<1> { let BufferSize = 0; } // FP Div/SQRT, 64/128
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//===----------------------------------------------------------------------===//
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// Subtarget-specific SchedWrite types
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let SchedModel = CortexA55Model in {
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// These latencies are modeled without taking into account forwarding paths
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// (the software optimisation guide lists latencies taking into account
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// typical forwarding paths).
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def : WriteRes<WriteImm, [CortexA55UnitALU]> { let Latency = 3; } // MOVN, MOVZ
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def : WriteRes<WriteI, [CortexA55UnitALU]> { let Latency = 3; } // ALU
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def : WriteRes<WriteISReg, [CortexA55UnitALU]> { let Latency = 3; } // ALU of Shifted-Reg
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def : WriteRes<WriteIEReg, [CortexA55UnitALU]> { let Latency = 3; } // ALU of Extended-Reg
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def : WriteRes<WriteExtr, [CortexA55UnitALU]> { let Latency = 3; } // EXTR from a reg pair
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def : WriteRes<WriteIS, [CortexA55UnitALU]> { let Latency = 3; } // Shift/Scale
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// MAC
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def : WriteRes<WriteIM32, [CortexA55UnitMAC]> { let Latency = 4; } // 32-bit Multiply
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def : WriteRes<WriteIM64, [CortexA55UnitMAC]> { let Latency = 4; } // 64-bit Multiply
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// Div
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def : WriteRes<WriteID32, [CortexA55UnitDiv]> {
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let Latency = 8; let ResourceCycles = [8];
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}
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def : WriteRes<WriteID64, [CortexA55UnitDiv]> {
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let Latency = 8; let ResourceCycles = [8];
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}
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// Load
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def : WriteRes<WriteLD, [CortexA55UnitLd]> { let Latency = 3; }
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def : WriteRes<WriteLDIdx, [CortexA55UnitLd]> { let Latency = 4; }
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def : WriteRes<WriteLDHi, [CortexA55UnitLd]> { let Latency = 5; }
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// Vector Load - Vector loads take 1-5 cycles to issue. For the WriteVecLd
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// below, choosing the median of 3 which makes the latency 6.
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// An extra cycle is needed to get the swizzling right.
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def : WriteRes<WriteVLD, [CortexA55UnitLd]> { let Latency = 6;
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let ResourceCycles = [3]; }
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def CortexA55WriteVLD1 : SchedWriteRes<[CortexA55UnitLd]> { let Latency = 4; }
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def CortexA55WriteVLD2 : SchedWriteRes<[CortexA55UnitLd]> { let Latency = 5;
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let ResourceCycles = [2]; }
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def CortexA55WriteVLD3 : SchedWriteRes<[CortexA55UnitLd]> { let Latency = 6;
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let ResourceCycles = [3]; }
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def CortexA55WriteVLD4 : SchedWriteRes<[CortexA55UnitLd]> { let Latency = 7;
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let ResourceCycles = [4]; }
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def CortexA55WriteVLD5 : SchedWriteRes<[CortexA55UnitLd]> { let Latency = 8;
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let ResourceCycles = [5]; }
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def CortexA55WriteVLD6 : SchedWriteRes<[CortexA55UnitLd]> { let Latency = 9;
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let ResourceCycles = [6]; }
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def CortexA55WriteVLD7 : SchedWriteRes<[CortexA55UnitLd]> { let Latency = 10;
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let ResourceCycles = [7]; }
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def CortexA55WriteVLD8 : SchedWriteRes<[CortexA55UnitLd]> { let Latency = 11;
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let ResourceCycles = [8]; }
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// Pre/Post Indexing - Performed as part of address generation
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def : WriteRes<WriteAdr, []> { let Latency = 0; }
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// Store
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def : WriteRes<WriteST, [CortexA55UnitSt]> { let Latency = 4; }
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def : WriteRes<WriteSTP, [CortexA55UnitSt]> { let Latency = 4; }
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def : WriteRes<WriteSTIdx, [CortexA55UnitSt]> { let Latency = 4; }
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def : WriteRes<WriteSTX, [CortexA55UnitSt]> { let Latency = 4; }
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// Vector Store - Similar to vector loads, can take 1-3 cycles to issue.
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def : WriteRes<WriteVST, [CortexA55UnitSt]> { let Latency = 5;
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let ResourceCycles = [2];}
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def CortexA55WriteVST1 : SchedWriteRes<[CortexA55UnitSt]> { let Latency = 4; }
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def CortexA55WriteVST2 : SchedWriteRes<[CortexA55UnitSt]> { let Latency = 5;
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let ResourceCycles = [2]; }
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def CortexA55WriteVST3 : SchedWriteRes<[CortexA55UnitSt]> { let Latency = 6;
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let ResourceCycles = [3]; }
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def CortexA55WriteVST4 : SchedWriteRes<[CortexA55UnitSt]> { let Latency = 5;
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let ResourceCycles = [4]; }
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def : WriteRes<WriteAtomic, []> { let Unsupported = 1; }
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// Branch
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def : WriteRes<WriteBr, [CortexA55UnitB]>;
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def : WriteRes<WriteBrReg, [CortexA55UnitB]>;
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def : WriteRes<WriteSys, [CortexA55UnitB]>;
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def : WriteRes<WriteBarrier, [CortexA55UnitB]>;
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def : WriteRes<WriteHint, [CortexA55UnitB]>;
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// FP ALU
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// As WriteF result is produced in F5 and it can be mostly forwarded
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// to consumer at F1, the effectively latency is set as 4.
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def : WriteRes<WriteF, [CortexA55UnitFPALU]> { let Latency = 4; }
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def : WriteRes<WriteFCmp, [CortexA55UnitFPALU]> { let Latency = 3; }
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def : WriteRes<WriteFCvt, [CortexA55UnitFPALU]> { let Latency = 4; }
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def : WriteRes<WriteFCopy, [CortexA55UnitFPALU]> { let Latency = 3; }
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def : WriteRes<WriteFImm, [CortexA55UnitFPALU]> { let Latency = 3; }
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def : WriteRes<WriteV, [CortexA55UnitFPALU]> { let Latency = 4; }
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// FP ALU specific new schedwrite definitions
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def CortexA55WriteFPALU_F3 : SchedWriteRes<[CortexA55UnitFPALU]> { let Latency = 3;}
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def CortexA55WriteFPALU_F4 : SchedWriteRes<[CortexA55UnitFPALU]> { let Latency = 4;}
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def CortexA55WriteFPALU_F5 : SchedWriteRes<[CortexA55UnitFPALU]> { let Latency = 5;}
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// FP Mul, Div, Sqrt. Div/Sqrt are not pipelined
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def : WriteRes<WriteFMul, [CortexA55UnitFPMAC]> { let Latency = 4; }
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def : WriteRes<WriteFDiv, [CortexA55UnitFPDIV]> { let Latency = 22;
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let ResourceCycles = [29]; }
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def CortexA55WriteFMAC : SchedWriteRes<[CortexA55UnitFPMAC]> { let Latency = 4; }
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def CortexA55WriteFDivHP : SchedWriteRes<[CortexA55UnitFPDIV]> { let Latency = 8;
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let ResourceCycles = [5]; }
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def CortexA55WriteFDivSP : SchedWriteRes<[CortexA55UnitFPDIV]> { let Latency = 13;
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let ResourceCycles = [10]; }
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def CortexA55WriteFDivDP : SchedWriteRes<[CortexA55UnitFPDIV]> { let Latency = 22;
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let ResourceCycles = [19]; }
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def CortexA55WriteFSqrtHP : SchedWriteRes<[CortexA55UnitFPDIV]> { let Latency = 8;
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let ResourceCycles = [5]; }
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def CortexA55WriteFSqrtSP : SchedWriteRes<[CortexA55UnitFPDIV]> { let Latency = 12;
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let ResourceCycles = [9]; }
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def CortexA55WriteFSqrtDP : SchedWriteRes<[CortexA55UnitFPDIV]> { let Latency = 22;
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let ResourceCycles = [19]; }
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//===----------------------------------------------------------------------===//
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// Subtarget-specific SchedRead types.
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def : ReadAdvance<ReadVLD, 0>;
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def : ReadAdvance<ReadExtrHi, 1>;
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def : ReadAdvance<ReadAdrBase, 1>;
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// ALU - ALU input operands are generally needed in EX1. An operand produced in
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// in say EX2 can be forwarded for consumption to ALU in EX1, thereby
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// allowing back-to-back ALU operations such as add. If an operand requires
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// a shift, it will, however, be required in ISS stage.
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def : ReadAdvance<ReadI, 2, [WriteImm,WriteI,
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WriteISReg, WriteIEReg,WriteIS,
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WriteID32,WriteID64,
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WriteIM32,WriteIM64]>;
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// Shifted operand
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def CortexA55ReadShifted : SchedReadAdvance<1, [WriteImm,WriteI,
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WriteISReg, WriteIEReg,WriteIS,
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WriteID32,WriteID64,
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WriteIM32,WriteIM64]>;
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def CortexA55ReadNotShifted : SchedReadAdvance<2, [WriteImm,WriteI,
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WriteISReg, WriteIEReg,WriteIS,
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WriteID32,WriteID64,
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WriteIM32,WriteIM64]>;
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def CortexA55ReadISReg : SchedReadVariant<[
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SchedVar<RegShiftedPred, [CortexA55ReadShifted]>,
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SchedVar<NoSchedPred, [CortexA55ReadNotShifted]>]>;
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def : SchedAlias<ReadISReg, CortexA55ReadISReg>;
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def CortexA55ReadIEReg : SchedReadVariant<[
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SchedVar<RegExtendedPred, [CortexA55ReadShifted]>,
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SchedVar<NoSchedPred, [CortexA55ReadNotShifted]>]>;
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def : SchedAlias<ReadIEReg, CortexA55ReadIEReg>;
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// MUL
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def : ReadAdvance<ReadIM, 1, [WriteImm,WriteI,
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WriteISReg, WriteIEReg,WriteIS,
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WriteID32,WriteID64,
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WriteIM32,WriteIM64]>;
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def : ReadAdvance<ReadIMA, 2, [WriteImm,WriteI,
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WriteISReg, WriteIEReg,WriteIS,
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WriteID32,WriteID64,
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WriteIM32,WriteIM64]>;
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// Div
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def : ReadAdvance<ReadID, 1, [WriteImm,WriteI,
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WriteISReg, WriteIEReg,WriteIS,
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WriteID32,WriteID64,
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WriteIM32,WriteIM64]>;
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//===----------------------------------------------------------------------===//
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// Subtarget-specific InstRWs.
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//---
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// Miscellaneous
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//---
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def : InstRW<[CortexA55WriteVLD2,CortexA55WriteVLD1], (instregex "LDP.*")>;
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def : InstRW<[WriteI], (instrs COPY)>;
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//---
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// Vector Loads - 64-bit per cycle
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//---
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// 1-element structures
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def : InstRW<[CortexA55WriteVLD1], (instregex "LD1i(8|16|32|64)$")>; // single element
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def : InstRW<[CortexA55WriteVLD1], (instregex "LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; // replicate
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def : InstRW<[CortexA55WriteVLD1], (instregex "LD1Onev(8b|4h|2s|1d)$")>;
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def : InstRW<[CortexA55WriteVLD2], (instregex "LD1Onev(16b|8h|4s|2d)$")>;
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def : InstRW<[CortexA55WriteVLD2], (instregex "LD1Twov(8b|4h|2s|1d)$")>; // multiple structures
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def : InstRW<[CortexA55WriteVLD4], (instregex "LD1Twov(16b|8h|4s|2d)$")>;
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def : InstRW<[CortexA55WriteVLD3], (instregex "LD1Threev(8b|4h|2s|1d)$")>;
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def : InstRW<[CortexA55WriteVLD6], (instregex "LD1Threev(16b|8h|4s|2d)$")>;
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def : InstRW<[CortexA55WriteVLD4], (instregex "LD1Fourv(8b|4h|2s|1d)$")>;
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def : InstRW<[CortexA55WriteVLD8], (instregex "LD1Fourv(16b|8h|4s|2d)$")>;
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def : InstRW<[CortexA55WriteVLD1, WriteAdr], (instregex "LD1i(8|16|32|64)_POST$")>;
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def : InstRW<[CortexA55WriteVLD1, WriteAdr], (instregex "LD1Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
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def : InstRW<[CortexA55WriteVLD1, WriteAdr], (instregex "LD1Onev(8b|4h|2s|1d)_POST$")>;
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def : InstRW<[CortexA55WriteVLD2, WriteAdr], (instregex "LD1Onev(16b|8h|4s|2d)_POST$")>;
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def : InstRW<[CortexA55WriteVLD2, WriteAdr], (instregex "LD1Twov(8b|4h|2s|1d)_POST$")>;
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def : InstRW<[CortexA55WriteVLD4, WriteAdr], (instregex "LD1Twov(16b|8h|4s|2d)_POST$")>;
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def : InstRW<[CortexA55WriteVLD3, WriteAdr], (instregex "LD1Threev(8b|4h|2s|1d)_POST$")>;
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def : InstRW<[CortexA55WriteVLD6, WriteAdr], (instregex "LD1Threev(16b|8h|4s|2d)_POST$")>;
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def : InstRW<[CortexA55WriteVLD4, WriteAdr], (instregex "LD1Fourv(8b|4h|2s|1d)_POST$")>;
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def : InstRW<[CortexA55WriteVLD8, WriteAdr], (instregex "LD1Fourv(16b|8h|4s|2d)_POST$")>;
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// 2-element structures
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def : InstRW<[CortexA55WriteVLD2], (instregex "LD2i(8|16|32|64)$")>;
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def : InstRW<[CortexA55WriteVLD2], (instregex "LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
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def : InstRW<[CortexA55WriteVLD2], (instregex "LD2Twov(8b|4h|2s)$")>;
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def : InstRW<[CortexA55WriteVLD4], (instregex "LD2Twov(16b|8h|4s|2d)$")>;
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def : InstRW<[CortexA55WriteVLD2, WriteAdr], (instregex "LD2i(8|16|32|64)(_POST)?$")>;
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def : InstRW<[CortexA55WriteVLD2, WriteAdr], (instregex "LD2Rv(8b|4h|2s|1d|16b|8h|4s|2d)(_POST)?$")>;
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def : InstRW<[CortexA55WriteVLD2, WriteAdr], (instregex "LD2Twov(8b|4h|2s)(_POST)?$")>;
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def : InstRW<[CortexA55WriteVLD4, WriteAdr], (instregex "LD2Twov(16b|8h|4s|2d)(_POST)?$")>;
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// 3-element structures
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def : InstRW<[CortexA55WriteVLD2], (instregex "LD3i(8|16|32|64)$")>;
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def : InstRW<[CortexA55WriteVLD2], (instregex "LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
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def : InstRW<[CortexA55WriteVLD3], (instregex "LD3Threev(8b|4h|2s|1d)$")>;
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def : InstRW<[CortexA55WriteVLD6], (instregex "LD3Threev(16b|8h|4s|2d)$")>;
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def : InstRW<[CortexA55WriteVLD2, WriteAdr], (instregex "LD3i(8|16|32|64)_POST$")>;
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def : InstRW<[CortexA55WriteVLD2, WriteAdr], (instregex "LD3Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
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def : InstRW<[CortexA55WriteVLD3, WriteAdr], (instregex "LD3Threev(8b|4h|2s|1d)_POST$")>;
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def : InstRW<[CortexA55WriteVLD6, WriteAdr], (instregex "LD3Threev(16b|8h|4s|2d)_POST$")>;
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// 4-element structures
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def : InstRW<[CortexA55WriteVLD2], (instregex "LD4i(8|16|32|64)$")>; // load single 4-el structure to one lane of 4 regs.
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def : InstRW<[CortexA55WriteVLD2], (instregex "LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)$")>; // load single 4-el structure, replicate to all lanes of 4 regs.
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def : InstRW<[CortexA55WriteVLD4], (instregex "LD4Fourv(8b|4h|2s|1d)$")>; // load multiple 4-el structures to 4 regs.
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def : InstRW<[CortexA55WriteVLD8], (instregex "LD4Fourv(16b|8h|4s|2d)$")>;
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def : InstRW<[CortexA55WriteVLD2, WriteAdr], (instregex "LD4i(8|16|32|64)_POST$")>;
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def : InstRW<[CortexA55WriteVLD2, WriteAdr], (instregex "LD4Rv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
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def : InstRW<[CortexA55WriteVLD4, WriteAdr], (instregex "LD4Fourv(8b|4h|2s|1d)_POST$")>;
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def : InstRW<[CortexA55WriteVLD8, WriteAdr], (instregex "LD4Fourv(16b|8h|4s|2d)_POST$")>;
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//---
|
||
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// Vector Stores
|
||
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//---
|
||
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def : InstRW<[CortexA55WriteVST1], (instregex "ST1i(8|16|32|64)$")>;
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def : InstRW<[CortexA55WriteVST1], (instregex "ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
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||
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def : InstRW<[CortexA55WriteVST1], (instregex "ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
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||
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def : InstRW<[CortexA55WriteVST2], (instregex "ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
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||
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def : InstRW<[CortexA55WriteVST4], (instregex "ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
|
||
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def : InstRW<[CortexA55WriteVST1, WriteAdr], (instregex "ST1i(8|16|32|64)_POST$")>;
|
||
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def : InstRW<[CortexA55WriteVST1, WriteAdr], (instregex "ST1Onev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
|
||
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|
def : InstRW<[CortexA55WriteVST1, WriteAdr], (instregex "ST1Twov(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
|
||
|
|
def : InstRW<[CortexA55WriteVST2, WriteAdr], (instregex "ST1Threev(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
|
||
|
|
def : InstRW<[CortexA55WriteVST4, WriteAdr], (instregex "ST1Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
|
||
|
|
|
||
|
|
def : InstRW<[CortexA55WriteVST2], (instregex "ST2i(8|16|32|64)$")>;
|
||
|
|
def : InstRW<[CortexA55WriteVST2], (instregex "ST2Twov(8b|4h|2s)$")>;
|
||
|
|
def : InstRW<[CortexA55WriteVST4], (instregex "ST2Twov(16b|8h|4s|2d)$")>;
|
||
|
|
def : InstRW<[CortexA55WriteVST2, WriteAdr], (instregex "ST2i(8|16|32|64)_POST$")>;
|
||
|
|
def : InstRW<[CortexA55WriteVST2, WriteAdr], (instregex "ST2Twov(8b|4h|2s)_POST$")>;
|
||
|
|
def : InstRW<[CortexA55WriteVST4, WriteAdr], (instregex "ST2Twov(16b|8h|4s|2d)_POST$")>;
|
||
|
|
|
||
|
|
def : InstRW<[CortexA55WriteVST2], (instregex "ST3i(8|16|32|64)$")>;
|
||
|
|
def : InstRW<[CortexA55WriteVST4], (instregex "ST3Threev(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
|
||
|
|
def : InstRW<[CortexA55WriteVST2, WriteAdr], (instregex "ST3i(8|16|32|64)_POST$")>;
|
||
|
|
def : InstRW<[CortexA55WriteVST4, WriteAdr], (instregex "ST3Threev(8b|4h|2s|1d|2d|16b|8h|4s|4d)_POST$")>;
|
||
|
|
|
||
|
|
def : InstRW<[CortexA55WriteVST2], (instregex "ST4i(8|16|32|64)$")>;
|
||
|
|
def : InstRW<[CortexA55WriteVST4], (instregex "ST4Fourv(8b|4h|2s|1d|16b|8h|4s|2d)$")>;
|
||
|
|
def : InstRW<[CortexA55WriteVST2, WriteAdr], (instregex "ST4i(8|16|32|64)_POST$")>;
|
||
|
|
def : InstRW<[CortexA55WriteVST4, WriteAdr], (instregex "ST4Fourv(8b|4h|2s|1d|16b|8h|4s|2d)_POST$")>;
|
||
|
|
|
||
|
|
//---
|
||
|
|
// Floating Point Conversions, MAC, DIV, SQRT
|
||
|
|
//---
|
||
|
|
def : InstRW<[CortexA55WriteFPALU_F3], (instregex "^FCVT[ALMNPZ][SU](S|U)?(W|X)")>;
|
||
|
|
def : InstRW<[CortexA55WriteFPALU_F4], (instregex "^FCVT(X)?[ALMNPXZ](S|U|N)?v")>;
|
||
|
|
|
||
|
|
def : InstRW<[CortexA55WriteFPALU_F4], (instregex "^(S|U)CVTF(S|U)(W|X)(H|S|D)")>;
|
||
|
|
def : InstRW<[CortexA55WriteFPALU_F4], (instregex "^(S|U)CVTF(h|s|d)")>;
|
||
|
|
def : InstRW<[CortexA55WriteFPALU_F4], (instregex "^(S|U)CVTFv")>;
|
||
|
|
|
||
|
|
def : InstRW<[CortexA55WriteFMAC], (instregex "^FN?M(ADD|SUB).*")>;
|
||
|
|
def : InstRW<[CortexA55WriteFMAC], (instregex "^FML(A|S).*")>;
|
||
|
|
def : InstRW<[CortexA55WriteFDivHP], (instrs FDIVHrr)>;
|
||
|
|
def : InstRW<[CortexA55WriteFDivSP], (instrs FDIVSrr)>;
|
||
|
|
def : InstRW<[CortexA55WriteFDivDP], (instrs FDIVDrr)>;
|
||
|
|
def : InstRW<[CortexA55WriteFDivHP], (instregex "^FDIVv.*16$")>;
|
||
|
|
def : InstRW<[CortexA55WriteFDivSP], (instregex "^FDIVv.*32$")>;
|
||
|
|
def : InstRW<[CortexA55WriteFDivDP], (instregex "^FDIVv.*64$")>;
|
||
|
|
def : InstRW<[CortexA55WriteFSqrtHP], (instregex "^.*SQRT.*16$")>;
|
||
|
|
def : InstRW<[CortexA55WriteFSqrtSP], (instregex "^.*SQRT.*32$")>;
|
||
|
|
def : InstRW<[CortexA55WriteFSqrtDP], (instregex "^.*SQRT.*64$")>;
|
||
|
|
}
|