1264 lines
57 KiB
TableGen
1264 lines
57 KiB
TableGen
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//=- AArch64.td - Describe the AArch64 Target Machine --------*- tablegen -*-=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Target-independent interfaces which we are implementing.
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//===----------------------------------------------------------------------===//
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include "llvm/Target/Target.td"
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//===----------------------------------------------------------------------===//
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// AArch64 Subtarget features.
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//
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def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8", "true",
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"Enable ARMv8 FP">;
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def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
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"Enable Advanced SIMD instructions", [FeatureFPARMv8]>;
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def FeatureSM4 : SubtargetFeature<
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"sm4", "HasSM4", "true",
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"Enable SM3 and SM4 support", [FeatureNEON]>;
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def FeatureSHA2 : SubtargetFeature<
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"sha2", "HasSHA2", "true",
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"Enable SHA1 and SHA256 support", [FeatureNEON]>;
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def FeatureSHA3 : SubtargetFeature<
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"sha3", "HasSHA3", "true",
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"Enable SHA512 and SHA3 support", [FeatureNEON, FeatureSHA2]>;
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def FeatureAES : SubtargetFeature<
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"aes", "HasAES", "true",
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"Enable AES support", [FeatureNEON]>;
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// Crypto has been split up and any combination is now valid (see the
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// crypto definitions above). Also, crypto is now context sensitive:
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// it has a different meaning for e.g. Armv8.4 than it has for Armv8.2.
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// Therefore, we rely on Clang, the user interacing tool, to pass on the
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// appropriate crypto options. But here in the backend, crypto has very little
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// meaning anymore. We kept the Crypto definition here for backward
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// compatibility, and now imply features SHA2 and AES, which was the
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// "traditional" meaning of Crypto.
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def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
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"Enable cryptographic instructions", [FeatureNEON, FeatureSHA2, FeatureAES]>;
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def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
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"Enable ARMv8 CRC-32 checksum instructions">;
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def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true",
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"Enable ARMv8 Reliability, Availability and Serviceability Extensions">;
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def FeatureLSE : SubtargetFeature<"lse", "HasLSE", "true",
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"Enable ARMv8.1 Large System Extension (LSE) atomic instructions">;
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def FeatureOutlineAtomics : SubtargetFeature<"outline-atomics", "OutlineAtomics", "true",
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"Enable out of line atomics to support LSE instructions">;
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def FeatureRDM : SubtargetFeature<"rdm", "HasRDM", "true",
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"Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions">;
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def FeaturePAN : SubtargetFeature<
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"pan", "HasPAN", "true",
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"Enables ARM v8.1 Privileged Access-Never extension">;
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def FeatureLOR : SubtargetFeature<
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"lor", "HasLOR", "true",
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"Enables ARM v8.1 Limited Ordering Regions extension">;
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def FeatureCONTEXTIDREL2 : SubtargetFeature<"CONTEXTIDREL2", "HasCONTEXTIDREL2",
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"true", "Enable RW operand CONTEXTIDR_EL2" >;
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def FeatureVH : SubtargetFeature<"vh", "HasVH", "true",
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"Enables ARM v8.1 Virtual Host extension", [FeatureCONTEXTIDREL2] >;
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def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
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"Enable ARMv8 PMUv3 Performance Monitors extension">;
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def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
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"Full FP16", [FeatureFPARMv8]>;
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def FeatureFP16FML : SubtargetFeature<"fp16fml", "HasFP16FML", "true",
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"Enable FP16 FML instructions", [FeatureFullFP16]>;
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def FeatureSPE : SubtargetFeature<"spe", "HasSPE", "true",
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"Enable Statistical Profiling extension">;
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def FeaturePAN_RWV : SubtargetFeature<
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"pan-rwv", "HasPAN_RWV", "true",
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"Enable v8.2 PAN s1e1R and s1e1W Variants",
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[FeaturePAN]>;
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// UAO PState
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def FeaturePsUAO : SubtargetFeature< "uaops", "HasPsUAO", "true",
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"Enable v8.2 UAO PState">;
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def FeatureCCPP : SubtargetFeature<"ccpp", "HasCCPP",
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"true", "Enable v8.2 data Cache Clean to Point of Persistence" >;
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def FeatureSVE : SubtargetFeature<"sve", "HasSVE", "true",
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"Enable Scalable Vector Extension (SVE) instructions", [FeatureFullFP16]>;
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// This flag is currently still labeled as Experimental, but when fully
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// implemented this should tell the compiler to use the zeroing pseudos to
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// benefit from the reverse instructions (e.g. SUB vs SUBR) if the inactive
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// lanes are known to be zero. The pseudos will then be expanded using the
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// MOVPRFX instruction to zero the inactive lanes. This feature should only be
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// enabled if MOVPRFX instructions are known to merge with the destructive
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// operations they prefix.
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//
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// This feature could similarly be extended to support cheap merging of _any_
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// value into the inactive lanes using the MOVPRFX instruction that uses
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// merging-predication.
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def FeatureExperimentalZeroingPseudos
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: SubtargetFeature<"use-experimental-zeroing-pseudos",
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"UseExperimentalZeroingPseudos", "true",
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"Hint to the compiler that the MOVPRFX instruction is "
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"merged with destructive operations",
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[]>;
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def FeatureSVE2 : SubtargetFeature<"sve2", "HasSVE2", "true",
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"Enable Scalable Vector Extension 2 (SVE2) instructions", [FeatureSVE]>;
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def FeatureSVE2AES : SubtargetFeature<"sve2-aes", "HasSVE2AES", "true",
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"Enable AES SVE2 instructions", [FeatureSVE2, FeatureAES]>;
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def FeatureSVE2SM4 : SubtargetFeature<"sve2-sm4", "HasSVE2SM4", "true",
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"Enable SM4 SVE2 instructions", [FeatureSVE2, FeatureSM4]>;
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def FeatureSVE2SHA3 : SubtargetFeature<"sve2-sha3", "HasSVE2SHA3", "true",
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"Enable SHA3 SVE2 instructions", [FeatureSVE2, FeatureSHA3]>;
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def FeatureSVE2BitPerm : SubtargetFeature<"sve2-bitperm", "HasSVE2BitPerm", "true",
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"Enable bit permutation SVE2 instructions", [FeatureSVE2]>;
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def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
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"Has zero-cycle register moves">;
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def FeatureZCZeroingGP : SubtargetFeature<"zcz-gp", "HasZeroCycleZeroingGP", "true",
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"Has zero-cycle zeroing instructions for generic registers">;
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def FeatureZCZeroingFP : SubtargetFeature<"zcz-fp", "HasZeroCycleZeroingFP", "true",
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"Has zero-cycle zeroing instructions for FP registers">;
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def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
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"Has zero-cycle zeroing instructions",
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[FeatureZCZeroingGP, FeatureZCZeroingFP]>;
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/// ... but the floating-point version doesn't quite work in rare cases on older
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/// CPUs.
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def FeatureZCZeroingFPWorkaround : SubtargetFeature<"zcz-fp-workaround",
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"HasZeroCycleZeroingFPWorkaround", "true",
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"The zero-cycle floating-point zeroing instruction has a bug">;
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def FeatureStrictAlign : SubtargetFeature<"strict-align",
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"StrictAlign", "true",
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"Disallow all unaligned memory "
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"access">;
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foreach i = {1-7,9-15,18,20-28,30} in
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def FeatureReserveX#i : SubtargetFeature<"reserve-x"#i, "ReserveXRegister["#i#"]", "true",
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"Reserve X"#i#", making it unavailable "
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"as a GPR">;
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foreach i = {8-15,18} in
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def FeatureCallSavedX#i : SubtargetFeature<"call-saved-x"#i,
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"CustomCallSavedXRegs["#i#"]", "true", "Make X"#i#" callee saved.">;
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def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true",
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"Use alias analysis during codegen">;
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def FeatureBalanceFPOps : SubtargetFeature<"balance-fp-ops", "BalanceFPOps",
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"true",
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"balance mix of odd and even D-registers for fp multiply(-accumulate) ops">;
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def FeaturePredictableSelectIsExpensive : SubtargetFeature<
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"predictable-select-expensive", "PredictableSelectIsExpensive", "true",
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"Prefer likely predicted branches over selects">;
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def FeatureCustomCheapAsMoveHandling : SubtargetFeature<"custom-cheap-as-move",
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"CustomAsCheapAsMove", "true",
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"Use custom handling of cheap instructions">;
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def FeatureExynosCheapAsMoveHandling : SubtargetFeature<"exynos-cheap-as-move",
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"ExynosAsCheapAsMove", "true",
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"Use Exynos specific handling of cheap instructions",
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[FeatureCustomCheapAsMoveHandling]>;
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def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
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"UsePostRAScheduler", "true", "Schedule again after register allocation">;
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def FeatureSlowMisaligned128Store : SubtargetFeature<"slow-misaligned-128store",
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"Misaligned128StoreIsSlow", "true", "Misaligned 128 bit stores are slow">;
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def FeatureSlowPaired128 : SubtargetFeature<"slow-paired-128",
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"Paired128IsSlow", "true", "Paired 128 bit loads and stores are slow">;
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def FeatureSlowSTRQro : SubtargetFeature<"slow-strqro-store", "STRQroIsSlow",
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"true", "STR of Q register with register offset is slow">;
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def FeatureAlternateSExtLoadCVTF32Pattern : SubtargetFeature<
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"alternate-sextload-cvt-f32-pattern", "UseAlternateSExtLoadCVTF32Pattern",
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"true", "Use alternative pattern for sextload convert to f32">;
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def FeatureArithmeticBccFusion : SubtargetFeature<
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"arith-bcc-fusion", "HasArithmeticBccFusion", "true",
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"CPU fuses arithmetic+bcc operations">;
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def FeatureArithmeticCbzFusion : SubtargetFeature<
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"arith-cbz-fusion", "HasArithmeticCbzFusion", "true",
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"CPU fuses arithmetic + cbz/cbnz operations">;
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def FeatureCmpBccFusion : SubtargetFeature<
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"cmp-bcc-fusion", "HasCmpBccFusion", "true",
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"CPU fuses cmp+bcc operations">;
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def FeatureFuseAddress : SubtargetFeature<
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"fuse-address", "HasFuseAddress", "true",
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"CPU fuses address generation and memory operations">;
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def FeatureFuseAES : SubtargetFeature<
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"fuse-aes", "HasFuseAES", "true",
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"CPU fuses AES crypto operations">;
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def FeatureFuseArithmeticLogic : SubtargetFeature<
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"fuse-arith-logic", "HasFuseArithmeticLogic", "true",
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"CPU fuses arithmetic and logic operations">;
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def FeatureFuseCCSelect : SubtargetFeature<
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"fuse-csel", "HasFuseCCSelect", "true",
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"CPU fuses conditional select operations">;
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def FeatureFuseCryptoEOR : SubtargetFeature<
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"fuse-crypto-eor", "HasFuseCryptoEOR", "true",
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"CPU fuses AES/PMULL and EOR operations">;
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def FeatureFuseLiterals : SubtargetFeature<
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"fuse-literals", "HasFuseLiterals", "true",
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"CPU fuses literal generation operations">;
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def FeatureDisableLatencySchedHeuristic : SubtargetFeature<
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"disable-latency-sched-heuristic", "DisableLatencySchedHeuristic", "true",
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"Disable latency scheduling heuristic">;
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def FeatureForce32BitJumpTables
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: SubtargetFeature<"force-32bit-jump-tables", "Force32BitJumpTables", "true",
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"Force jump table entries to be 32-bits wide except at MinSize">;
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def FeatureRCPC : SubtargetFeature<"rcpc", "HasRCPC", "true",
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"Enable support for RCPC extension">;
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def FeatureUseRSqrt : SubtargetFeature<
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"use-reciprocal-square-root", "UseRSqrt", "true",
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"Use the reciprocal square root approximation">;
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def FeatureDotProd : SubtargetFeature<
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"dotprod", "HasDotProd", "true",
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"Enable dot product support">;
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def FeaturePAuth : SubtargetFeature<
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"pauth", "HasPAuth", "true",
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"Enable v8.3-A Pointer Authentication extension">;
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def FeatureJS : SubtargetFeature<
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"jsconv", "HasJS", "true",
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"Enable v8.3-A JavaScript FP conversion instructions",
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[FeatureFPARMv8]>;
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def FeatureCCIDX : SubtargetFeature<
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"ccidx", "HasCCIDX", "true",
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"Enable v8.3-A Extend of the CCSIDR number of sets">;
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def FeatureComplxNum : SubtargetFeature<
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"complxnum", "HasComplxNum", "true",
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"Enable v8.3-A Floating-point complex number support",
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[FeatureNEON]>;
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def FeatureNV : SubtargetFeature<
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"nv", "HasNV", "true",
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"Enable v8.4-A Nested Virtualization Enchancement">;
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def FeatureMPAM : SubtargetFeature<
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"mpam", "HasMPAM", "true",
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"Enable v8.4-A Memory system Partitioning and Monitoring extension">;
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def FeatureDIT : SubtargetFeature<
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"dit", "HasDIT", "true",
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"Enable v8.4-A Data Independent Timing instructions">;
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def FeatureTRACEV8_4 : SubtargetFeature<
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"tracev8.4", "HasTRACEV8_4", "true",
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"Enable v8.4-A Trace extension">;
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def FeatureAM : SubtargetFeature<
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"am", "HasAM", "true",
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"Enable v8.4-A Activity Monitors extension">;
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def FeatureAMVS : SubtargetFeature<
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"amvs", "HasAMVS", "true",
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"Enable v8.6-A Activity Monitors Virtualization support",
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[FeatureAM]>;
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def FeatureSEL2 : SubtargetFeature<
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"sel2", "HasSEL2", "true",
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"Enable v8.4-A Secure Exception Level 2 extension">;
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def FeaturePMU : SubtargetFeature<
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"pmu", "HasPMU", "true",
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"Enable v8.4-A PMU extension">;
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def FeatureTLB_RMI : SubtargetFeature<
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"tlb-rmi", "HasTLB_RMI", "true",
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"Enable v8.4-A TLB Range and Maintenance Instructions">;
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def FeatureFlagM : SubtargetFeature<
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"flagm", "HasFlagM", "true",
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"Enable v8.4-A Flag Manipulation Instructions">;
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||
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// 8.4 RCPC enchancements: LDAPR & STLR instructions with Immediate Offset
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def FeatureRCPC_IMMO : SubtargetFeature<"rcpc-immo", "HasRCPC_IMMO", "true",
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"Enable v8.4-A RCPC instructions with Immediate Offsets",
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[FeatureRCPC]>;
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|
|
def FeatureNoNegativeImmediates : SubtargetFeature<"no-neg-immediates",
|
||
|
|
"NegativeImmediates", "false",
|
||
|
|
"Convert immediates and instructions "
|
||
|
|
"to their negated or complemented "
|
||
|
|
"equivalent when the immediate does "
|
||
|
|
"not fit in the encoding.">;
|
||
|
|
|
||
|
|
def FeatureLSLFast : SubtargetFeature<
|
||
|
|
"lsl-fast", "HasLSLFast", "true",
|
||
|
|
"CPU has a fastpath logical shift of up to 3 places">;
|
||
|
|
|
||
|
|
def FeatureAggressiveFMA :
|
||
|
|
SubtargetFeature<"aggressive-fma",
|
||
|
|
"HasAggressiveFMA",
|
||
|
|
"true",
|
||
|
|
"Enable Aggressive FMA for floating-point.">;
|
||
|
|
|
||
|
|
def FeatureAltFPCmp : SubtargetFeature<"altnzcv", "HasAlternativeNZCV", "true",
|
||
|
|
"Enable alternative NZCV format for floating point comparisons">;
|
||
|
|
|
||
|
|
def FeatureFRInt3264 : SubtargetFeature<"fptoint", "HasFRInt3264", "true",
|
||
|
|
"Enable FRInt[32|64][Z|X] instructions that round a floating-point number to "
|
||
|
|
"an integer (in FP format) forcing it to fit into a 32- or 64-bit int" >;
|
||
|
|
|
||
|
|
def FeatureSpecRestrict : SubtargetFeature<"specrestrict", "HasSpecRestrict",
|
||
|
|
"true", "Enable architectural speculation restriction" >;
|
||
|
|
|
||
|
|
def FeatureSB : SubtargetFeature<"sb", "HasSB",
|
||
|
|
"true", "Enable v8.5 Speculation Barrier" >;
|
||
|
|
|
||
|
|
def FeatureSSBS : SubtargetFeature<"ssbs", "HasSSBS",
|
||
|
|
"true", "Enable Speculative Store Bypass Safe bit" >;
|
||
|
|
|
||
|
|
def FeaturePredRes : SubtargetFeature<"predres", "HasPredRes", "true",
|
||
|
|
"Enable v8.5a execution and data prediction invalidation instructions" >;
|
||
|
|
|
||
|
|
def FeatureCacheDeepPersist : SubtargetFeature<"ccdp", "HasCCDP",
|
||
|
|
"true", "Enable v8.5 Cache Clean to Point of Deep Persistence" >;
|
||
|
|
|
||
|
|
def FeatureBranchTargetId : SubtargetFeature<"bti", "HasBTI",
|
||
|
|
"true", "Enable Branch Target Identification" >;
|
||
|
|
|
||
|
|
def FeatureRandGen : SubtargetFeature<"rand", "HasRandGen",
|
||
|
|
"true", "Enable Random Number generation instructions" >;
|
||
|
|
|
||
|
|
def FeatureMTE : SubtargetFeature<"mte", "HasMTE",
|
||
|
|
"true", "Enable Memory Tagging Extension" >;
|
||
|
|
|
||
|
|
def FeatureTRBE : SubtargetFeature<"trbe", "HasTRBE",
|
||
|
|
"true", "Enable Trace Buffer Extension">;
|
||
|
|
|
||
|
|
def FeatureETE : SubtargetFeature<"ete", "HasETE",
|
||
|
|
"true", "Enable Embedded Trace Extension",
|
||
|
|
[FeatureTRBE]>;
|
||
|
|
|
||
|
|
def FeatureTME : SubtargetFeature<"tme", "HasTME",
|
||
|
|
"true", "Enable Transactional Memory Extension" >;
|
||
|
|
|
||
|
|
def FeatureTaggedGlobals : SubtargetFeature<"tagged-globals",
|
||
|
|
"AllowTaggedGlobals",
|
||
|
|
"true", "Use an instruction sequence for taking the address of a global "
|
||
|
|
"that allows a memory tag in the upper address bits">;
|
||
|
|
|
||
|
|
def FeatureBF16 : SubtargetFeature<"bf16", "HasBF16",
|
||
|
|
"true", "Enable BFloat16 Extension" >;
|
||
|
|
|
||
|
|
def FeatureMatMulInt8 : SubtargetFeature<"i8mm", "HasMatMulInt8",
|
||
|
|
"true", "Enable Matrix Multiply Int8 Extension">;
|
||
|
|
|
||
|
|
def FeatureMatMulFP32 : SubtargetFeature<"f32mm", "HasMatMulFP32",
|
||
|
|
"true", "Enable Matrix Multiply FP32 Extension", [FeatureSVE]>;
|
||
|
|
|
||
|
|
def FeatureMatMulFP64 : SubtargetFeature<"f64mm", "HasMatMulFP64",
|
||
|
|
"true", "Enable Matrix Multiply FP64 Extension", [FeatureSVE]>;
|
||
|
|
|
||
|
|
def FeatureXS : SubtargetFeature<"xs", "HasXS",
|
||
|
|
"true", "Enable Armv8.7-A limited-TLB-maintenance instruction">;
|
||
|
|
|
||
|
|
def FeatureWFxT : SubtargetFeature<"wfxt", "HasWFxT",
|
||
|
|
"true", "Enable Armv8.7-A WFET and WFIT instruction">;
|
||
|
|
|
||
|
|
def FeatureHCX : SubtargetFeature<
|
||
|
|
"hcx", "HasHCX", "true", "Enable Armv8.7-A HCRX_EL2 system register">;
|
||
|
|
|
||
|
|
def FeatureLS64 : SubtargetFeature<"ls64", "HasLS64",
|
||
|
|
"true", "Enable Armv8.7-A LD64B/ST64B Accelerator Extension">;
|
||
|
|
|
||
|
|
def FeatureBRBE : SubtargetFeature<"brbe", "HasBRBE",
|
||
|
|
"true", "Enable Branch Record Buffer Extension">;
|
||
|
|
|
||
|
|
def FeatureSPE_EEF : SubtargetFeature<"spe-eef", "HasSPE_EEF",
|
||
|
|
"true", "Enable extra register in the Statistical Profiling Extension">;
|
||
|
|
|
||
|
|
def FeatureFineGrainedTraps : SubtargetFeature<"fgt", "HasFineGrainedTraps",
|
||
|
|
"true", "Enable fine grained virtualization traps extension">;
|
||
|
|
|
||
|
|
def FeatureEnhancedCounterVirtualization :
|
||
|
|
SubtargetFeature<"ecv", "HasEnhancedCounterVirtualization",
|
||
|
|
"true", "Enable enhanced counter virtualization extension">;
|
||
|
|
|
||
|
|
//===----------------------------------------------------------------------===//
|
||
|
|
// Architectures.
|
||
|
|
//
|
||
|
|
|
||
|
|
def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
|
||
|
|
"Support ARM v8.1a instructions", [FeatureCRC, FeatureLSE, FeatureRDM,
|
||
|
|
FeaturePAN, FeatureLOR, FeatureVH]>;
|
||
|
|
|
||
|
|
def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
|
||
|
|
"Support ARM v8.2a instructions", [HasV8_1aOps, FeaturePsUAO,
|
||
|
|
FeaturePAN_RWV, FeatureRAS, FeatureCCPP]>;
|
||
|
|
|
||
|
|
def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true",
|
||
|
|
"Support ARM v8.3a instructions", [HasV8_2aOps, FeatureRCPC, FeaturePAuth,
|
||
|
|
FeatureJS, FeatureCCIDX, FeatureComplxNum]>;
|
||
|
|
|
||
|
|
def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true",
|
||
|
|
"Support ARM v8.4a instructions", [HasV8_3aOps, FeatureDotProd,
|
||
|
|
FeatureNV, FeatureMPAM, FeatureDIT,
|
||
|
|
FeatureTRACEV8_4, FeatureAM, FeatureSEL2, FeaturePMU, FeatureTLB_RMI,
|
||
|
|
FeatureFlagM, FeatureRCPC_IMMO]>;
|
||
|
|
|
||
|
|
def HasV8_5aOps : SubtargetFeature<
|
||
|
|
"v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions",
|
||
|
|
[HasV8_4aOps, FeatureAltFPCmp, FeatureFRInt3264, FeatureSpecRestrict,
|
||
|
|
FeatureSSBS, FeatureSB, FeaturePredRes, FeatureCacheDeepPersist,
|
||
|
|
FeatureBranchTargetId]>;
|
||
|
|
|
||
|
|
def HasV8_6aOps : SubtargetFeature<
|
||
|
|
"v8.6a", "HasV8_6aOps", "true", "Support ARM v8.6a instructions",
|
||
|
|
[HasV8_5aOps, FeatureAMVS, FeatureBF16, FeatureFineGrainedTraps,
|
||
|
|
FeatureEnhancedCounterVirtualization, FeatureMatMulInt8]>;
|
||
|
|
|
||
|
|
def HasV8_7aOps : SubtargetFeature<
|
||
|
|
"v8.7a", "HasV8_7aOps", "true", "Support ARM v8.7a instructions",
|
||
|
|
[HasV8_6aOps, FeatureXS, FeatureWFxT, FeatureHCX]>;
|
||
|
|
|
||
|
|
def HasV8_0rOps : SubtargetFeature<
|
||
|
|
"v8r", "HasV8_0rOps", "true", "Support ARM v8r instructions",
|
||
|
|
[//v8.1
|
||
|
|
FeatureCRC, FeaturePAN, FeatureRDM, FeatureLSE, FeatureCONTEXTIDREL2,
|
||
|
|
//v8.2
|
||
|
|
FeaturePerfMon, FeatureRAS, FeaturePsUAO, FeatureSM4,
|
||
|
|
FeatureSHA3, FeatureCCPP, FeatureFullFP16, FeaturePAN_RWV,
|
||
|
|
//v8.3
|
||
|
|
FeatureComplxNum, FeatureCCIDX, FeatureJS,
|
||
|
|
FeaturePAuth, FeatureRCPC,
|
||
|
|
//v8.4
|
||
|
|
FeatureDotProd, FeatureFP16FML, FeatureTRACEV8_4,
|
||
|
|
FeatureTLB_RMI, FeatureFlagM, FeatureDIT, FeatureSEL2, FeatureRCPC_IMMO,
|
||
|
|
//v8.5
|
||
|
|
FeatureSSBS, FeaturePredRes, FeatureSB, FeatureSpecRestrict]>;
|
||
|
|
|
||
|
|
//===----------------------------------------------------------------------===//
|
||
|
|
// Register File Description
|
||
|
|
//===----------------------------------------------------------------------===//
|
||
|
|
|
||
|
|
include "AArch64RegisterInfo.td"
|
||
|
|
include "AArch64RegisterBanks.td"
|
||
|
|
include "AArch64CallingConvention.td"
|
||
|
|
|
||
|
|
//===----------------------------------------------------------------------===//
|
||
|
|
// Instruction Descriptions
|
||
|
|
//===----------------------------------------------------------------------===//
|
||
|
|
|
||
|
|
include "AArch64Schedule.td"
|
||
|
|
include "AArch64InstrInfo.td"
|
||
|
|
include "AArch64SchedPredicates.td"
|
||
|
|
include "AArch64SchedPredExynos.td"
|
||
|
|
include "AArch64Combine.td"
|
||
|
|
|
||
|
|
def AArch64InstrInfo : InstrInfo;
|
||
|
|
|
||
|
|
//===----------------------------------------------------------------------===//
|
||
|
|
// Named operands for MRS/MSR/TLBI/...
|
||
|
|
//===----------------------------------------------------------------------===//
|
||
|
|
|
||
|
|
include "AArch64SystemOperands.td"
|
||
|
|
|
||
|
|
//===----------------------------------------------------------------------===//
|
||
|
|
// Access to privileged registers
|
||
|
|
//===----------------------------------------------------------------------===//
|
||
|
|
|
||
|
|
foreach i = 1-3 in
|
||
|
|
def FeatureUseEL#i#ForTP : SubtargetFeature<"tpidr-el"#i, "UseEL"#i#"ForTP",
|
||
|
|
"true", "Permit use of TPIDR_EL"#i#" for the TLS base">;
|
||
|
|
|
||
|
|
//===----------------------------------------------------------------------===//
|
||
|
|
// Control codegen mitigation against Straight Line Speculation vulnerability.
|
||
|
|
//===----------------------------------------------------------------------===//
|
||
|
|
|
||
|
|
def FeatureHardenSlsRetBr : SubtargetFeature<"harden-sls-retbr",
|
||
|
|
"HardenSlsRetBr", "true",
|
||
|
|
"Harden against straight line speculation across RET and BR instructions">;
|
||
|
|
def FeatureHardenSlsBlr : SubtargetFeature<"harden-sls-blr",
|
||
|
|
"HardenSlsBlr", "true",
|
||
|
|
"Harden against straight line speculation across BLR instructions">;
|
||
|
|
|
||
|
|
//===----------------------------------------------------------------------===//
|
||
|
|
// AArch64 Processors supported.
|
||
|
|
//
|
||
|
|
|
||
|
|
//===----------------------------------------------------------------------===//
|
||
|
|
// Unsupported features to disable for scheduling models
|
||
|
|
//===----------------------------------------------------------------------===//
|
||
|
|
|
||
|
|
class AArch64Unsupported { list<Predicate> F; }
|
||
|
|
|
||
|
|
def SVEUnsupported : AArch64Unsupported {
|
||
|
|
let F = [HasSVE, HasSVE2, HasSVE2AES, HasSVE2SM4, HasSVE2SHA3,
|
||
|
|
HasSVE2BitPerm];
|
||
|
|
}
|
||
|
|
|
||
|
|
def PAUnsupported : AArch64Unsupported {
|
||
|
|
let F = [HasPAuth];
|
||
|
|
}
|
||
|
|
|
||
|
|
include "AArch64SchedA53.td"
|
||
|
|
include "AArch64SchedA55.td"
|
||
|
|
include "AArch64SchedA57.td"
|
||
|
|
include "AArch64SchedCyclone.td"
|
||
|
|
include "AArch64SchedFalkor.td"
|
||
|
|
include "AArch64SchedKryo.td"
|
||
|
|
include "AArch64SchedExynosM3.td"
|
||
|
|
include "AArch64SchedExynosM4.td"
|
||
|
|
include "AArch64SchedExynosM5.td"
|
||
|
|
include "AArch64SchedThunderX.td"
|
||
|
|
include "AArch64SchedThunderX2T99.td"
|
||
|
|
include "AArch64SchedA64FX.td"
|
||
|
|
include "AArch64SchedThunderX3T110.td"
|
||
|
|
include "AArch64SchedTSV110.td"
|
||
|
|
|
||
|
|
def ProcA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35",
|
||
|
|
"Cortex-A35 ARM processors", [
|
||
|
|
FeatureCRC,
|
||
|
|
FeatureCrypto,
|
||
|
|
FeatureFPARMv8,
|
||
|
|
FeatureNEON,
|
||
|
|
FeaturePerfMon
|
||
|
|
]>;
|
||
|
|
|
||
|
|
def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
|
||
|
|
"Cortex-A53 ARM processors", [
|
||
|
|
FeatureBalanceFPOps,
|
||
|
|
FeatureCRC,
|
||
|
|
FeatureCrypto,
|
||
|
|
FeatureCustomCheapAsMoveHandling,
|
||
|
|
FeatureFPARMv8,
|
||
|
|
FeatureFuseAES,
|
||
|
|
FeatureNEON,
|
||
|
|
FeaturePerfMon,
|
||
|
|
FeaturePostRAScheduler,
|
||
|
|
FeatureUseAA
|
||
|
|
]>;
|
||
|
|
|
||
|
|
def ProcA55 : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55",
|
||
|
|
"Cortex-A55 ARM processors", [
|
||
|
|
HasV8_2aOps,
|
||
|
|
FeatureCrypto,
|
||
|
|
FeatureFPARMv8,
|
||
|
|
FeatureFuseAES,
|
||
|
|
FeatureNEON,
|
||
|
|
FeatureFullFP16,
|
||
|
|
FeatureDotProd,
|
||
|
|
FeatureRCPC,
|
||
|
|
FeaturePerfMon
|
||
|
|
]>;
|
||
|
|
|
||
|
|
def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
|
||
|
|
"Cortex-A57 ARM processors", [
|
||
|
|
FeatureBalanceFPOps,
|
||
|
|
FeatureCRC,
|
||
|
|
FeatureCrypto,
|
||
|
|
FeatureCustomCheapAsMoveHandling,
|
||
|
|
FeatureFPARMv8,
|
||
|
|
FeatureFuseAES,
|
||
|
|
FeatureFuseLiterals,
|
||
|
|
FeatureNEON,
|
||
|
|
FeaturePerfMon,
|
||
|
|
FeaturePostRAScheduler,
|
||
|
|
FeaturePredictableSelectIsExpensive
|
||
|
|
]>;
|
||
|
|
|
||
|
|
def ProcA65 : SubtargetFeature<"a65", "ARMProcFamily", "CortexA65",
|
||
|
|
"Cortex-A65 ARM processors", [
|
||
|
|
HasV8_2aOps,
|
||
|
|
FeatureCrypto,
|
||
|
|
FeatureDotProd,
|
||
|
|
FeatureFPARMv8,
|
||
|
|
FeatureFullFP16,
|
||
|
|
FeatureFuseAddress,
|
||
|
|
FeatureFuseAES,
|
||
|
|
FeatureFuseLiterals,
|
||
|
|
FeatureNEON,
|
||
|
|
FeatureRAS,
|
||
|
|
FeatureRCPC,
|
||
|
|
FeatureSSBS,
|
||
|
|
]>;
|
||
|
|
|
||
|
|
def ProcA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72",
|
||
|
|
"Cortex-A72 ARM processors", [
|
||
|
|
FeatureCRC,
|
||
|
|
FeatureCrypto,
|
||
|
|
FeatureFPARMv8,
|
||
|
|
FeatureFuseAES,
|
||
|
|
FeatureFuseLiterals,
|
||
|
|
FeatureNEON,
|
||
|
|
FeaturePerfMon
|
||
|
|
]>;
|
||
|
|
|
||
|
|
def ProcA73 : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73",
|
||
|
|
"Cortex-A73 ARM processors", [
|
||
|
|
FeatureCRC,
|
||
|
|
FeatureCrypto,
|
||
|
|
FeatureFPARMv8,
|
||
|
|
FeatureFuseAES,
|
||
|
|
FeatureNEON,
|
||
|
|
FeaturePerfMon
|
||
|
|
]>;
|
||
|
|
|
||
|
|
def ProcA75 : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75",
|
||
|
|
"Cortex-A75 ARM processors", [
|
||
|
|
HasV8_2aOps,
|
||
|
|
FeatureCrypto,
|
||
|
|
FeatureFPARMv8,
|
||
|
|
FeatureFuseAES,
|
||
|
|
FeatureNEON,
|
||
|
|
FeatureFullFP16,
|
||
|
|
FeatureDotProd,
|
||
|
|
FeatureRCPC,
|
||
|
|
FeaturePerfMon
|
||
|
|
]>;
|
||
|
|
|
||
|
|
def ProcA76 : SubtargetFeature<"a76", "ARMProcFamily", "CortexA76",
|
||
|
|
"Cortex-A76 ARM processors", [
|
||
|
|
HasV8_2aOps,
|
||
|
|
FeatureFPARMv8,
|
||
|
|
FeatureFuseAES,
|
||
|
|
FeatureNEON,
|
||
|
|
FeatureRCPC,
|
||
|
|
FeatureCrypto,
|
||
|
|
FeatureFullFP16,
|
||
|
|
FeatureDotProd,
|
||
|
|
FeatureSSBS
|
||
|
|
]>;
|
||
|
|
|
||
|
|
def ProcA77 : SubtargetFeature<"a77", "ARMProcFamily", "CortexA77",
|
||
|
|
"Cortex-A77 ARM processors", [
|
||
|
|
HasV8_2aOps,
|
||
|
|
FeatureCmpBccFusion,
|
||
|
|
FeatureFPARMv8,
|
||
|
|
FeatureFuseAES,
|
||
|
|
FeatureNEON, FeatureRCPC,
|
||
|
|
FeatureCrypto,
|
||
|
|
FeatureFullFP16,
|
||
|
|
FeatureDotProd
|
||
|
|
]>;
|
||
|
|
|
||
|
|
def ProcA78 : SubtargetFeature<"cortex-a78", "ARMProcFamily",
|
||
|
|
"CortexA78",
|
||
|
|
"Cortex-A78 ARM processors", [
|
||
|
|
HasV8_2aOps,
|
||
|
|
FeatureCmpBccFusion,
|
||
|
|
FeatureCrypto,
|
||
|
|
FeatureFPARMv8,
|
||
|
|
FeatureFuseAES,
|
||
|
|
FeatureNEON,
|
||
|
|
FeatureRCPC,
|
||
|
|
FeaturePerfMon,
|
||
|
|
FeaturePostRAScheduler,
|
||
|
|
FeatureSPE,
|
||
|
|
FeatureFullFP16,
|
||
|
|
FeatureSSBS,
|
||
|
|
FeatureDotProd]>;
|
||
|
|
|
||
|
|
def ProcA78C : SubtargetFeature<"cortex-a78c", "ARMProcFamily",
|
||
|
|
"CortexA78C",
|
||
|
|
"Cortex-A78C ARM processors", [
|
||
|
|
HasV8_2aOps,
|
||
|
|
FeatureCmpBccFusion,
|
||
|
|
FeatureCrypto,
|
||
|
|
FeatureDotProd,
|
||
|
|
FeatureFlagM,
|
||
|
|
FeatureFP16FML,
|
||
|
|
FeatureFPARMv8,
|
||
|
|
FeatureFullFP16,
|
||
|
|
FeatureFuseAES,
|
||
|
|
FeatureNEON,
|
||
|
|
FeaturePAuth,
|
||
|
|
FeaturePerfMon,
|
||
|
|
FeaturePostRAScheduler,
|
||
|
|
FeatureRCPC,
|
||
|
|
FeatureSPE,
|
||
|
|
FeatureSSBS]>;
|
||
|
|
|
||
|
|
def ProcR82 : SubtargetFeature<"cortex-r82", "ARMProcFamily",
|
||
|
|
"CortexR82",
|
||
|
|
"Cortex-R82 ARM Processors", [
|
||
|
|
FeaturePostRAScheduler,
|
||
|
|
// TODO: crypto and FuseAES
|
||
|
|
// All other features are implied by v8_0r ops:
|
||
|
|
HasV8_0rOps,
|
||
|
|
]>;
|
||
|
|
|
||
|
|
def ProcX1 : SubtargetFeature<"cortex-x1", "ARMProcFamily", "CortexX1",
|
||
|
|
"Cortex-X1 ARM processors", [
|
||
|
|
HasV8_2aOps,
|
||
|
|
FeatureCmpBccFusion,
|
||
|
|
FeatureCrypto,
|
||
|
|
FeatureFPARMv8,
|
||
|
|
FeatureFuseAES,
|
||
|
|
FeatureNEON,
|
||
|
|
FeatureRCPC,
|
||
|
|
FeaturePerfMon,
|
||
|
|
FeaturePostRAScheduler,
|
||
|
|
FeatureSPE,
|
||
|
|
FeatureFullFP16,
|
||
|
|
FeatureDotProd]>;
|
||
|
|
|
||
|
|
def ProcA64FX : SubtargetFeature<"a64fx", "ARMProcFamily", "A64FX",
|
||
|
|
"Fujitsu A64FX processors", [
|
||
|
|
HasV8_2aOps,
|
||
|
|
FeatureFPARMv8,
|
||
|
|
FeatureNEON,
|
||
|
|
FeatureSHA2,
|
||
|
|
FeaturePerfMon,
|
||
|
|
FeatureFullFP16,
|
||
|
|
FeatureSVE,
|
||
|
|
FeaturePostRAScheduler,
|
||
|
|
FeatureComplxNum,
|
||
|
|
FeatureAggressiveFMA,
|
||
|
|
FeatureArithmeticBccFusion,
|
||
|
|
FeaturePredictableSelectIsExpensive
|
||
|
|
]>;
|
||
|
|
|
||
|
|
def ProcCarmel : SubtargetFeature<"carmel", "ARMProcFamily", "Carmel",
|
||
|
|
"Nvidia Carmel processors", [
|
||
|
|
HasV8_2aOps,
|
||
|
|
FeatureNEON,
|
||
|
|
FeatureCrypto,
|
||
|
|
FeatureFullFP16
|
||
|
|
]>;
|
||
|
|
|
||
|
|
// Note that cyclone does not fuse AES instructions, but newer apple chips do
|
||
|
|
// perform the fusion and cyclone is used by default when targetting apple OSes.
|
||
|
|
def ProcAppleA7 : SubtargetFeature<"apple-a7", "ARMProcFamily", "AppleA7",
|
||
|
|
"Apple A7 (the CPU formerly known as Cyclone)", [
|
||
|
|
FeatureAlternateSExtLoadCVTF32Pattern,
|
||
|
|
FeatureArithmeticBccFusion,
|
||
|
|
FeatureArithmeticCbzFusion,
|
||
|
|
FeatureCrypto,
|
||
|
|
FeatureDisableLatencySchedHeuristic,
|
||
|
|
FeatureFPARMv8,
|
||
|
|
FeatureFuseAES,
|
||
|
|
FeatureFuseCryptoEOR,
|
||
|
|
FeatureNEON,
|
||
|
|
FeaturePerfMon,
|
||
|
|
FeatureZCRegMove,
|
||
|
|
FeatureZCZeroing,
|
||
|
|
FeatureZCZeroingFPWorkaround
|
||
|
|
]>;
|
||
|
|
|
||
|
|
def ProcAppleA10 : SubtargetFeature<"apple-a10", "ARMProcFamily", "AppleA10",
|
||
|
|
"Apple A10", [
|
||
|
|
FeatureAlternateSExtLoadCVTF32Pattern,
|
||
|
|
FeatureArithmeticBccFusion,
|
||
|
|
FeatureArithmeticCbzFusion,
|
||
|
|
FeatureCrypto,
|
||
|
|
FeatureDisableLatencySchedHeuristic,
|
||
|
|
FeatureFPARMv8,
|
||
|
|
FeatureFuseAES,
|
||
|
|
FeatureFuseCryptoEOR,
|
||
|
|
FeatureNEON,
|
||
|
|
FeaturePerfMon,
|
||
|
|
FeatureZCRegMove,
|
||
|
|
FeatureZCZeroing,
|
||
|
|
FeatureCRC,
|
||
|
|
FeatureRDM,
|
||
|
|
FeaturePAN,
|
||
|
|
FeatureLOR,
|
||
|
|
FeatureVH,
|
||
|
|
]>;
|
||
|
|
|
||
|
|
def ProcAppleA11 : SubtargetFeature<"apple-a11", "ARMProcFamily", "AppleA11",
|
||
|
|
"Apple A11", [
|
||
|
|
FeatureAlternateSExtLoadCVTF32Pattern,
|
||
|
|
FeatureArithmeticBccFusion,
|
||
|
|
FeatureArithmeticCbzFusion,
|
||
|
|
FeatureCrypto,
|
||
|
|
FeatureDisableLatencySchedHeuristic,
|
||
|
|
FeatureFPARMv8,
|
||
|
|
FeatureFuseAES,
|
||
|
|
FeatureFuseCryptoEOR,
|
||
|
|
FeatureNEON,
|
||
|
|
FeaturePerfMon,
|
||
|
|
FeatureZCRegMove,
|
||
|
|
FeatureZCZeroing,
|
||
|
|
FeatureFullFP16,
|
||
|
|
HasV8_2aOps
|
||
|
|
]>;
|
||
|
|
|
||
|
|
def ProcAppleA12 : SubtargetFeature<"apple-a12", "ARMProcFamily", "AppleA12",
|
||
|
|
"Apple A12", [
|
||
|
|
FeatureAlternateSExtLoadCVTF32Pattern,
|
||
|
|
FeatureArithmeticBccFusion,
|
||
|
|
FeatureArithmeticCbzFusion,
|
||
|
|
FeatureCrypto,
|
||
|
|
FeatureDisableLatencySchedHeuristic,
|
||
|
|
FeatureFPARMv8,
|
||
|
|
FeatureFuseAES,
|
||
|
|
FeatureFuseCryptoEOR,
|
||
|
|
FeatureNEON,
|
||
|
|
FeaturePerfMon,
|
||
|
|
FeatureZCRegMove,
|
||
|
|
FeatureZCZeroing,
|
||
|
|
FeatureFullFP16,
|
||
|
|
HasV8_3aOps
|
||
|
|
]>;
|
||
|
|
|
||
|
|
def ProcAppleA13 : SubtargetFeature<"apple-a13", "ARMProcFamily", "AppleA13",
|
||
|
|
"Apple A13", [
|
||
|
|
FeatureAlternateSExtLoadCVTF32Pattern,
|
||
|
|
FeatureArithmeticBccFusion,
|
||
|
|
FeatureArithmeticCbzFusion,
|
||
|
|
FeatureCrypto,
|
||
|
|
FeatureDisableLatencySchedHeuristic,
|
||
|
|
FeatureFPARMv8,
|
||
|
|
FeatureFuseAES,
|
||
|
|
FeatureFuseCryptoEOR,
|
||
|
|
FeatureNEON,
|
||
|
|
FeaturePerfMon,
|
||
|
|
FeatureZCRegMove,
|
||
|
|
FeatureZCZeroing,
|
||
|
|
FeatureFullFP16,
|
||
|
|
FeatureFP16FML,
|
||
|
|
FeatureSHA3,
|
||
|
|
HasV8_4aOps
|
||
|
|
]>;
|
||
|
|
|
||
|
|
def ProcAppleA14 : SubtargetFeature<"apple-a14", "ARMProcFamily", "AppleA14",
|
||
|
|
"Apple A14", [
|
||
|
|
FeatureAggressiveFMA,
|
||
|
|
FeatureAlternateSExtLoadCVTF32Pattern,
|
||
|
|
FeatureAltFPCmp,
|
||
|
|
FeatureArithmeticBccFusion,
|
||
|
|
FeatureArithmeticCbzFusion,
|
||
|
|
FeatureCrypto,
|
||
|
|
FeatureDisableLatencySchedHeuristic,
|
||
|
|
FeatureFPARMv8,
|
||
|
|
FeatureFRInt3264,
|
||
|
|
FeatureFuseAddress,
|
||
|
|
FeatureFuseAES,
|
||
|
|
FeatureFuseArithmeticLogic,
|
||
|
|
FeatureFuseCCSelect,
|
||
|
|
FeatureFuseCryptoEOR,
|
||
|
|
FeatureFuseLiterals,
|
||
|
|
FeatureNEON,
|
||
|
|
FeaturePerfMon,
|
||
|
|
FeatureSpecRestrict,
|
||
|
|
FeatureSSBS,
|
||
|
|
FeatureSB,
|
||
|
|
FeaturePredRes,
|
||
|
|
FeatureCacheDeepPersist,
|
||
|
|
FeatureZCRegMove,
|
||
|
|
FeatureZCZeroing,
|
||
|
|
FeatureFullFP16,
|
||
|
|
FeatureFP16FML,
|
||
|
|
FeatureSHA3,
|
||
|
|
HasV8_4aOps
|
||
|
|
]>;
|
||
|
|
|
||
|
|
def ProcExynosM3 : SubtargetFeature<"exynosm3", "ARMProcFamily", "ExynosM3",
|
||
|
|
"Samsung Exynos-M3 processors",
|
||
|
|
[FeatureCRC,
|
||
|
|
FeatureCrypto,
|
||
|
|
FeatureExynosCheapAsMoveHandling,
|
||
|
|
FeatureForce32BitJumpTables,
|
||
|
|
FeatureFuseAddress,
|
||
|
|
FeatureFuseAES,
|
||
|
|
FeatureFuseCCSelect,
|
||
|
|
FeatureFuseLiterals,
|
||
|
|
FeatureLSLFast,
|
||
|
|
FeaturePerfMon,
|
||
|
|
FeaturePostRAScheduler,
|
||
|
|
FeaturePredictableSelectIsExpensive,
|
||
|
|
FeatureZCZeroingFP]>;
|
||
|
|
|
||
|
|
def ProcExynosM4 : SubtargetFeature<"exynosm4", "ARMProcFamily", "ExynosM3",
|
||
|
|
"Samsung Exynos-M4 processors",
|
||
|
|
[HasV8_2aOps,
|
||
|
|
FeatureArithmeticBccFusion,
|
||
|
|
FeatureArithmeticCbzFusion,
|
||
|
|
FeatureCrypto,
|
||
|
|
FeatureDotProd,
|
||
|
|
FeatureExynosCheapAsMoveHandling,
|
||
|
|
FeatureForce32BitJumpTables,
|
||
|
|
FeatureFullFP16,
|
||
|
|
FeatureFuseAddress,
|
||
|
|
FeatureFuseAES,
|
||
|
|
FeatureFuseArithmeticLogic,
|
||
|
|
FeatureFuseCCSelect,
|
||
|
|
FeatureFuseLiterals,
|
||
|
|
FeatureLSLFast,
|
||
|
|
FeaturePerfMon,
|
||
|
|
FeaturePostRAScheduler,
|
||
|
|
FeatureZCZeroing]>;
|
||
|
|
|
||
|
|
def ProcKryo : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo",
|
||
|
|
"Qualcomm Kryo processors", [
|
||
|
|
FeatureCRC,
|
||
|
|
FeatureCrypto,
|
||
|
|
FeatureCustomCheapAsMoveHandling,
|
||
|
|
FeatureFPARMv8,
|
||
|
|
FeatureNEON,
|
||
|
|
FeaturePerfMon,
|
||
|
|
FeaturePostRAScheduler,
|
||
|
|
FeaturePredictableSelectIsExpensive,
|
||
|
|
FeatureZCZeroing,
|
||
|
|
FeatureLSLFast
|
||
|
|
]>;
|
||
|
|
|
||
|
|
def ProcFalkor : SubtargetFeature<"falkor", "ARMProcFamily", "Falkor",
|
||
|
|
"Qualcomm Falkor processors", [
|
||
|
|
FeatureCRC,
|
||
|
|
FeatureCrypto,
|
||
|
|
FeatureCustomCheapAsMoveHandling,
|
||
|
|
FeatureFPARMv8,
|
||
|
|
FeatureNEON,
|
||
|
|
FeaturePerfMon,
|
||
|
|
FeaturePostRAScheduler,
|
||
|
|
FeaturePredictableSelectIsExpensive,
|
||
|
|
FeatureRDM,
|
||
|
|
FeatureZCZeroing,
|
||
|
|
FeatureLSLFast,
|
||
|
|
FeatureSlowSTRQro
|
||
|
|
]>;
|
||
|
|
|
||
|
|
def ProcNeoverseE1 : SubtargetFeature<"neoversee1", "ARMProcFamily",
|
||
|
|
"NeoverseE1",
|
||
|
|
"Neoverse E1 ARM processors", [
|
||
|
|
HasV8_2aOps,
|
||
|
|
FeatureCrypto,
|
||
|
|
FeatureDotProd,
|
||
|
|
FeatureFPARMv8,
|
||
|
|
FeatureFullFP16,
|
||
|
|
FeatureNEON,
|
||
|
|
FeatureRCPC,
|
||
|
|
FeatureSSBS,
|
||
|
|
]>;
|
||
|
|
|
||
|
|
def ProcNeoverseN1 : SubtargetFeature<"neoversen1", "ARMProcFamily",
|
||
|
|
"NeoverseN1",
|
||
|
|
"Neoverse N1 ARM processors", [
|
||
|
|
HasV8_2aOps,
|
||
|
|
FeatureCrypto,
|
||
|
|
FeatureDotProd,
|
||
|
|
FeatureFPARMv8,
|
||
|
|
FeatureFullFP16,
|
||
|
|
FeatureNEON,
|
||
|
|
FeatureRCPC,
|
||
|
|
FeatureSPE,
|
||
|
|
FeatureSSBS,
|
||
|
|
]>;
|
||
|
|
|
||
|
|
def ProcNeoverseN2 : SubtargetFeature<"neoversen2", "ARMProcFamily",
|
||
|
|
"NeoverseN2",
|
||
|
|
"Neoverse N2 ARM processors", [
|
||
|
|
HasV8_5aOps,
|
||
|
|
FeatureBF16,
|
||
|
|
FeatureETE,
|
||
|
|
FeatureMatMulInt8,
|
||
|
|
FeatureMTE,
|
||
|
|
FeatureSVE2,
|
||
|
|
FeatureSVE2BitPerm,
|
||
|
|
FeatureTRBE]>;
|
||
|
|
|
||
|
|
def ProcNeoverseV1 : SubtargetFeature<"neoversev1", "ARMProcFamily",
|
||
|
|
"NeoverseV1",
|
||
|
|
"Neoverse V1 ARM processors", [
|
||
|
|
HasV8_4aOps,
|
||
|
|
FeatureBF16,
|
||
|
|
FeatureCacheDeepPersist,
|
||
|
|
FeatureCrypto,
|
||
|
|
FeatureFPARMv8,
|
||
|
|
FeatureFP16FML,
|
||
|
|
FeatureFullFP16,
|
||
|
|
FeatureFuseAES,
|
||
|
|
FeatureMatMulInt8,
|
||
|
|
FeatureNEON,
|
||
|
|
FeaturePerfMon,
|
||
|
|
FeaturePostRAScheduler,
|
||
|
|
FeatureRandGen,
|
||
|
|
FeatureSPE,
|
||
|
|
FeatureSSBS,
|
||
|
|
FeatureSVE]>;
|
||
|
|
|
||
|
|
def ProcSaphira : SubtargetFeature<"saphira", "ARMProcFamily", "Saphira",
|
||
|
|
"Qualcomm Saphira processors", [
|
||
|
|
FeatureCrypto,
|
||
|
|
FeatureCustomCheapAsMoveHandling,
|
||
|
|
FeatureFPARMv8,
|
||
|
|
FeatureNEON,
|
||
|
|
FeatureSPE,
|
||
|
|
FeaturePerfMon,
|
||
|
|
FeaturePostRAScheduler,
|
||
|
|
FeaturePredictableSelectIsExpensive,
|
||
|
|
FeatureZCZeroing,
|
||
|
|
FeatureLSLFast,
|
||
|
|
HasV8_4aOps]>;
|
||
|
|
|
||
|
|
def ProcThunderX2T99 : SubtargetFeature<"thunderx2t99", "ARMProcFamily",
|
||
|
|
"ThunderX2T99",
|
||
|
|
"Cavium ThunderX2 processors", [
|
||
|
|
FeatureAggressiveFMA,
|
||
|
|
FeatureCRC,
|
||
|
|
FeatureCrypto,
|
||
|
|
FeatureFPARMv8,
|
||
|
|
FeatureArithmeticBccFusion,
|
||
|
|
FeatureNEON,
|
||
|
|
FeaturePostRAScheduler,
|
||
|
|
FeaturePredictableSelectIsExpensive,
|
||
|
|
FeatureLSE,
|
||
|
|
HasV8_1aOps]>;
|
||
|
|
|
||
|
|
def ProcThunderX3T110 : SubtargetFeature<"thunderx3t110", "ARMProcFamily",
|
||
|
|
"ThunderX3T110",
|
||
|
|
"Marvell ThunderX3 processors", [
|
||
|
|
FeatureAggressiveFMA,
|
||
|
|
FeatureCRC,
|
||
|
|
FeatureCrypto,
|
||
|
|
FeatureFPARMv8,
|
||
|
|
FeatureArithmeticBccFusion,
|
||
|
|
FeatureNEON,
|
||
|
|
FeaturePostRAScheduler,
|
||
|
|
FeaturePredictableSelectIsExpensive,
|
||
|
|
FeatureLSE,
|
||
|
|
FeaturePAuth,
|
||
|
|
FeatureUseAA,
|
||
|
|
FeatureBalanceFPOps,
|
||
|
|
FeaturePerfMon,
|
||
|
|
FeatureStrictAlign,
|
||
|
|
HasV8_3aOps]>;
|
||
|
|
|
||
|
|
def ProcThunderX : SubtargetFeature<"thunderx", "ARMProcFamily", "ThunderX",
|
||
|
|
"Cavium ThunderX processors", [
|
||
|
|
FeatureCRC,
|
||
|
|
FeatureCrypto,
|
||
|
|
FeatureFPARMv8,
|
||
|
|
FeaturePerfMon,
|
||
|
|
FeaturePostRAScheduler,
|
||
|
|
FeaturePredictableSelectIsExpensive,
|
||
|
|
FeatureNEON]>;
|
||
|
|
|
||
|
|
def ProcThunderXT88 : SubtargetFeature<"thunderxt88", "ARMProcFamily",
|
||
|
|
"ThunderXT88",
|
||
|
|
"Cavium ThunderX processors", [
|
||
|
|
FeatureCRC,
|
||
|
|
FeatureCrypto,
|
||
|
|
FeatureFPARMv8,
|
||
|
|
FeaturePerfMon,
|
||
|
|
FeaturePostRAScheduler,
|
||
|
|
FeaturePredictableSelectIsExpensive,
|
||
|
|
FeatureNEON]>;
|
||
|
|
|
||
|
|
def ProcThunderXT81 : SubtargetFeature<"thunderxt81", "ARMProcFamily",
|
||
|
|
"ThunderXT81",
|
||
|
|
"Cavium ThunderX processors", [
|
||
|
|
FeatureCRC,
|
||
|
|
FeatureCrypto,
|
||
|
|
FeatureFPARMv8,
|
||
|
|
FeaturePerfMon,
|
||
|
|
FeaturePostRAScheduler,
|
||
|
|
FeaturePredictableSelectIsExpensive,
|
||
|
|
FeatureNEON]>;
|
||
|
|
|
||
|
|
def ProcThunderXT83 : SubtargetFeature<"thunderxt83", "ARMProcFamily",
|
||
|
|
"ThunderXT83",
|
||
|
|
"Cavium ThunderX processors", [
|
||
|
|
FeatureCRC,
|
||
|
|
FeatureCrypto,
|
||
|
|
FeatureFPARMv8,
|
||
|
|
FeaturePerfMon,
|
||
|
|
FeaturePostRAScheduler,
|
||
|
|
FeaturePredictableSelectIsExpensive,
|
||
|
|
FeatureNEON]>;
|
||
|
|
|
||
|
|
def ProcTSV110 : SubtargetFeature<"tsv110", "ARMProcFamily", "TSV110",
|
||
|
|
"HiSilicon TS-V110 processors", [
|
||
|
|
HasV8_2aOps,
|
||
|
|
FeatureCrypto,
|
||
|
|
FeatureCustomCheapAsMoveHandling,
|
||
|
|
FeatureFPARMv8,
|
||
|
|
FeatureFuseAES,
|
||
|
|
FeatureNEON,
|
||
|
|
FeaturePerfMon,
|
||
|
|
FeaturePostRAScheduler,
|
||
|
|
FeatureSPE,
|
||
|
|
FeatureFullFP16,
|
||
|
|
FeatureFP16FML,
|
||
|
|
FeatureDotProd]>;
|
||
|
|
|
||
|
|
def : ProcessorModel<"generic", NoSchedModel, [
|
||
|
|
FeatureFPARMv8,
|
||
|
|
FeatureFuseAES,
|
||
|
|
FeatureNEON,
|
||
|
|
FeaturePerfMon,
|
||
|
|
FeaturePostRAScheduler,
|
||
|
|
// ETE and TRBE are future architecture extensions. We temporarily enable them
|
||
|
|
// by default for users targeting generic AArch64, until it is decided in which
|
||
|
|
// armv8.x-a architecture revision they will end up. The extensions do not
|
||
|
|
// affect code generated by the compiler and can be used only by explicitly
|
||
|
|
// mentioning the new system register names in assembly.
|
||
|
|
FeatureETE
|
||
|
|
]>;
|
||
|
|
|
||
|
|
def : ProcessorModel<"cortex-a35", CortexA53Model, [ProcA35]>;
|
||
|
|
def : ProcessorModel<"cortex-a34", CortexA53Model, [ProcA35]>;
|
||
|
|
def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>;
|
||
|
|
def : ProcessorModel<"cortex-a55", CortexA55Model, [ProcA55]>;
|
||
|
|
def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>;
|
||
|
|
def : ProcessorModel<"cortex-a65", CortexA53Model, [ProcA65]>;
|
||
|
|
def : ProcessorModel<"cortex-a65ae", CortexA53Model, [ProcA65]>;
|
||
|
|
def : ProcessorModel<"cortex-a72", CortexA57Model, [ProcA72]>;
|
||
|
|
def : ProcessorModel<"cortex-a73", CortexA57Model, [ProcA73]>;
|
||
|
|
def : ProcessorModel<"cortex-a75", CortexA57Model, [ProcA75]>;
|
||
|
|
def : ProcessorModel<"cortex-a76", CortexA57Model, [ProcA76]>;
|
||
|
|
def : ProcessorModel<"cortex-a76ae", CortexA57Model, [ProcA76]>;
|
||
|
|
def : ProcessorModel<"cortex-a77", CortexA57Model, [ProcA77]>;
|
||
|
|
def : ProcessorModel<"cortex-a78", CortexA57Model, [ProcA78]>;
|
||
|
|
def : ProcessorModel<"cortex-a78c", CortexA57Model, [ProcA78C]>;
|
||
|
|
def : ProcessorModel<"cortex-r82", CortexA55Model, [ProcR82]>;
|
||
|
|
def : ProcessorModel<"cortex-x1", CortexA57Model, [ProcX1]>;
|
||
|
|
def : ProcessorModel<"neoverse-e1", CortexA53Model, [ProcNeoverseE1]>;
|
||
|
|
def : ProcessorModel<"neoverse-n1", CortexA57Model, [ProcNeoverseN1]>;
|
||
|
|
def : ProcessorModel<"neoverse-n2", CortexA57Model, [ProcNeoverseN2]>;
|
||
|
|
def : ProcessorModel<"neoverse-v1", CortexA57Model, [ProcNeoverseV1]>;
|
||
|
|
def : ProcessorModel<"exynos-m3", ExynosM3Model, [ProcExynosM3]>;
|
||
|
|
def : ProcessorModel<"exynos-m4", ExynosM4Model, [ProcExynosM4]>;
|
||
|
|
def : ProcessorModel<"exynos-m5", ExynosM5Model, [ProcExynosM4]>;
|
||
|
|
def : ProcessorModel<"falkor", FalkorModel, [ProcFalkor]>;
|
||
|
|
def : ProcessorModel<"saphira", FalkorModel, [ProcSaphira]>;
|
||
|
|
def : ProcessorModel<"kryo", KryoModel, [ProcKryo]>;
|
||
|
|
// Cavium ThunderX/ThunderX T8X Processors
|
||
|
|
def : ProcessorModel<"thunderx", ThunderXT8XModel, [ProcThunderX]>;
|
||
|
|
def : ProcessorModel<"thunderxt88", ThunderXT8XModel, [ProcThunderXT88]>;
|
||
|
|
def : ProcessorModel<"thunderxt81", ThunderXT8XModel, [ProcThunderXT81]>;
|
||
|
|
def : ProcessorModel<"thunderxt83", ThunderXT8XModel, [ProcThunderXT83]>;
|
||
|
|
// Cavium ThunderX2T9X Processors. Formerly Broadcom Vulcan.
|
||
|
|
def : ProcessorModel<"thunderx2t99", ThunderX2T99Model, [ProcThunderX2T99]>;
|
||
|
|
// Marvell ThunderX3T110 Processors.
|
||
|
|
def : ProcessorModel<"thunderx3t110", ThunderX3T110Model, [ProcThunderX3T110]>;
|
||
|
|
def : ProcessorModel<"tsv110", TSV110Model, [ProcTSV110]>;
|
||
|
|
|
||
|
|
// Support cyclone as an alias for apple-a7 so we can still LTO old bitcode.
|
||
|
|
def : ProcessorModel<"cyclone", CycloneModel, [ProcAppleA7]>;
|
||
|
|
|
||
|
|
// iPhone and iPad CPUs
|
||
|
|
def : ProcessorModel<"apple-a7", CycloneModel, [ProcAppleA7]>;
|
||
|
|
def : ProcessorModel<"apple-a8", CycloneModel, [ProcAppleA7]>;
|
||
|
|
def : ProcessorModel<"apple-a9", CycloneModel, [ProcAppleA7]>;
|
||
|
|
def : ProcessorModel<"apple-a10", CycloneModel, [ProcAppleA10]>;
|
||
|
|
def : ProcessorModel<"apple-a11", CycloneModel, [ProcAppleA11]>;
|
||
|
|
def : ProcessorModel<"apple-a12", CycloneModel, [ProcAppleA12]>;
|
||
|
|
def : ProcessorModel<"apple-a13", CycloneModel, [ProcAppleA13]>;
|
||
|
|
def : ProcessorModel<"apple-a14", CycloneModel, [ProcAppleA14]>;
|
||
|
|
|
||
|
|
// watch CPUs.
|
||
|
|
def : ProcessorModel<"apple-s4", CycloneModel, [ProcAppleA12]>;
|
||
|
|
def : ProcessorModel<"apple-s5", CycloneModel, [ProcAppleA12]>;
|
||
|
|
|
||
|
|
// Alias for the latest Apple processor model supported by LLVM.
|
||
|
|
def : ProcessorModel<"apple-latest", CycloneModel, [ProcAppleA13]>;
|
||
|
|
|
||
|
|
// Fujitsu A64FX
|
||
|
|
def : ProcessorModel<"a64fx", A64FXModel, [ProcA64FX]>;
|
||
|
|
|
||
|
|
// Nvidia Carmel
|
||
|
|
def : ProcessorModel<"carmel", NoSchedModel, [ProcCarmel]>;
|
||
|
|
|
||
|
|
//===----------------------------------------------------------------------===//
|
||
|
|
// Assembly parser
|
||
|
|
//===----------------------------------------------------------------------===//
|
||
|
|
|
||
|
|
def GenericAsmParserVariant : AsmParserVariant {
|
||
|
|
int Variant = 0;
|
||
|
|
string Name = "generic";
|
||
|
|
string BreakCharacters = ".";
|
||
|
|
string TokenizingCharacters = "[]*!/";
|
||
|
|
}
|
||
|
|
|
||
|
|
def AppleAsmParserVariant : AsmParserVariant {
|
||
|
|
int Variant = 1;
|
||
|
|
string Name = "apple-neon";
|
||
|
|
string BreakCharacters = ".";
|
||
|
|
string TokenizingCharacters = "[]*!/";
|
||
|
|
}
|
||
|
|
|
||
|
|
//===----------------------------------------------------------------------===//
|
||
|
|
// Assembly printer
|
||
|
|
//===----------------------------------------------------------------------===//
|
||
|
|
// AArch64 Uses the MC printer for asm output, so make sure the TableGen
|
||
|
|
// AsmWriter bits get associated with the correct class.
|
||
|
|
def GenericAsmWriter : AsmWriter {
|
||
|
|
string AsmWriterClassName = "InstPrinter";
|
||
|
|
int PassSubtarget = 1;
|
||
|
|
int Variant = 0;
|
||
|
|
bit isMCAsmWriter = 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
def AppleAsmWriter : AsmWriter {
|
||
|
|
let AsmWriterClassName = "AppleInstPrinter";
|
||
|
|
int PassSubtarget = 1;
|
||
|
|
int Variant = 1;
|
||
|
|
int isMCAsmWriter = 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
//===----------------------------------------------------------------------===//
|
||
|
|
// Target Declaration
|
||
|
|
//===----------------------------------------------------------------------===//
|
||
|
|
|
||
|
|
def AArch64 : Target {
|
||
|
|
let InstructionSet = AArch64InstrInfo;
|
||
|
|
let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant];
|
||
|
|
let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter];
|
||
|
|
let AllowRegisterRenaming = 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
//===----------------------------------------------------------------------===//
|
||
|
|
// Pfm Counters
|
||
|
|
//===----------------------------------------------------------------------===//
|
||
|
|
|
||
|
|
include "AArch64PfmCounters.td"
|