505 lines
18 KiB
C++
505 lines
18 KiB
C++
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//===-- DWARFExpression.cpp -----------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/DebugInfo/DWARF/DWARFExpression.h"
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#include "llvm/DebugInfo/DWARF/DWARFUnit.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/Support/Format.h"
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#include <cassert>
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#include <cstdint>
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#include <vector>
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using namespace llvm;
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using namespace dwarf;
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namespace llvm {
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typedef std::vector<DWARFExpression::Operation::Description> DescVector;
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static DescVector getDescriptions() {
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DescVector Descriptions;
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typedef DWARFExpression::Operation Op;
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typedef Op::Description Desc;
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Descriptions.resize(0xff);
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Descriptions[DW_OP_addr] = Desc(Op::Dwarf2, Op::SizeAddr);
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Descriptions[DW_OP_deref] = Desc(Op::Dwarf2);
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Descriptions[DW_OP_const1u] = Desc(Op::Dwarf2, Op::Size1);
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Descriptions[DW_OP_const1s] = Desc(Op::Dwarf2, Op::SignedSize1);
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Descriptions[DW_OP_const2u] = Desc(Op::Dwarf2, Op::Size2);
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Descriptions[DW_OP_const2s] = Desc(Op::Dwarf2, Op::SignedSize2);
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Descriptions[DW_OP_const4u] = Desc(Op::Dwarf2, Op::Size4);
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Descriptions[DW_OP_const4s] = Desc(Op::Dwarf2, Op::SignedSize4);
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Descriptions[DW_OP_const8u] = Desc(Op::Dwarf2, Op::Size8);
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Descriptions[DW_OP_const8s] = Desc(Op::Dwarf2, Op::SignedSize8);
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Descriptions[DW_OP_constu] = Desc(Op::Dwarf2, Op::SizeLEB);
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Descriptions[DW_OP_consts] = Desc(Op::Dwarf2, Op::SignedSizeLEB);
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Descriptions[DW_OP_dup] = Desc(Op::Dwarf2);
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Descriptions[DW_OP_drop] = Desc(Op::Dwarf2);
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Descriptions[DW_OP_over] = Desc(Op::Dwarf2);
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Descriptions[DW_OP_pick] = Desc(Op::Dwarf2, Op::Size1);
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Descriptions[DW_OP_swap] = Desc(Op::Dwarf2);
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Descriptions[DW_OP_rot] = Desc(Op::Dwarf2);
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Descriptions[DW_OP_xderef] = Desc(Op::Dwarf2);
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Descriptions[DW_OP_abs] = Desc(Op::Dwarf2);
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Descriptions[DW_OP_and] = Desc(Op::Dwarf2);
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Descriptions[DW_OP_div] = Desc(Op::Dwarf2);
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Descriptions[DW_OP_minus] = Desc(Op::Dwarf2);
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Descriptions[DW_OP_mod] = Desc(Op::Dwarf2);
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Descriptions[DW_OP_mul] = Desc(Op::Dwarf2);
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Descriptions[DW_OP_neg] = Desc(Op::Dwarf2);
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Descriptions[DW_OP_not] = Desc(Op::Dwarf2);
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Descriptions[DW_OP_or] = Desc(Op::Dwarf2);
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Descriptions[DW_OP_plus] = Desc(Op::Dwarf2);
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Descriptions[DW_OP_plus_uconst] = Desc(Op::Dwarf2, Op::SizeLEB);
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Descriptions[DW_OP_shl] = Desc(Op::Dwarf2);
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Descriptions[DW_OP_shr] = Desc(Op::Dwarf2);
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Descriptions[DW_OP_shra] = Desc(Op::Dwarf2);
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Descriptions[DW_OP_xor] = Desc(Op::Dwarf2);
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Descriptions[DW_OP_skip] = Desc(Op::Dwarf2, Op::SignedSize2);
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Descriptions[DW_OP_bra] = Desc(Op::Dwarf2, Op::SignedSize2);
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Descriptions[DW_OP_eq] = Desc(Op::Dwarf2);
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Descriptions[DW_OP_ge] = Desc(Op::Dwarf2);
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Descriptions[DW_OP_gt] = Desc(Op::Dwarf2);
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Descriptions[DW_OP_le] = Desc(Op::Dwarf2);
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Descriptions[DW_OP_lt] = Desc(Op::Dwarf2);
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Descriptions[DW_OP_ne] = Desc(Op::Dwarf2);
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for (uint16_t LA = DW_OP_lit0; LA <= DW_OP_lit31; ++LA)
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Descriptions[LA] = Desc(Op::Dwarf2);
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for (uint16_t LA = DW_OP_reg0; LA <= DW_OP_reg31; ++LA)
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Descriptions[LA] = Desc(Op::Dwarf2);
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for (uint16_t LA = DW_OP_breg0; LA <= DW_OP_breg31; ++LA)
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Descriptions[LA] = Desc(Op::Dwarf2, Op::SignedSizeLEB);
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Descriptions[DW_OP_regx] = Desc(Op::Dwarf2, Op::SizeLEB);
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Descriptions[DW_OP_fbreg] = Desc(Op::Dwarf2, Op::SignedSizeLEB);
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Descriptions[DW_OP_bregx] = Desc(Op::Dwarf2, Op::SizeLEB, Op::SignedSizeLEB);
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Descriptions[DW_OP_piece] = Desc(Op::Dwarf2, Op::SizeLEB);
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Descriptions[DW_OP_deref_size] = Desc(Op::Dwarf2, Op::Size1);
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Descriptions[DW_OP_xderef_size] = Desc(Op::Dwarf2, Op::Size1);
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Descriptions[DW_OP_nop] = Desc(Op::Dwarf2);
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Descriptions[DW_OP_push_object_address] = Desc(Op::Dwarf3);
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Descriptions[DW_OP_call2] = Desc(Op::Dwarf3, Op::Size2);
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Descriptions[DW_OP_call4] = Desc(Op::Dwarf3, Op::Size4);
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Descriptions[DW_OP_call_ref] = Desc(Op::Dwarf3, Op::SizeRefAddr);
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Descriptions[DW_OP_form_tls_address] = Desc(Op::Dwarf3);
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Descriptions[DW_OP_call_frame_cfa] = Desc(Op::Dwarf3);
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Descriptions[DW_OP_bit_piece] = Desc(Op::Dwarf3, Op::SizeLEB, Op::SizeLEB);
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Descriptions[DW_OP_implicit_value] =
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Desc(Op::Dwarf3, Op::SizeLEB, Op::SizeBlock);
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Descriptions[DW_OP_stack_value] = Desc(Op::Dwarf3);
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Descriptions[DW_OP_WASM_location] =
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Desc(Op::Dwarf4, Op::SizeLEB, Op::WasmLocationArg);
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Descriptions[DW_OP_GNU_push_tls_address] = Desc(Op::Dwarf3);
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Descriptions[DW_OP_addrx] = Desc(Op::Dwarf4, Op::SizeLEB);
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Descriptions[DW_OP_GNU_addr_index] = Desc(Op::Dwarf4, Op::SizeLEB);
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Descriptions[DW_OP_GNU_const_index] = Desc(Op::Dwarf4, Op::SizeLEB);
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Descriptions[DW_OP_GNU_entry_value] = Desc(Op::Dwarf4, Op::SizeLEB);
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Descriptions[DW_OP_convert] = Desc(Op::Dwarf5, Op::BaseTypeRef);
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Descriptions[DW_OP_entry_value] = Desc(Op::Dwarf5, Op::SizeLEB);
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Descriptions[DW_OP_regval_type] =
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Desc(Op::Dwarf5, Op::SizeLEB, Op::BaseTypeRef);
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return Descriptions;
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}
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static DWARFExpression::Operation::Description getOpDesc(unsigned OpCode) {
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// FIXME: Make this constexpr once all compilers are smart enough to do it.
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static DescVector Descriptions = getDescriptions();
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// Handle possible corrupted or unsupported operation.
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if (OpCode >= Descriptions.size())
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return {};
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return Descriptions[OpCode];
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}
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bool DWARFExpression::Operation::extract(DataExtractor Data,
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uint8_t AddressSize, uint64_t Offset,
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Optional<DwarfFormat> Format) {
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EndOffset = Offset;
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Opcode = Data.getU8(&Offset);
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Desc = getOpDesc(Opcode);
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if (Desc.Version == Operation::DwarfNA)
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return false;
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for (unsigned Operand = 0; Operand < 2; ++Operand) {
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unsigned Size = Desc.Op[Operand];
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unsigned Signed = Size & Operation::SignBit;
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if (Size == Operation::SizeNA)
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break;
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switch (Size & ~Operation::SignBit) {
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case Operation::Size1:
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Operands[Operand] = Data.getU8(&Offset);
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if (Signed)
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Operands[Operand] = (int8_t)Operands[Operand];
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break;
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case Operation::Size2:
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Operands[Operand] = Data.getU16(&Offset);
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if (Signed)
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Operands[Operand] = (int16_t)Operands[Operand];
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break;
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case Operation::Size4:
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Operands[Operand] = Data.getU32(&Offset);
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if (Signed)
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Operands[Operand] = (int32_t)Operands[Operand];
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break;
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case Operation::Size8:
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Operands[Operand] = Data.getU64(&Offset);
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break;
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case Operation::SizeAddr:
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Operands[Operand] = Data.getUnsigned(&Offset, AddressSize);
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break;
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case Operation::SizeRefAddr:
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if (!Format)
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return false;
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Operands[Operand] =
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Data.getUnsigned(&Offset, dwarf::getDwarfOffsetByteSize(*Format));
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break;
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case Operation::SizeLEB:
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if (Signed)
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Operands[Operand] = Data.getSLEB128(&Offset);
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else
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Operands[Operand] = Data.getULEB128(&Offset);
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break;
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case Operation::BaseTypeRef:
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Operands[Operand] = Data.getULEB128(&Offset);
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break;
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case Operation::WasmLocationArg:
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assert(Operand == 1);
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switch (Operands[0]) {
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case 0: case 1: case 2:
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Operands[Operand] = Data.getULEB128(&Offset);
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break;
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case 3: // global as uint32
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Operands[Operand] = Data.getU32(&Offset);
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break;
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default:
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return false; // Unknown Wasm location
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}
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break;
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case Operation::SizeBlock:
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// We need a size, so this cannot be the first operand
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if (Operand == 0)
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return false;
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// Store the offset of the block as the value.
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Operands[Operand] = Offset;
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Offset += Operands[Operand - 1];
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break;
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default:
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llvm_unreachable("Unknown DWARFExpression Op size");
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}
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OperandEndOffsets[Operand] = Offset;
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}
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EndOffset = Offset;
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return true;
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}
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static void prettyPrintBaseTypeRef(DWARFUnit *U, raw_ostream &OS,
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DIDumpOptions DumpOpts, uint64_t Operands[2],
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unsigned Operand) {
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assert(Operand < 2 && "operand out of bounds");
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auto Die = U->getDIEForOffset(U->getOffset() + Operands[Operand]);
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if (Die && Die.getTag() == dwarf::DW_TAG_base_type) {
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OS << " (";
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if (DumpOpts.Verbose)
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OS << format("0x%08" PRIx64 " -> ", Operands[Operand]);
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OS << format("0x%08" PRIx64 ")", U->getOffset() + Operands[Operand]);
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if (auto Name = Die.find(dwarf::DW_AT_name))
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OS << " \"" << Name->getAsCString() << "\"";
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} else {
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OS << format(" <invalid base_type ref: 0x%" PRIx64 ">",
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Operands[Operand]);
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}
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}
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static bool prettyPrintRegisterOp(DWARFUnit *U, raw_ostream &OS,
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DIDumpOptions DumpOpts, uint8_t Opcode,
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uint64_t Operands[2],
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const MCRegisterInfo *MRI, bool isEH) {
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if (!MRI)
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return false;
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uint64_t DwarfRegNum;
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unsigned OpNum = 0;
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if (Opcode == DW_OP_bregx || Opcode == DW_OP_regx ||
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Opcode == DW_OP_regval_type)
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DwarfRegNum = Operands[OpNum++];
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else if (Opcode >= DW_OP_breg0 && Opcode < DW_OP_bregx)
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DwarfRegNum = Opcode - DW_OP_breg0;
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else
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DwarfRegNum = Opcode - DW_OP_reg0;
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if (Optional<unsigned> LLVMRegNum = MRI->getLLVMRegNum(DwarfRegNum, isEH)) {
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if (const char *RegName = MRI->getName(*LLVMRegNum)) {
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if ((Opcode >= DW_OP_breg0 && Opcode <= DW_OP_breg31) ||
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Opcode == DW_OP_bregx)
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OS << format(" %s%+" PRId64, RegName, Operands[OpNum]);
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else
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OS << ' ' << RegName;
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if (Opcode == DW_OP_regval_type)
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prettyPrintBaseTypeRef(U, OS, DumpOpts, Operands, 1);
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return true;
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}
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}
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return false;
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}
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bool DWARFExpression::Operation::print(raw_ostream &OS, DIDumpOptions DumpOpts,
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const DWARFExpression *Expr,
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const MCRegisterInfo *RegInfo,
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DWARFUnit *U, bool isEH) {
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if (Error) {
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OS << "<decoding error>";
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return false;
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}
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StringRef Name = OperationEncodingString(Opcode);
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assert(!Name.empty() && "DW_OP has no name!");
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OS << Name;
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if ((Opcode >= DW_OP_breg0 && Opcode <= DW_OP_breg31) ||
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(Opcode >= DW_OP_reg0 && Opcode <= DW_OP_reg31) ||
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Opcode == DW_OP_bregx || Opcode == DW_OP_regx ||
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Opcode == DW_OP_regval_type)
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if (prettyPrintRegisterOp(U, OS, DumpOpts, Opcode, Operands, RegInfo, isEH))
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return true;
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for (unsigned Operand = 0; Operand < 2; ++Operand) {
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unsigned Size = Desc.Op[Operand];
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unsigned Signed = Size & Operation::SignBit;
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if (Size == Operation::SizeNA)
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break;
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if (Size == Operation::BaseTypeRef && U) {
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// For DW_OP_convert the operand may be 0 to indicate that conversion to
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// the generic type should be done. The same holds for DW_OP_reinterpret,
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// which is currently not supported.
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if (Opcode == DW_OP_convert && Operands[Operand] == 0)
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OS << " 0x0";
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else
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prettyPrintBaseTypeRef(U, OS, DumpOpts, Operands, Operand);
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} else if (Size == Operation::WasmLocationArg) {
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assert(Operand == 1);
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switch (Operands[0]) {
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case 0: case 1: case 2:
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case 3: // global as uint32
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OS << format(" 0x%" PRIx64, Operands[Operand]);
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break;
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default: assert(false);
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}
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} else if (Size == Operation::SizeBlock) {
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uint64_t Offset = Operands[Operand];
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for (unsigned i = 0; i < Operands[Operand - 1]; ++i)
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OS << format(" 0x%02x", Expr->Data.getU8(&Offset));
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} else {
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if (Signed)
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OS << format(" %+" PRId64, (int64_t)Operands[Operand]);
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else if (Opcode != DW_OP_entry_value &&
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Opcode != DW_OP_GNU_entry_value)
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OS << format(" 0x%" PRIx64, Operands[Operand]);
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}
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}
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|
|
return true;
|
||
|
|
}
|
||
|
|
|
||
|
|
void DWARFExpression::print(raw_ostream &OS, DIDumpOptions DumpOpts,
|
||
|
|
const MCRegisterInfo *RegInfo, DWARFUnit *U,
|
||
|
|
bool IsEH) const {
|
||
|
|
uint32_t EntryValExprSize = 0;
|
||
|
|
for (auto &Op : *this) {
|
||
|
|
if (!Op.print(OS, DumpOpts, this, RegInfo, U, IsEH)) {
|
||
|
|
uint64_t FailOffset = Op.getEndOffset();
|
||
|
|
while (FailOffset < Data.getData().size())
|
||
|
|
OS << format(" %02x", Data.getU8(&FailOffset));
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (Op.getCode() == DW_OP_entry_value ||
|
||
|
|
Op.getCode() == DW_OP_GNU_entry_value) {
|
||
|
|
OS << "(";
|
||
|
|
EntryValExprSize = Op.getRawOperand(0);
|
||
|
|
continue;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (EntryValExprSize) {
|
||
|
|
EntryValExprSize--;
|
||
|
|
if (EntryValExprSize == 0)
|
||
|
|
OS << ")";
|
||
|
|
}
|
||
|
|
|
||
|
|
if (Op.getEndOffset() < Data.getData().size())
|
||
|
|
OS << ", ";
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
bool DWARFExpression::Operation::verify(DWARFUnit *U) {
|
||
|
|
|
||
|
|
for (unsigned Operand = 0; Operand < 2; ++Operand) {
|
||
|
|
unsigned Size = Desc.Op[Operand];
|
||
|
|
|
||
|
|
if (Size == Operation::SizeNA)
|
||
|
|
break;
|
||
|
|
|
||
|
|
if (Size == Operation::BaseTypeRef) {
|
||
|
|
// For DW_OP_convert the operand may be 0 to indicate that conversion to
|
||
|
|
// the generic type should be done, so don't look up a base type in that
|
||
|
|
// case. The same holds for DW_OP_reinterpret, which is currently not
|
||
|
|
// supported.
|
||
|
|
if (Opcode == DW_OP_convert && Operands[Operand] == 0)
|
||
|
|
continue;
|
||
|
|
auto Die = U->getDIEForOffset(U->getOffset() + Operands[Operand]);
|
||
|
|
if (!Die || Die.getTag() != dwarf::DW_TAG_base_type) {
|
||
|
|
Error = true;
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
|
||
|
|
bool DWARFExpression::verify(DWARFUnit *U) {
|
||
|
|
for (auto &Op : *this)
|
||
|
|
if (!Op.verify(U))
|
||
|
|
return false;
|
||
|
|
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
|
||
|
|
/// A user-facing string representation of a DWARF expression. This might be an
|
||
|
|
/// Address expression, in which case it will be implicitly dereferenced, or a
|
||
|
|
/// Value expression.
|
||
|
|
struct PrintedExpr {
|
||
|
|
enum ExprKind {
|
||
|
|
Address,
|
||
|
|
Value,
|
||
|
|
};
|
||
|
|
ExprKind Kind;
|
||
|
|
SmallString<16> String;
|
||
|
|
|
||
|
|
PrintedExpr(ExprKind K = Address) : Kind(K) {}
|
||
|
|
};
|
||
|
|
|
||
|
|
static bool printCompactDWARFExpr(raw_ostream &OS, DWARFExpression::iterator I,
|
||
|
|
const DWARFExpression::iterator E,
|
||
|
|
const MCRegisterInfo &MRI) {
|
||
|
|
SmallVector<PrintedExpr, 4> Stack;
|
||
|
|
|
||
|
|
while (I != E) {
|
||
|
|
DWARFExpression::Operation &Op = *I;
|
||
|
|
uint8_t Opcode = Op.getCode();
|
||
|
|
switch (Opcode) {
|
||
|
|
case dwarf::DW_OP_regx: {
|
||
|
|
// DW_OP_regx: A register, with the register num given as an operand.
|
||
|
|
// Printed as the plain register name.
|
||
|
|
uint64_t DwarfRegNum = Op.getRawOperand(0);
|
||
|
|
Optional<unsigned> LLVMRegNum = MRI.getLLVMRegNum(DwarfRegNum, false);
|
||
|
|
if (!LLVMRegNum) {
|
||
|
|
OS << "<unknown register " << DwarfRegNum << ">";
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
raw_svector_ostream S(Stack.emplace_back(PrintedExpr::Value).String);
|
||
|
|
S << MRI.getName(*LLVMRegNum);
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
case dwarf::DW_OP_bregx: {
|
||
|
|
int DwarfRegNum = Op.getRawOperand(0);
|
||
|
|
int64_t Offset = Op.getRawOperand(1);
|
||
|
|
Optional<unsigned> LLVMRegNum = MRI.getLLVMRegNum(DwarfRegNum, false);
|
||
|
|
if (!LLVMRegNum) {
|
||
|
|
OS << "<unknown register " << DwarfRegNum << ">";
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
raw_svector_ostream S(Stack.emplace_back().String);
|
||
|
|
S << MRI.getName(*LLVMRegNum);
|
||
|
|
if (Offset)
|
||
|
|
S << format("%+" PRId64, Offset);
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
case dwarf::DW_OP_entry_value:
|
||
|
|
case dwarf::DW_OP_GNU_entry_value: {
|
||
|
|
// DW_OP_entry_value contains a sub-expression which must be rendered
|
||
|
|
// separately.
|
||
|
|
uint64_t SubExprLength = Op.getRawOperand(0);
|
||
|
|
DWARFExpression::iterator SubExprEnd = I.skipBytes(SubExprLength);
|
||
|
|
++I;
|
||
|
|
raw_svector_ostream S(Stack.emplace_back().String);
|
||
|
|
S << "entry(";
|
||
|
|
printCompactDWARFExpr(S, I, SubExprEnd, MRI);
|
||
|
|
S << ")";
|
||
|
|
I = SubExprEnd;
|
||
|
|
continue;
|
||
|
|
}
|
||
|
|
case dwarf::DW_OP_stack_value: {
|
||
|
|
// The top stack entry should be treated as the actual value of tne
|
||
|
|
// variable, rather than the address of the variable in memory.
|
||
|
|
assert(!Stack.empty());
|
||
|
|
Stack.back().Kind = PrintedExpr::Value;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
default:
|
||
|
|
if (Opcode >= dwarf::DW_OP_reg0 && Opcode <= dwarf::DW_OP_reg31) {
|
||
|
|
// DW_OP_reg<N>: A register, with the register num implied by the
|
||
|
|
// opcode. Printed as the plain register name.
|
||
|
|
uint64_t DwarfRegNum = Opcode - dwarf::DW_OP_reg0;
|
||
|
|
Optional<unsigned> LLVMRegNum = MRI.getLLVMRegNum(DwarfRegNum, false);
|
||
|
|
if (!LLVMRegNum) {
|
||
|
|
OS << "<unknown register " << DwarfRegNum << ">";
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
raw_svector_ostream S(Stack.emplace_back(PrintedExpr::Value).String);
|
||
|
|
S << MRI.getName(*LLVMRegNum);
|
||
|
|
} else if (Opcode >= dwarf::DW_OP_breg0 &&
|
||
|
|
Opcode <= dwarf::DW_OP_breg31) {
|
||
|
|
int DwarfRegNum = Opcode - dwarf::DW_OP_breg0;
|
||
|
|
int64_t Offset = Op.getRawOperand(0);
|
||
|
|
Optional<unsigned> LLVMRegNum = MRI.getLLVMRegNum(DwarfRegNum, false);
|
||
|
|
if (!LLVMRegNum) {
|
||
|
|
OS << "<unknown register " << DwarfRegNum << ">";
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
raw_svector_ostream S(Stack.emplace_back().String);
|
||
|
|
S << MRI.getName(*LLVMRegNum);
|
||
|
|
if (Offset)
|
||
|
|
S << format("%+" PRId64, Offset);
|
||
|
|
} else {
|
||
|
|
// If we hit an unknown operand, we don't know its effect on the stack,
|
||
|
|
// so bail out on the whole expression.
|
||
|
|
OS << "<unknown op " << dwarf::OperationEncodingString(Opcode) << " ("
|
||
|
|
<< (int)Opcode << ")>";
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
++I;
|
||
|
|
}
|
||
|
|
|
||
|
|
assert(Stack.size() == 1 && "expected one value on stack");
|
||
|
|
|
||
|
|
if (Stack.front().Kind == PrintedExpr::Address)
|
||
|
|
OS << "[" << Stack.front().String << "]";
|
||
|
|
else
|
||
|
|
OS << Stack.front().String;
|
||
|
|
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
|
||
|
|
bool DWARFExpression::printCompact(raw_ostream &OS, const MCRegisterInfo &MRI) {
|
||
|
|
return printCompactDWARFExpr(OS, begin(), end(), MRI);
|
||
|
|
}
|
||
|
|
|
||
|
|
} // namespace llvm
|