54 lines
2.0 KiB
C++
54 lines
2.0 KiB
C++
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//===-- llvm/CodeGen/AllocationOrder.cpp - Allocation Order ---------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements an allocation order for virtual registers.
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//
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// The preferred allocation order for a virtual register depends on allocation
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// hints and target hooks. The AllocationOrder class encapsulates all of that.
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//
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//===----------------------------------------------------------------------===//
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#include "AllocationOrder.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/RegisterClassInfo.h"
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#include "llvm/CodeGen/VirtRegMap.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "regalloc"
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// Compare VirtRegMap::getRegAllocPref().
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AllocationOrder AllocationOrder::create(unsigned VirtReg, const VirtRegMap &VRM,
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const RegisterClassInfo &RegClassInfo,
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const LiveRegMatrix *Matrix) {
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const MachineFunction &MF = VRM.getMachineFunction();
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const TargetRegisterInfo *TRI = &VRM.getTargetRegInfo();
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auto Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg));
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SmallVector<MCPhysReg, 16> Hints;
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bool HardHints =
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TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM, Matrix);
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LLVM_DEBUG({
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if (!Hints.empty()) {
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dbgs() << "hints:";
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for (unsigned I = 0, E = Hints.size(); I != E; ++I)
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dbgs() << ' ' << printReg(Hints[I], TRI);
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dbgs() << '\n';
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}
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});
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#ifndef NDEBUG
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for (unsigned I = 0, E = Hints.size(); I != E; ++I)
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assert(is_contained(Order, Hints[I]) &&
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"Target hint is outside allocation order.");
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#endif
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return AllocationOrder(std::move(Hints), Order, HardHints);
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}
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