371 lines
15 KiB
TableGen
371 lines
15 KiB
TableGen
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//===- IntrinsicsWebAssembly.td - Defines wasm intrinsics --*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file defines all of the WebAssembly-specific intrinsics.
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///
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//===----------------------------------------------------------------------===//
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let TargetPrefix = "wasm" in { // All intrinsics start with "llvm.wasm.".
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// Query the current memory size, and increase the current memory size.
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// Note that memory.size is not IntrNoMem because it must be sequenced with
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// respect to memory.grow calls.
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def int_wasm_memory_size : Intrinsic<[llvm_anyint_ty],
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[llvm_i32_ty],
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[IntrReadMem]>;
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def int_wasm_memory_grow : Intrinsic<[llvm_anyint_ty],
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[llvm_i32_ty, LLVMMatchType<0>],
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[]>;
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//===----------------------------------------------------------------------===//
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// Trapping float-to-int conversions
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//===----------------------------------------------------------------------===//
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def int_wasm_trunc_signed : Intrinsic<[llvm_anyint_ty],
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[llvm_anyfloat_ty],
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[IntrNoMem]>;
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def int_wasm_trunc_unsigned : Intrinsic<[llvm_anyint_ty],
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[llvm_anyfloat_ty],
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[IntrNoMem]>;
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//===----------------------------------------------------------------------===//
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// Saturating float-to-int conversions
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//===----------------------------------------------------------------------===//
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def int_wasm_trunc_saturate_signed : Intrinsic<[llvm_anyint_ty],
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[llvm_anyfloat_ty],
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[IntrNoMem, IntrSpeculatable]>;
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def int_wasm_trunc_saturate_unsigned : Intrinsic<[llvm_anyint_ty],
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[llvm_anyfloat_ty],
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[IntrNoMem, IntrSpeculatable]>;
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//===----------------------------------------------------------------------===//
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// Exception handling intrinsics
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//===----------------------------------------------------------------------===//
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// throw / rethrow
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// The immediate argument is an index to a tag, which is 0 for C++.
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def int_wasm_throw : Intrinsic<[], [llvm_i32_ty, llvm_ptr_ty],
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[Throws, IntrNoReturn, ImmArg<ArgIndex<0>>]>;
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def int_wasm_rethrow : Intrinsic<[], [], [Throws, IntrNoReturn]>;
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// Since wasm does not use landingpad instructions, these instructions return
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// exception pointer and selector values until we lower them in WasmEHPrepare.
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def int_wasm_get_exception : Intrinsic<[llvm_ptr_ty], [llvm_token_ty],
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[IntrHasSideEffects]>;
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def int_wasm_get_ehselector : Intrinsic<[llvm_i32_ty], [llvm_token_ty],
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[IntrHasSideEffects]>;
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// wasm.catch returns the pointer to the exception object caught by wasm 'catch'
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// instruction. This returns a single pointer, which is sufficient for C++
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// support. The immediate argument is an index to for a tag, which is 0 for C++.
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def int_wasm_catch : Intrinsic<[llvm_ptr_ty], [llvm_i32_ty],
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[IntrHasSideEffects, ImmArg<ArgIndex<0>>]>;
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// WebAssembly EH must maintain the landingpads in the order assigned to them
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// by WasmEHPrepare pass to generate landingpad table in EHStreamer. This is
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// used in order to give them the indices in WasmEHPrepare.
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def int_wasm_landingpad_index: Intrinsic<[], [llvm_token_ty, llvm_i32_ty],
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[IntrNoMem, ImmArg<ArgIndex<1>>]>;
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// Returns LSDA address of the current function.
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def int_wasm_lsda : Intrinsic<[llvm_ptr_ty], [], [IntrNoMem]>;
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//===----------------------------------------------------------------------===//
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// Atomic intrinsics
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//===----------------------------------------------------------------------===//
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// wait / notify
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def int_wasm_memory_atomic_wait32 :
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Intrinsic<[llvm_i32_ty],
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[LLVMPointerType<llvm_i32_ty>, llvm_i32_ty, llvm_i64_ty],
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[IntrInaccessibleMemOrArgMemOnly, ReadOnly<ArgIndex<0>>,
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NoCapture<ArgIndex<0>>, IntrHasSideEffects],
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"", [SDNPMemOperand]>;
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def int_wasm_memory_atomic_wait64 :
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Intrinsic<[llvm_i32_ty],
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[LLVMPointerType<llvm_i64_ty>, llvm_i64_ty, llvm_i64_ty],
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[IntrInaccessibleMemOrArgMemOnly, ReadOnly<ArgIndex<0>>,
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NoCapture<ArgIndex<0>>, IntrHasSideEffects],
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"", [SDNPMemOperand]>;
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def int_wasm_memory_atomic_notify:
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Intrinsic<[llvm_i32_ty], [LLVMPointerType<llvm_i32_ty>, llvm_i32_ty],
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[IntrInaccessibleMemOnly, NoCapture<ArgIndex<0>>,
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IntrHasSideEffects],
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"", [SDNPMemOperand]>;
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//===----------------------------------------------------------------------===//
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// SIMD intrinsics
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//===----------------------------------------------------------------------===//
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def int_wasm_swizzle :
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Intrinsic<[llvm_v16i8_ty],
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[llvm_v16i8_ty, llvm_v16i8_ty],
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[IntrNoMem, IntrSpeculatable]>;
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def int_wasm_shuffle :
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Intrinsic<[llvm_v16i8_ty],
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[llvm_v16i8_ty, llvm_v16i8_ty, llvm_i32_ty, llvm_i32_ty,
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llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
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llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
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llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
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[IntrNoMem, IntrSpeculatable]>;
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def int_wasm_sub_saturate_signed :
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Intrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>, LLVMMatchType<0>],
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[IntrNoMem, IntrSpeculatable]>;
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def int_wasm_sub_saturate_unsigned :
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Intrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>, LLVMMatchType<0>],
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[IntrNoMem, IntrSpeculatable]>;
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def int_wasm_avgr_unsigned :
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Intrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>, LLVMMatchType<0>],
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[IntrNoMem, IntrSpeculatable]>;
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def int_wasm_bitselect :
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Intrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
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[IntrNoMem, IntrSpeculatable]>;
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def int_wasm_anytrue :
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Intrinsic<[llvm_i32_ty],
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[llvm_anyvector_ty],
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[IntrNoMem, IntrSpeculatable]>;
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def int_wasm_alltrue :
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Intrinsic<[llvm_i32_ty],
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[llvm_anyvector_ty],
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[IntrNoMem, IntrSpeculatable]>;
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def int_wasm_bitmask :
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Intrinsic<[llvm_i32_ty],
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[llvm_anyvector_ty],
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[IntrNoMem, IntrSpeculatable]>;
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def int_wasm_qfma :
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Intrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
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[IntrNoMem, IntrSpeculatable]>;
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def int_wasm_qfms :
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Intrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
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[IntrNoMem, IntrSpeculatable]>;
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def int_wasm_dot :
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Intrinsic<[llvm_v4i32_ty],
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[llvm_v8i16_ty, llvm_v8i16_ty],
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[IntrNoMem, IntrSpeculatable]>;
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def int_wasm_narrow_signed :
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Intrinsic<[llvm_anyvector_ty],
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[llvm_anyvector_ty, LLVMMatchType<1>],
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[IntrNoMem, IntrSpeculatable]>;
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def int_wasm_narrow_unsigned :
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Intrinsic<[llvm_anyvector_ty],
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[llvm_anyvector_ty, LLVMMatchType<1>],
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[IntrNoMem, IntrSpeculatable]>;
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// TODO: Replace these intrinsics with normal ISel patterns once i32x4 to i64x2
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// widening is merged to the proposal.
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def int_wasm_widen_low_signed :
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Intrinsic<[llvm_v2i64_ty], [llvm_v4i32_ty], [IntrNoMem, IntrSpeculatable]>;
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def int_wasm_widen_high_signed :
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Intrinsic<[llvm_v2i64_ty], [llvm_v4i32_ty], [IntrNoMem, IntrSpeculatable]>;
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def int_wasm_widen_low_unsigned :
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Intrinsic<[llvm_v2i64_ty], [llvm_v4i32_ty], [IntrNoMem, IntrSpeculatable]>;
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def int_wasm_widen_high_unsigned :
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Intrinsic<[llvm_v2i64_ty], [llvm_v4i32_ty], [IntrNoMem, IntrSpeculatable]>;
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def int_wasm_q15mulr_saturate_signed :
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Intrinsic<[llvm_v8i16_ty],
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[llvm_v8i16_ty, llvm_v8i16_ty],
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[IntrNoMem, IntrSpeculatable]>;
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// TODO: Replace these intrinsics with normal ISel patterns
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def int_wasm_pmin :
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Intrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>, LLVMMatchType<0>],
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[IntrNoMem, IntrSpeculatable]>;
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def int_wasm_pmax :
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Intrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>, LLVMMatchType<0>],
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[IntrNoMem, IntrSpeculatable]>;
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// TODO: Replace these instrinsics with normal ISel patterns once the
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// rounding instructions are merged to the proposal
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// (https://github.com/WebAssembly/simd/pull/232).
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def int_wasm_ceil :
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Intrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>],
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[IntrNoMem, IntrSpeculatable]>;
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def int_wasm_floor :
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Intrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>],
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[IntrNoMem, IntrSpeculatable]>;
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def int_wasm_trunc :
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Intrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>],
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[IntrNoMem, IntrSpeculatable]>;
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def int_wasm_nearest :
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Intrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>],
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[IntrNoMem, IntrSpeculatable]>;
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// TODO: Replace these intrinsic with normal ISel patterns once the
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// load_zero instructions are merged to the proposal.
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def int_wasm_load32_zero :
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Intrinsic<[llvm_v4i32_ty],
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[LLVMPointerType<llvm_i32_ty>],
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[IntrReadMem, IntrArgMemOnly],
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"", [SDNPMemOperand]>;
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def int_wasm_load64_zero :
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Intrinsic<[llvm_v2i64_ty],
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[LLVMPointerType<llvm_i64_ty>],
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[IntrReadMem, IntrArgMemOnly],
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"", [SDNPMemOperand]>;
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// These intrinsics do not mark their lane index arguments as immediate because
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// that changes the corresponding SDNode from ISD::Constant to
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// ISD::TargetConstant, which would require extra complications in the ISel
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// tablegen patterns. TODO: Replace these intrinsic with normal ISel patterns
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// once the load_lane instructions are merged to the proposal.
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def int_wasm_load8_lane :
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Intrinsic<[llvm_v16i8_ty],
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[LLVMPointerType<llvm_i8_ty>, llvm_v16i8_ty, llvm_i32_ty],
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[IntrReadMem, IntrArgMemOnly],
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"", [SDNPMemOperand]>;
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def int_wasm_load16_lane :
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Intrinsic<[llvm_v8i16_ty],
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[LLVMPointerType<llvm_i16_ty>, llvm_v8i16_ty, llvm_i32_ty],
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[IntrReadMem, IntrArgMemOnly],
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"", [SDNPMemOperand]>;
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def int_wasm_load32_lane :
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Intrinsic<[llvm_v4i32_ty],
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[LLVMPointerType<llvm_i32_ty>, llvm_v4i32_ty, llvm_i32_ty],
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[IntrReadMem, IntrArgMemOnly],
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"", [SDNPMemOperand]>;
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def int_wasm_load64_lane :
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Intrinsic<[llvm_v2i64_ty],
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[LLVMPointerType<llvm_i64_ty>, llvm_v2i64_ty, llvm_i32_ty],
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[IntrReadMem, IntrArgMemOnly],
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"", [SDNPMemOperand]>;
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def int_wasm_store8_lane :
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Intrinsic<[],
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[LLVMPointerType<llvm_i8_ty>, llvm_v16i8_ty, llvm_i32_ty],
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[IntrWriteMem, IntrArgMemOnly],
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"", [SDNPMemOperand]>;
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def int_wasm_store16_lane :
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Intrinsic<[],
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[LLVMPointerType<llvm_i16_ty>, llvm_v8i16_ty, llvm_i32_ty],
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[IntrWriteMem, IntrArgMemOnly],
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"", [SDNPMemOperand]>;
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def int_wasm_store32_lane :
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Intrinsic<[],
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[LLVMPointerType<llvm_i32_ty>, llvm_v4i32_ty, llvm_i32_ty],
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[IntrWriteMem, IntrArgMemOnly],
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"", [SDNPMemOperand]>;
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def int_wasm_store64_lane :
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Intrinsic<[],
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[LLVMPointerType<llvm_i64_ty>, llvm_v2i64_ty, llvm_i32_ty],
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[IntrWriteMem, IntrArgMemOnly],
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"", [SDNPMemOperand]>;
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// TODO: Replace this intrinsic with normal ISel patterns once popcnt is merged
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// to the proposal.
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def int_wasm_popcnt :
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Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty], [IntrNoMem, IntrSpeculatable]>;
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def int_wasm_extmul_low_signed :
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Intrinsic<[llvm_anyvector_ty],
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[LLVMSubdivide2VectorType<0>, LLVMSubdivide2VectorType<0>],
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[IntrNoMem, IntrSpeculatable]>;
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def int_wasm_extmul_high_signed :
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Intrinsic<[llvm_anyvector_ty],
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[LLVMSubdivide2VectorType<0>, LLVMSubdivide2VectorType<0>],
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[IntrNoMem, IntrSpeculatable]>;
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def int_wasm_extmul_low_unsigned :
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Intrinsic<[llvm_anyvector_ty],
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[LLVMSubdivide2VectorType<0>, LLVMSubdivide2VectorType<0>],
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[IntrNoMem, IntrSpeculatable]>;
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def int_wasm_extmul_high_unsigned :
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Intrinsic<[llvm_anyvector_ty],
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[LLVMSubdivide2VectorType<0>, LLVMSubdivide2VectorType<0>],
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[IntrNoMem, IntrSpeculatable]>;
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def int_wasm_extadd_pairwise_signed :
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Intrinsic<[llvm_anyvector_ty],
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[LLVMSubdivide2VectorType<0>],
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[IntrNoMem, IntrSpeculatable]>;
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def int_wasm_extadd_pairwise_unsigned :
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Intrinsic<[llvm_anyvector_ty],
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[LLVMSubdivide2VectorType<0>],
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[IntrNoMem, IntrSpeculatable]>;
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def int_wasm_signselect :
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Intrinsic<[llvm_anyvector_ty],
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[LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
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[IntrNoMem, IntrSpeculatable]>;
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|
|
// TODO: Remove this intrinsic and the associated builtin if i64x2.eq gets
|
||
|
|
// merged to the proposal.
|
||
|
|
def int_wasm_eq :
|
||
|
|
Intrinsic<[llvm_v2i64_ty],
|
||
|
|
[llvm_v2i64_ty, llvm_v2i64_ty],
|
||
|
|
[IntrNoMem, IntrSpeculatable]>;
|
||
|
|
|
||
|
|
// TODO: Remove this after experiments have been run. Use the target-agnostic
|
||
|
|
// int_prefetch if this becomes specified at some point.
|
||
|
|
def int_wasm_prefetch_t :
|
||
|
|
Intrinsic<[], [llvm_ptr_ty],
|
||
|
|
[IntrInaccessibleMemOrArgMemOnly, IntrWillReturn,
|
||
|
|
ReadOnly<ArgIndex<0>>, NoCapture<ArgIndex<0>>],
|
||
|
|
"", [SDNPMemOperand]>;
|
||
|
|
|
||
|
|
def int_wasm_prefetch_nt :
|
||
|
|
Intrinsic<[], [llvm_ptr_ty],
|
||
|
|
[IntrInaccessibleMemOrArgMemOnly, IntrWillReturn,
|
||
|
|
ReadOnly<ArgIndex<0>>, NoCapture<ArgIndex<0>>],
|
||
|
|
"", [SDNPMemOperand]>;
|
||
|
|
|
||
|
|
// TODO: Remove these if possible if they are merged to the spec.
|
||
|
|
def int_wasm_convert_low_signed :
|
||
|
|
Intrinsic<[llvm_v2f64_ty], [llvm_v4i32_ty],
|
||
|
|
[IntrNoMem, IntrSpeculatable]>;
|
||
|
|
def int_wasm_convert_low_unsigned :
|
||
|
|
Intrinsic<[llvm_v2f64_ty], [llvm_v4i32_ty],
|
||
|
|
[IntrNoMem, IntrSpeculatable]>;
|
||
|
|
def int_wasm_trunc_saturate_zero_signed :
|
||
|
|
Intrinsic<[llvm_v4i32_ty], [llvm_v2f64_ty],
|
||
|
|
[IntrNoMem, IntrSpeculatable]>;
|
||
|
|
def int_wasm_trunc_saturate_zero_unsigned :
|
||
|
|
Intrinsic<[llvm_v4i32_ty], [llvm_v2f64_ty],
|
||
|
|
[IntrNoMem, IntrSpeculatable]>;
|
||
|
|
def int_wasm_demote_zero :
|
||
|
|
Intrinsic<[llvm_v4f32_ty], [llvm_v2f64_ty],
|
||
|
|
[IntrNoMem, IntrSpeculatable]>;
|
||
|
|
def int_wasm_promote_low :
|
||
|
|
Intrinsic<[llvm_v2f64_ty], [llvm_v4f32_ty],
|
||
|
|
[IntrNoMem, IntrSpeculatable]>;
|
||
|
|
|
||
|
|
//===----------------------------------------------------------------------===//
|
||
|
|
// Thread-local storage intrinsics
|
||
|
|
//===----------------------------------------------------------------------===//
|
||
|
|
|
||
|
|
def int_wasm_tls_size :
|
||
|
|
Intrinsic<[llvm_anyint_ty],
|
||
|
|
[],
|
||
|
|
[IntrNoMem, IntrSpeculatable]>;
|
||
|
|
|
||
|
|
def int_wasm_tls_align :
|
||
|
|
Intrinsic<[llvm_anyint_ty],
|
||
|
|
[],
|
||
|
|
[IntrNoMem, IntrSpeculatable]>;
|
||
|
|
|
||
|
|
def int_wasm_tls_base :
|
||
|
|
Intrinsic<[llvm_ptr_ty],
|
||
|
|
[],
|
||
|
|
[IntrReadMem]>;
|
||
|
|
|
||
|
|
} // TargetPrefix = "wasm"
|