283 lines
13 KiB
C
283 lines
13 KiB
C
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//==-- llvm/CodeGen/GlobalISel/Utils.h ---------------------------*- C++ -*-==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file This file declares the API of helper functions used throughout the
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/// GlobalISel pipeline.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_GLOBALISEL_UTILS_H
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#define LLVM_CODEGEN_GLOBALISEL_UTILS_H
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#include "llvm/ADT/StringRef.h"
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#include "llvm/CodeGen/Register.h"
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#include "llvm/Support/Alignment.h"
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#include "llvm/Support/LowLevelTypeImpl.h"
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#include <cstdint>
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namespace llvm {
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class AnalysisUsage;
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class GISelKnownBits;
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class MachineFunction;
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class MachineInstr;
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class MachineOperand;
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class MachineOptimizationRemarkEmitter;
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class MachineOptimizationRemarkMissed;
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struct MachinePointerInfo;
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class MachineRegisterInfo;
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class MCInstrDesc;
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class RegisterBankInfo;
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class TargetInstrInfo;
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class TargetLowering;
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class TargetPassConfig;
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class TargetRegisterInfo;
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class TargetRegisterClass;
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class ConstantFP;
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class APFloat;
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/// Try to constrain Reg to the specified register class. If this fails,
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/// create a new virtual register in the correct class.
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///
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/// \return The virtual register constrained to the right register class.
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Register constrainRegToClass(MachineRegisterInfo &MRI,
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const TargetInstrInfo &TII,
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const RegisterBankInfo &RBI, Register Reg,
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const TargetRegisterClass &RegClass);
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/// Constrain the Register operand OpIdx, so that it is now constrained to the
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/// TargetRegisterClass passed as an argument (RegClass).
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/// If this fails, create a new virtual register in the correct class and insert
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/// a COPY before \p InsertPt if it is a use or after if it is a definition.
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/// In both cases, the function also updates the register of RegMo. The debug
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/// location of \p InsertPt is used for the new copy.
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///
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/// \return The virtual register constrained to the right register class.
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Register constrainOperandRegClass(const MachineFunction &MF,
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const TargetRegisterInfo &TRI,
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MachineRegisterInfo &MRI,
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const TargetInstrInfo &TII,
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const RegisterBankInfo &RBI,
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MachineInstr &InsertPt,
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const TargetRegisterClass &RegClass,
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MachineOperand &RegMO);
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/// Try to constrain Reg so that it is usable by argument OpIdx of the provided
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/// MCInstrDesc \p II. If this fails, create a new virtual register in the
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/// correct class and insert a COPY before \p InsertPt if it is a use or after
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/// if it is a definition. In both cases, the function also updates the register
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/// of RegMo.
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/// This is equivalent to constrainOperandRegClass(..., RegClass, ...)
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/// with RegClass obtained from the MCInstrDesc. The debug location of \p
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/// InsertPt is used for the new copy.
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///
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/// \return The virtual register constrained to the right register class.
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Register constrainOperandRegClass(const MachineFunction &MF,
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const TargetRegisterInfo &TRI,
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MachineRegisterInfo &MRI,
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const TargetInstrInfo &TII,
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const RegisterBankInfo &RBI,
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MachineInstr &InsertPt, const MCInstrDesc &II,
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MachineOperand &RegMO, unsigned OpIdx);
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/// Mutate the newly-selected instruction \p I to constrain its (possibly
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/// generic) virtual register operands to the instruction's register class.
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/// This could involve inserting COPYs before (for uses) or after (for defs).
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/// This requires the number of operands to match the instruction description.
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/// \returns whether operand regclass constraining succeeded.
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///
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// FIXME: Not all instructions have the same number of operands. We should
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// probably expose a constrain helper per operand and let the target selector
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// constrain individual registers, like fast-isel.
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bool constrainSelectedInstRegOperands(MachineInstr &I,
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const TargetInstrInfo &TII,
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const TargetRegisterInfo &TRI,
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const RegisterBankInfo &RBI);
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/// Check if DstReg can be replaced with SrcReg depending on the register
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/// constraints.
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bool canReplaceReg(Register DstReg, Register SrcReg, MachineRegisterInfo &MRI);
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/// Check whether an instruction \p MI is dead: it only defines dead virtual
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/// registers, and doesn't have other side effects.
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bool isTriviallyDead(const MachineInstr &MI, const MachineRegisterInfo &MRI);
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/// Report an ISel error as a missed optimization remark to the LLVMContext's
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/// diagnostic stream. Set the FailedISel MachineFunction property.
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void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
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MachineOptimizationRemarkEmitter &MORE,
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MachineOptimizationRemarkMissed &R);
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void reportGISelFailure(MachineFunction &MF, const TargetPassConfig &TPC,
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MachineOptimizationRemarkEmitter &MORE,
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const char *PassName, StringRef Msg,
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const MachineInstr &MI);
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/// Report an ISel warning as a missed optimization remark to the LLVMContext's
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/// diagnostic stream.
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void reportGISelWarning(MachineFunction &MF, const TargetPassConfig &TPC,
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MachineOptimizationRemarkEmitter &MORE,
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MachineOptimizationRemarkMissed &R);
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/// If \p VReg is defined by a G_CONSTANT, return the corresponding value.
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Optional<APInt> getConstantVRegVal(Register VReg,
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const MachineRegisterInfo &MRI);
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/// If \p VReg is defined by a G_CONSTANT fits in int64_t
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/// returns it.
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Optional<int64_t> getConstantVRegSExtVal(Register VReg,
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const MachineRegisterInfo &MRI);
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/// Simple struct used to hold a constant integer value and a virtual
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/// register.
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struct ValueAndVReg {
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APInt Value;
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Register VReg;
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};
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/// If \p VReg is defined by a statically evaluable chain of
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/// instructions rooted on a G_F/CONSTANT (\p LookThroughInstrs == true)
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/// and that constant fits in int64_t, returns its value as well as the
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/// virtual register defined by this G_F/CONSTANT.
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/// When \p LookThroughInstrs == false this function behaves like
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/// getConstantVRegVal.
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/// When \p HandleFConstants == false the function bails on G_FCONSTANTs.
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/// When \p LookThroughAnyExt == true the function treats G_ANYEXT same as
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/// G_SEXT.
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Optional<ValueAndVReg>
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getConstantVRegValWithLookThrough(Register VReg, const MachineRegisterInfo &MRI,
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bool LookThroughInstrs = true,
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bool HandleFConstants = true,
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bool LookThroughAnyExt = false);
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const ConstantFP* getConstantFPVRegVal(Register VReg,
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const MachineRegisterInfo &MRI);
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/// See if Reg is defined by an single def instruction that is
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/// Opcode. Also try to do trivial folding if it's a COPY with
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/// same types. Returns null otherwise.
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MachineInstr *getOpcodeDef(unsigned Opcode, Register Reg,
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const MachineRegisterInfo &MRI);
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/// Simple struct used to hold a Register value and the instruction which
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/// defines it.
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struct DefinitionAndSourceRegister {
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MachineInstr *MI;
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Register Reg;
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};
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/// Find the def instruction for \p Reg, and underlying value Register folding
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/// away any copies.
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Optional<DefinitionAndSourceRegister>
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getDefSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI);
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/// Find the def instruction for \p Reg, folding away any trivial copies. May
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/// return nullptr if \p Reg is not a generic virtual register.
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MachineInstr *getDefIgnoringCopies(Register Reg,
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const MachineRegisterInfo &MRI);
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/// Find the source register for \p Reg, folding away any trivial copies. It
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/// will be an output register of the instruction that getDefIgnoringCopies
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/// returns. May return an invalid register if \p Reg is not a generic virtual
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/// register.
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Register getSrcRegIgnoringCopies(Register Reg,
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const MachineRegisterInfo &MRI);
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/// Returns an APFloat from Val converted to the appropriate size.
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APFloat getAPFloatFromSize(double Val, unsigned Size);
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/// Modify analysis usage so it preserves passes required for the SelectionDAG
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/// fallback.
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void getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU);
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Optional<APInt> ConstantFoldBinOp(unsigned Opcode, const Register Op1,
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const Register Op2,
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const MachineRegisterInfo &MRI);
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Optional<APInt> ConstantFoldExtOp(unsigned Opcode, const Register Op1,
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uint64_t Imm, const MachineRegisterInfo &MRI);
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/// Test if the given value is known to have exactly one bit set. This differs
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/// from computeKnownBits in that it doesn't necessarily determine which bit is
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/// set.
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bool isKnownToBeAPowerOfTwo(Register Val, const MachineRegisterInfo &MRI,
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GISelKnownBits *KnownBits = nullptr);
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/// Returns true if \p Val can be assumed to never be a NaN. If \p SNaN is true,
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/// this returns if \p Val can be assumed to never be a signaling NaN.
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bool isKnownNeverNaN(Register Val, const MachineRegisterInfo &MRI,
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bool SNaN = false);
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/// Returns true if \p Val can be assumed to never be a signaling NaN.
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inline bool isKnownNeverSNaN(Register Val, const MachineRegisterInfo &MRI) {
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return isKnownNeverNaN(Val, MRI, true);
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}
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Align inferAlignFromPtrInfo(MachineFunction &MF, const MachinePointerInfo &MPO);
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/// Return a virtual register corresponding to the incoming argument register \p
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/// PhysReg. This register is expected to have class \p RC, and optional type \p
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/// RegTy. This assumes all references to the register will use the same type.
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///
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/// If there is an existing live-in argument register, it will be returned.
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/// This will also ensure there is a valid copy
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Register getFunctionLiveInPhysReg(MachineFunction &MF, const TargetInstrInfo &TII,
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MCRegister PhysReg,
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const TargetRegisterClass &RC,
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LLT RegTy = LLT());
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/// Return the least common multiple type of \p OrigTy and \p TargetTy, by changing the
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/// number of vector elements or scalar bitwidth. The intent is a
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/// G_MERGE_VALUES, G_BUILD_VECTOR, or G_CONCAT_VECTORS can be constructed from
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/// \p OrigTy elements, and unmerged into \p TargetTy
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LLVM_READNONE
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LLT getLCMType(LLT OrigTy, LLT TargetTy);
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/// Return a type where the total size is the greatest common divisor of \p
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/// OrigTy and \p TargetTy. This will try to either change the number of vector
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/// elements, or bitwidth of scalars. The intent is the result type can be used
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/// as the result of a G_UNMERGE_VALUES from \p OrigTy, and then some
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/// combination of G_MERGE_VALUES, G_BUILD_VECTOR and G_CONCAT_VECTORS (possibly
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/// with intermediate casts) can re-form \p TargetTy.
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///
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/// If these are vectors with different element types, this will try to produce
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/// a vector with a compatible total size, but the element type of \p OrigTy. If
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/// this can't be satisfied, this will produce a scalar smaller than the
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/// original vector elements.
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///
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/// In the worst case, this returns LLT::scalar(1)
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LLVM_READNONE
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LLT getGCDType(LLT OrigTy, LLT TargetTy);
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/// \returns The splat index of a G_SHUFFLE_VECTOR \p MI when \p MI is a splat.
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/// If \p MI is not a splat, returns None.
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Optional<int> getSplatIndex(MachineInstr &MI);
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/// Returns a scalar constant of a G_BUILD_VECTOR splat if it exists.
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Optional<int64_t> getBuildVectorConstantSplat(const MachineInstr &MI,
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const MachineRegisterInfo &MRI);
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/// Return true if the specified instruction is a G_BUILD_VECTOR or
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/// G_BUILD_VECTOR_TRUNC where all of the elements are 0 or undef.
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bool isBuildVectorAllZeros(const MachineInstr &MI,
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const MachineRegisterInfo &MRI);
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/// Return true if the specified instruction is a G_BUILD_VECTOR or
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/// G_BUILD_VECTOR_TRUNC where all of the elements are ~0 or undef.
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bool isBuildVectorAllOnes(const MachineInstr &MI,
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const MachineRegisterInfo &MRI);
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/// Returns true if given the TargetLowering's boolean contents information,
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/// the value \p Val contains a true value.
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bool isConstTrueVal(const TargetLowering &TLI, int64_t Val, bool IsVector,
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bool IsFP);
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/// Returns an integer representing true, as defined by the
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/// TargetBooleanContents.
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int64_t getICmpTrueVal(const TargetLowering &TLI, bool IsVector, bool IsFP);
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} // End namespace llvm.
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#endif
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