398 lines
18 KiB
C
398 lines
18 KiB
C
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//== llvm/CodeGen/GlobalISel/LegalizerHelper.h ---------------- -*- C++ -*-==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file A pass to convert the target-illegal operations created by IR -> MIR
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/// translation into ones the target expects to be able to select. This may
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/// occur in multiple phases, for example G_ADD <2 x i8> -> G_ADD <2 x i16> ->
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/// G_ADD <4 x i16>.
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///
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/// The LegalizerHelper class is where most of the work happens, and is
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/// designed to be callable from other passes that find themselves with an
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/// illegal instruction.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_GLOBALISEL_MACHINELEGALIZEHELPER_H
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#define LLVM_CODEGEN_GLOBALISEL_MACHINELEGALIZEHELPER_H
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#include "llvm/CodeGen/GlobalISel/CallLowering.h"
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#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
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#include "llvm/CodeGen/LowLevelType.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/RuntimeLibcalls.h"
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namespace llvm {
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// Forward declarations.
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class LegalizerInfo;
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class Legalizer;
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class MachineRegisterInfo;
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class GISelChangeObserver;
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class TargetLowering;
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class LegalizerHelper {
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public:
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/// Expose MIRBuilder so clients can set their own RecordInsertInstruction
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/// functions
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MachineIRBuilder &MIRBuilder;
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/// To keep track of changes made by the LegalizerHelper.
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GISelChangeObserver &Observer;
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private:
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MachineRegisterInfo &MRI;
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const LegalizerInfo &LI;
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const TargetLowering &TLI;
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public:
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enum LegalizeResult {
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/// Instruction was already legal and no change was made to the
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/// MachineFunction.
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AlreadyLegal,
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/// Instruction has been legalized and the MachineFunction changed.
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Legalized,
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/// Some kind of error has occurred and we could not legalize this
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/// instruction.
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UnableToLegalize,
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};
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/// Expose LegalizerInfo so the clients can re-use.
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const LegalizerInfo &getLegalizerInfo() const { return LI; }
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const TargetLowering &getTargetLowering() const { return TLI; }
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LegalizerHelper(MachineFunction &MF, GISelChangeObserver &Observer,
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MachineIRBuilder &B);
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LegalizerHelper(MachineFunction &MF, const LegalizerInfo &LI,
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GISelChangeObserver &Observer, MachineIRBuilder &B);
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/// Replace \p MI by a sequence of legal instructions that can implement the
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/// same operation. Note that this means \p MI may be deleted, so any iterator
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/// steps should be performed before calling this function. \p Helper should
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/// be initialized to the MachineFunction containing \p MI.
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///
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/// Considered as an opaque blob, the legal code will use and define the same
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/// registers as \p MI.
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LegalizeResult legalizeInstrStep(MachineInstr &MI);
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/// Legalize an instruction by emiting a runtime library call instead.
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LegalizeResult libcall(MachineInstr &MI);
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/// Legalize an instruction by reducing the width of the underlying scalar
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/// type.
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LegalizeResult narrowScalar(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy);
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/// Legalize an instruction by performing the operation on a wider scalar type
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/// (for example a 16-bit addition can be safely performed at 32-bits
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/// precision, ignoring the unused bits).
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LegalizeResult widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
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/// Legalize an instruction by replacing the value type
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LegalizeResult bitcast(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
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/// Legalize an instruction by splitting it into simpler parts, hopefully
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/// understood by the target.
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LegalizeResult lower(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
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/// Legalize a vector instruction by splitting into multiple components, each
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/// acting on the same scalar type as the original but with fewer elements.
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LegalizeResult fewerElementsVector(MachineInstr &MI, unsigned TypeIdx,
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LLT NarrowTy);
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/// Legalize a vector instruction by increasing the number of vector elements
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/// involved and ignoring the added elements later.
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LegalizeResult moreElementsVector(MachineInstr &MI, unsigned TypeIdx,
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LLT MoreTy);
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/// Cast the given value to an LLT::scalar with an equivalent size. Returns
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/// the register to use if an instruction was inserted. Returns the original
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/// register if no coercion was necessary.
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//
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// This may also fail and return Register() if there is no legal way to cast.
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Register coerceToScalar(Register Val);
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/// Legalize a single operand \p OpIdx of the machine instruction \p MI as a
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/// Use by extending the operand's type to \p WideTy using the specified \p
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/// ExtOpcode for the extension instruction, and replacing the vreg of the
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/// operand in place.
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void widenScalarSrc(MachineInstr &MI, LLT WideTy, unsigned OpIdx,
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unsigned ExtOpcode);
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/// Legalize a single operand \p OpIdx of the machine instruction \p MI as a
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/// Use by truncating the operand's type to \p NarrowTy using G_TRUNC, and
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/// replacing the vreg of the operand in place.
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void narrowScalarSrc(MachineInstr &MI, LLT NarrowTy, unsigned OpIdx);
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/// Legalize a single operand \p OpIdx of the machine instruction \p MI as a
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/// Def by extending the operand's type to \p WideTy and truncating it back
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/// with the \p TruncOpcode, and replacing the vreg of the operand in place.
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void widenScalarDst(MachineInstr &MI, LLT WideTy, unsigned OpIdx = 0,
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unsigned TruncOpcode = TargetOpcode::G_TRUNC);
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// Legalize a single operand \p OpIdx of the machine instruction \p MI as a
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// Def by truncating the operand's type to \p NarrowTy, replacing in place and
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// extending back with \p ExtOpcode.
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void narrowScalarDst(MachineInstr &MI, LLT NarrowTy, unsigned OpIdx,
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unsigned ExtOpcode);
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/// Legalize a single operand \p OpIdx of the machine instruction \p MI as a
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/// Def by performing it with additional vector elements and extracting the
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/// result elements, and replacing the vreg of the operand in place.
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void moreElementsVectorDst(MachineInstr &MI, LLT MoreTy, unsigned OpIdx);
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/// Legalize a single operand \p OpIdx of the machine instruction \p MI as a
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/// Use by producing a vector with undefined high elements, extracting the
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/// original vector type, and replacing the vreg of the operand in place.
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void moreElementsVectorSrc(MachineInstr &MI, LLT MoreTy, unsigned OpIdx);
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/// Legalize a single operand \p OpIdx of the machine instruction \p MI as a
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/// use by inserting a G_BITCAST to \p CastTy
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void bitcastSrc(MachineInstr &MI, LLT CastTy, unsigned OpIdx);
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/// Legalize a single operand \p OpIdx of the machine instruction \p MI as a
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/// def by inserting a G_BITCAST from \p CastTy
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void bitcastDst(MachineInstr &MI, LLT CastTy, unsigned OpIdx);
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/// Widen \p OrigReg to \p WideTy by merging to a wider type, padding with
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/// G_IMPLICIT_DEF, and producing dead results.
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Register widenWithUnmerge(LLT WideTy, Register OrigReg);
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private:
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LegalizeResult
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widenScalarMergeValues(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
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LegalizeResult
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widenScalarUnmergeValues(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
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LegalizeResult
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widenScalarExtract(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
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LegalizeResult
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widenScalarInsert(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
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LegalizeResult widenScalarAddoSubo(MachineInstr &MI, unsigned TypeIdx,
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LLT WideTy);
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LegalizeResult widenScalarAddSubShlSat(MachineInstr &MI, unsigned TypeIdx,
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LLT WideTy);
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/// Helper function to split a wide generic register into bitwise blocks with
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/// the given Type (which implies the number of blocks needed). The generic
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/// registers created are appended to Ops, starting at bit 0 of Reg.
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void extractParts(Register Reg, LLT Ty, int NumParts,
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SmallVectorImpl<Register> &VRegs);
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/// Version which handles irregular splits.
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bool extractParts(Register Reg, LLT RegTy, LLT MainTy,
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LLT &LeftoverTy,
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SmallVectorImpl<Register> &VRegs,
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SmallVectorImpl<Register> &LeftoverVRegs);
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/// Helper function to build a wide generic register \p DstReg of type \p
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/// RegTy from smaller parts. This will produce a G_MERGE_VALUES,
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/// G_BUILD_VECTOR, G_CONCAT_VECTORS, or sequence of G_INSERT as appropriate
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/// for the types.
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///
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/// \p PartRegs must be registers of type \p PartTy.
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///
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/// If \p ResultTy does not evenly break into \p PartTy sized pieces, the
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/// remainder must be specified with \p LeftoverRegs of type \p LeftoverTy.
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void insertParts(Register DstReg, LLT ResultTy,
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LLT PartTy, ArrayRef<Register> PartRegs,
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LLT LeftoverTy = LLT(), ArrayRef<Register> LeftoverRegs = {});
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/// Unmerge \p SrcReg into smaller sized values, and append them to \p
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/// Parts. The elements of \p Parts will be the greatest common divisor type
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/// of \p DstTy, \p NarrowTy and the type of \p SrcReg. This will compute and
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/// return the GCD type.
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LLT extractGCDType(SmallVectorImpl<Register> &Parts, LLT DstTy,
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LLT NarrowTy, Register SrcReg);
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/// Unmerge \p SrcReg into \p GCDTy typed registers. This will append all of
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/// the unpacked registers to \p Parts. This version is if the common unmerge
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/// type is already known.
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void extractGCDType(SmallVectorImpl<Register> &Parts, LLT GCDTy,
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Register SrcReg);
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/// Produce a merge of values in \p VRegs to define \p DstReg. Perform a merge
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/// from the least common multiple type, and convert as appropriate to \p
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/// DstReg.
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///
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/// \p VRegs should each have type \p GCDTy. This type should be greatest
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/// common divisor type of \p DstReg, \p NarrowTy, and an undetermined source
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/// type.
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///
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/// \p NarrowTy is the desired result merge source type. If the source value
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/// needs to be widened to evenly cover \p DstReg, inserts high bits
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/// corresponding to the extension opcode \p PadStrategy.
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///
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/// \p VRegs will be cleared, and the the result \p NarrowTy register pieces
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/// will replace it. Returns The complete LCMTy that \p VRegs will cover when
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/// merged.
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LLT buildLCMMergePieces(LLT DstTy, LLT NarrowTy, LLT GCDTy,
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SmallVectorImpl<Register> &VRegs,
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unsigned PadStrategy = TargetOpcode::G_ANYEXT);
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/// Merge the values in \p RemergeRegs to an \p LCMTy typed value. Extract the
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/// low bits into \p DstReg. This is intended to use the outputs from
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/// buildLCMMergePieces after processing.
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void buildWidenedRemergeToDst(Register DstReg, LLT LCMTy,
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ArrayRef<Register> RemergeRegs);
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/// Perform generic multiplication of values held in multiple registers.
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/// Generated instructions use only types NarrowTy and i1.
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/// Destination can be same or two times size of the source.
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void multiplyRegisters(SmallVectorImpl<Register> &DstRegs,
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ArrayRef<Register> Src1Regs,
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ArrayRef<Register> Src2Regs, LLT NarrowTy);
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void changeOpcode(MachineInstr &MI, unsigned NewOpcode);
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public:
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/// Return the alignment to use for a stack temporary object with the given
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/// type.
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Align getStackTemporaryAlignment(LLT Type, Align MinAlign = Align()) const;
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/// Create a stack temporary based on the size in bytes and the alignment
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MachineInstrBuilder createStackTemporary(TypeSize Bytes, Align Alignment,
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MachinePointerInfo &PtrInfo);
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/// Get a pointer to vector element \p Index located in memory for a vector of
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/// type \p VecTy starting at a base address of \p VecPtr. If \p Index is out
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/// of bounds the returned pointer is unspecified, but will be within the
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/// vector bounds.
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Register getVectorElementPointer(Register VecPtr, LLT VecTy, Register Index);
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LegalizeResult fewerElementsVectorImplicitDef(MachineInstr &MI,
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unsigned TypeIdx, LLT NarrowTy);
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/// Legalize a instruction with a vector type where each operand may have a
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/// different element type. All type indexes must have the same number of
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/// elements.
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LegalizeResult fewerElementsVectorMultiEltType(MachineInstr &MI,
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unsigned TypeIdx, LLT NarrowTy);
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LegalizeResult fewerElementsVectorCasts(MachineInstr &MI, unsigned TypeIdx,
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LLT NarrowTy);
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LegalizeResult
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fewerElementsVectorCmp(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy);
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LegalizeResult
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fewerElementsVectorSelect(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy);
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LegalizeResult fewerElementsVectorPhi(MachineInstr &MI,
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unsigned TypeIdx, LLT NarrowTy);
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LegalizeResult moreElementsVectorPhi(MachineInstr &MI, unsigned TypeIdx,
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LLT MoreTy);
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LegalizeResult fewerElementsVectorUnmergeValues(MachineInstr &MI,
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unsigned TypeIdx,
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LLT NarrowTy);
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LegalizeResult fewerElementsVectorMerge(MachineInstr &MI, unsigned TypeIdx,
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LLT NarrowTy);
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LegalizeResult fewerElementsVectorExtractInsertVectorElt(MachineInstr &MI,
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unsigned TypeIdx,
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LLT NarrowTy);
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LegalizeResult
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reduceLoadStoreWidth(MachineInstr &MI, unsigned TypeIdx, LLT NarrowTy);
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/// Legalize an instruction by reducing the operation width, either by
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/// narrowing the type of the operation or by reducing the number of elements
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/// of a vector.
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/// The used strategy (narrow vs. fewerElements) is decided by \p NarrowTy.
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/// Narrow is used if the scalar type of \p NarrowTy and \p DstTy differ,
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/// fewerElements is used when the scalar type is the same but the number of
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/// elements between \p NarrowTy and \p DstTy differ.
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LegalizeResult reduceOperationWidth(MachineInstr &MI, unsigned TypeIdx,
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LLT NarrowTy);
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LegalizeResult fewerElementsVectorSextInReg(MachineInstr &MI, unsigned TypeIdx,
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LLT NarrowTy);
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LegalizeResult narrowScalarShiftByConstant(MachineInstr &MI, const APInt &Amt,
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LLT HalfTy, LLT ShiftAmtTy);
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LegalizeResult narrowScalarShift(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
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LegalizeResult narrowScalarMul(MachineInstr &MI, LLT Ty);
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LegalizeResult narrowScalarExtract(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
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LegalizeResult narrowScalarInsert(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
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LegalizeResult narrowScalarBasic(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
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LegalizeResult narrowScalarExt(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
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LegalizeResult narrowScalarSelect(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
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LegalizeResult narrowScalarCTLZ(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
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LegalizeResult narrowScalarCTTZ(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
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LegalizeResult narrowScalarCTPOP(MachineInstr &MI, unsigned TypeIdx, LLT Ty);
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/// Perform Bitcast legalize action on G_EXTRACT_VECTOR_ELT.
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LegalizeResult bitcastExtractVectorElt(MachineInstr &MI, unsigned TypeIdx,
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LLT CastTy);
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/// Perform Bitcast legalize action on G_INSERT_VECTOR_ELT.
|
||
|
|
LegalizeResult bitcastInsertVectorElt(MachineInstr &MI, unsigned TypeIdx,
|
||
|
|
LLT CastTy);
|
||
|
|
|
||
|
|
LegalizeResult lowerBitcast(MachineInstr &MI);
|
||
|
|
LegalizeResult lowerLoad(MachineInstr &MI);
|
||
|
|
LegalizeResult lowerStore(MachineInstr &MI);
|
||
|
|
LegalizeResult lowerBitCount(MachineInstr &MI);
|
||
|
|
|
||
|
|
LegalizeResult lowerU64ToF32BitOps(MachineInstr &MI);
|
||
|
|
LegalizeResult lowerUITOFP(MachineInstr &MI);
|
||
|
|
LegalizeResult lowerSITOFP(MachineInstr &MI);
|
||
|
|
LegalizeResult lowerFPTOUI(MachineInstr &MI);
|
||
|
|
LegalizeResult lowerFPTOSI(MachineInstr &MI);
|
||
|
|
|
||
|
|
LegalizeResult lowerFPTRUNC_F64_TO_F16(MachineInstr &MI);
|
||
|
|
LegalizeResult lowerFPTRUNC(MachineInstr &MI);
|
||
|
|
LegalizeResult lowerFPOWI(MachineInstr &MI);
|
||
|
|
|
||
|
|
LegalizeResult lowerMinMax(MachineInstr &MI);
|
||
|
|
LegalizeResult lowerFCopySign(MachineInstr &MI);
|
||
|
|
LegalizeResult lowerFMinNumMaxNum(MachineInstr &MI);
|
||
|
|
LegalizeResult lowerFMad(MachineInstr &MI);
|
||
|
|
LegalizeResult lowerIntrinsicRound(MachineInstr &MI);
|
||
|
|
LegalizeResult lowerFFloor(MachineInstr &MI);
|
||
|
|
LegalizeResult lowerMergeValues(MachineInstr &MI);
|
||
|
|
LegalizeResult lowerUnmergeValues(MachineInstr &MI);
|
||
|
|
LegalizeResult lowerExtractInsertVectorElt(MachineInstr &MI);
|
||
|
|
LegalizeResult lowerShuffleVector(MachineInstr &MI);
|
||
|
|
LegalizeResult lowerDynStackAlloc(MachineInstr &MI);
|
||
|
|
LegalizeResult lowerExtract(MachineInstr &MI);
|
||
|
|
LegalizeResult lowerInsert(MachineInstr &MI);
|
||
|
|
LegalizeResult lowerSADDO_SSUBO(MachineInstr &MI);
|
||
|
|
LegalizeResult lowerAddSubSatToMinMax(MachineInstr &MI);
|
||
|
|
LegalizeResult lowerAddSubSatToAddoSubo(MachineInstr &MI);
|
||
|
|
LegalizeResult lowerShlSat(MachineInstr &MI);
|
||
|
|
LegalizeResult lowerBswap(MachineInstr &MI);
|
||
|
|
LegalizeResult lowerBitreverse(MachineInstr &MI);
|
||
|
|
LegalizeResult lowerReadWriteRegister(MachineInstr &MI);
|
||
|
|
LegalizeResult lowerSMULH_UMULH(MachineInstr &MI);
|
||
|
|
LegalizeResult lowerSelect(MachineInstr &MI);
|
||
|
|
|
||
|
|
};
|
||
|
|
|
||
|
|
/// Helper function that creates a libcall to the given \p Name using the given
|
||
|
|
/// calling convention \p CC.
|
||
|
|
LegalizerHelper::LegalizeResult
|
||
|
|
createLibcall(MachineIRBuilder &MIRBuilder, const char *Name,
|
||
|
|
const CallLowering::ArgInfo &Result,
|
||
|
|
ArrayRef<CallLowering::ArgInfo> Args, CallingConv::ID CC);
|
||
|
|
|
||
|
|
/// Helper function that creates the given libcall.
|
||
|
|
LegalizerHelper::LegalizeResult
|
||
|
|
createLibcall(MachineIRBuilder &MIRBuilder, RTLIB::Libcall Libcall,
|
||
|
|
const CallLowering::ArgInfo &Result,
|
||
|
|
ArrayRef<CallLowering::ArgInfo> Args);
|
||
|
|
|
||
|
|
/// Create a libcall to memcpy et al.
|
||
|
|
LegalizerHelper::LegalizeResult createMemLibcall(MachineIRBuilder &MIRBuilder,
|
||
|
|
MachineRegisterInfo &MRI,
|
||
|
|
MachineInstr &MI);
|
||
|
|
|
||
|
|
} // End namespace llvm.
|
||
|
|
|
||
|
|
#endif
|