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2
.gitignore
vendored
2
.gitignore
vendored
@ -9,5 +9,3 @@
|
||||
/mpfr-*/
|
||||
/build-*/
|
||||
/linux-*/
|
||||
/isl-*/
|
||||
/build/
|
||||
|
||||
16
COPYRIGHT
16
COPYRIGHT
@ -1,16 +0,0 @@
|
||||
Copyright Notes
|
||||
===============
|
||||
|
||||
The musl-cross-make build tools and documentation are licensed under
|
||||
the MIT/Expat license as found in the `LICENSE` file.
|
||||
|
||||
Note that this license does not cover the patches (`patches/`) or
|
||||
resulting binary artifacts.
|
||||
|
||||
Each patch (`patches/`) is distributed under the terms of the license
|
||||
of the upstream project to which it is applied.
|
||||
|
||||
Similarly, any resulting binary artifacts produced using this build
|
||||
tooling retain the original licensing from the upstream projects. The
|
||||
authors of musl-cross-make do not make any additional copyright claims
|
||||
to these artifacts.
|
||||
19
LICENSE
19
LICENSE
@ -1,19 +0,0 @@
|
||||
Copyright (c) 2015-2020 Rich Felker, et al.
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in
|
||||
all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
THE SOFTWARE.
|
||||
89
Makefile
89
Makefile
@ -2,36 +2,40 @@
|
||||
SOURCES = sources
|
||||
|
||||
CONFIG_SUB_REV = 3d5db9ebe860
|
||||
BINUTILS_VER = 2.33.1
|
||||
GCC_VER = 9.4.0
|
||||
MUSL_VER = 1.2.5
|
||||
GMP_VER = 6.1.2
|
||||
MPC_VER = 1.1.0
|
||||
MPFR_VER = 4.0.2
|
||||
LINUX_VER = headers-4.19.88-2
|
||||
BINUTILS_VER = 2.27
|
||||
GCC_VER = 6.3.0
|
||||
MUSL_VER = 1.1.18
|
||||
GMP_VER = 6.1.1
|
||||
MPC_VER = 1.0.3
|
||||
MPFR_VER = 3.1.4
|
||||
LINUX_VER = 4.4.10
|
||||
|
||||
GNU_SITE = https://ftpmirror.gnu.org/gnu
|
||||
GNU_SITE = https://ftp.gnu.org/pub/gnu
|
||||
GCC_SITE = $(GNU_SITE)/gcc
|
||||
BINUTILS_SITE = $(GNU_SITE)/binutils
|
||||
GMP_SITE = $(GNU_SITE)/gmp
|
||||
MPC_SITE = $(GNU_SITE)/mpc
|
||||
MPFR_SITE = $(GNU_SITE)/mpfr
|
||||
ISL_SITE = https://downloads.sourceforge.net/project/libisl/
|
||||
ISL_SITE = http://isl.gforge.inria.fr/
|
||||
|
||||
MUSL_SITE = https://musl.libc.org/releases
|
||||
MUSL_REPO = https://git.musl-libc.org/git/musl
|
||||
MUSL_SITE = https://www.musl-libc.org/releases
|
||||
MUSL_REPO = git://git.musl-libc.org/musl
|
||||
|
||||
LINUX_SITE = https://cdn.kernel.org/pub/linux/kernel
|
||||
LINUX_HEADERS_SITE = https://ftp.barfooze.de/pub/sabotage/tarballs/
|
||||
|
||||
DL_CMD = wget -c -O
|
||||
SHA1_CMD = sha1sum -c
|
||||
|
||||
COWPATCH = $(CURDIR)/cowpatch.sh
|
||||
ifneq ($(NATIVE),)
|
||||
HOST := $(TARGET)
|
||||
endif
|
||||
|
||||
HOST = $(if $(NATIVE),$(TARGET))
|
||||
BUILD_DIR = build/$(if $(HOST),$(HOST),local)/$(TARGET)
|
||||
OUTPUT = $(CURDIR)/output$(if $(HOST),-$(HOST))
|
||||
ifneq ($(HOST),)
|
||||
BUILD_DIR = build/$(HOST)/$(TARGET)
|
||||
OUTPUT = $(CURDIR)/output-$(HOST)
|
||||
else
|
||||
BUILD_DIR = build/local/$(TARGET)
|
||||
OUTPUT = $(CURDIR)/output
|
||||
endif
|
||||
|
||||
REL_TOP = ../../..
|
||||
|
||||
@ -65,20 +69,18 @@ $(patsubst hashes/%.sha1,$(SOURCES)/%,$(wildcard hashes/isl*)): SITE = $(ISL_SIT
|
||||
$(patsubst hashes/%.sha1,$(SOURCES)/%,$(wildcard hashes/binutils*)): SITE = $(BINUTILS_SITE)
|
||||
$(patsubst hashes/%.sha1,$(SOURCES)/%,$(wildcard hashes/gcc*)): SITE = $(GCC_SITE)/$(basename $(basename $(notdir $@)))
|
||||
$(patsubst hashes/%.sha1,$(SOURCES)/%,$(wildcard hashes/musl*)): SITE = $(MUSL_SITE)
|
||||
$(patsubst hashes/%.sha1,$(SOURCES)/%,$(wildcard hashes/linux-5*)): SITE = $(LINUX_SITE)/v5.x
|
||||
$(patsubst hashes/%.sha1,$(SOURCES)/%,$(wildcard hashes/linux-4*)): SITE = $(LINUX_SITE)/v4.x
|
||||
$(patsubst hashes/%.sha1,$(SOURCES)/%,$(wildcard hashes/linux-3*)): SITE = $(LINUX_SITE)/v3.x
|
||||
$(patsubst hashes/%.sha1,$(SOURCES)/%,$(wildcard hashes/linux-2.6*)): SITE = $(LINUX_SITE)/v2.6
|
||||
$(patsubst hashes/%.sha1,$(SOURCES)/%,$(wildcard hashes/linux-headers-*)): SITE = $(LINUX_HEADERS_SITE)
|
||||
|
||||
$(SOURCES):
|
||||
mkdir -p $@
|
||||
|
||||
$(SOURCES)/config.sub: | $(SOURCES)
|
||||
mkdir -p $@.tmp
|
||||
cd $@.tmp && $(DL_CMD) $(notdir $@) "https://git.savannah.gnu.org/gitweb/?p=config.git;a=blob_plain;f=config.sub;hb=$(CONFIG_SUB_REV)"
|
||||
cd $@.tmp && $(DL_CMD) $(notdir $@) "http://git.savannah.gnu.org/gitweb/?p=config.git;a=blob_plain;f=config.sub;hb=$(CONFIG_SUB_REV)"
|
||||
cd $@.tmp && touch $(notdir $@)
|
||||
cd $@.tmp && $(SHA1_CMD) $(CURDIR)/hashes/$(notdir $@).$(CONFIG_SUB_REV).sha1
|
||||
cd $@.tmp && sha1sum -c $(CURDIR)/hashes/$(notdir $@).$(CONFIG_SUB_REV).sha1
|
||||
mv $@.tmp/$(notdir $@) $@
|
||||
rm -rf $@.tmp
|
||||
|
||||
@ -86,7 +88,7 @@ $(SOURCES)/%: hashes/%.sha1 | $(SOURCES)
|
||||
mkdir -p $@.tmp
|
||||
cd $@.tmp && $(DL_CMD) $(notdir $@) $(SITE)/$(notdir $@)
|
||||
cd $@.tmp && touch $(notdir $@)
|
||||
cd $@.tmp && $(SHA1_CMD) $(CURDIR)/hashes/$(notdir $@).sha1
|
||||
cd $@.tmp && sha1sum -c $(CURDIR)/hashes/$(notdir $@).sha1
|
||||
mv $@.tmp/$(notdir $@) $@
|
||||
rm -rf $@.tmp
|
||||
|
||||
@ -101,50 +103,39 @@ musl-git-%:
|
||||
cd $@.tmp && git fsck
|
||||
mv $@.tmp $@
|
||||
|
||||
%.orig: $(SOURCES)/%.tar.gz
|
||||
case "$@" in */*) exit 1 ;; esac
|
||||
%: $(SOURCES)/%.tar.gz | $(SOURCES)/config.sub
|
||||
rm -rf $@.tmp
|
||||
mkdir $@.tmp
|
||||
( cd $@.tmp && tar zxvf - ) < $<
|
||||
test ! -d patches/$@ || cat patches/$@/* | ( cd $@.tmp/$@ && patch -p1 )
|
||||
test ! -f $@.tmp/$@/config.sub || cp -f $(SOURCES)/config.sub $@.tmp/$@
|
||||
rm -rf $@
|
||||
touch $@.tmp/$(patsubst %.orig,%,$@)
|
||||
mv $@.tmp/$(patsubst %.orig,%,$@) $@
|
||||
touch $@.tmp/$@
|
||||
mv $@.tmp/$@ $@
|
||||
rm -rf $@.tmp
|
||||
|
||||
%.orig: $(SOURCES)/%.tar.bz2
|
||||
case "$@" in */*) exit 1 ;; esac
|
||||
%: $(SOURCES)/%.tar.bz2 | $(SOURCES)/config.sub
|
||||
rm -rf $@.tmp
|
||||
mkdir $@.tmp
|
||||
( cd $@.tmp && tar jxvf - ) < $<
|
||||
test ! -d patches/$@ || cat patches/$@/* | ( cd $@.tmp/$@ && patch -p1 )
|
||||
test ! -f $@.tmp/$@/config.sub || cp -f $(SOURCES)/config.sub $@.tmp/$@
|
||||
rm -rf $@
|
||||
touch $@.tmp/$(patsubst %.orig,%,$@)
|
||||
mv $@.tmp/$(patsubst %.orig,%,$@) $@
|
||||
touch $@.tmp/$@
|
||||
mv $@.tmp/$@ $@
|
||||
rm -rf $@.tmp
|
||||
|
||||
%.orig: $(SOURCES)/%.tar.xz
|
||||
case "$@" in */*) exit 1 ;; esac
|
||||
%: $(SOURCES)/%.tar.xz | $(SOURCES)/config.sub
|
||||
rm -rf $@.tmp
|
||||
mkdir $@.tmp
|
||||
( cd $@.tmp && tar Jxvf - ) < $<
|
||||
test ! -d patches/$@ || cat patches/$@/* | ( cd $@.tmp/$@ && patch -p1 )
|
||||
test ! -f $@.tmp/$@/config.sub || cp -f $(SOURCES)/config.sub $@.tmp/$@
|
||||
rm -rf $@
|
||||
touch $@.tmp/$(patsubst %.orig,%,$@)
|
||||
mv $@.tmp/$(patsubst %.orig,%,$@) $@
|
||||
touch $@.tmp/$@
|
||||
mv $@.tmp/$@ $@
|
||||
rm -rf $@.tmp
|
||||
|
||||
%: %.orig | $(SOURCES)/config.sub
|
||||
case "$@" in */*) exit 1 ;; esac
|
||||
rm -rf $@.tmp
|
||||
mkdir $@.tmp
|
||||
( cd $@.tmp && $(COWPATCH) -I ../$< )
|
||||
test ! -d patches/$@ || cat patches/$@/* | ( cd $@.tmp && $(COWPATCH) -p1 )
|
||||
if test -f $</configfsf.sub ; then cs=configfsf.sub ; elif test -f $</config.sub ; then cs=config.sub ; else exit 0 ; fi ; rm -f $@.tmp/$$cs && cp -f $(SOURCES)/config.sub $@.tmp/$$cs && chmod +x $@.tmp/$$cs
|
||||
rm -rf $@
|
||||
mv $@.tmp $@
|
||||
|
||||
|
||||
# Add deps for all patched source dirs on their patchsets
|
||||
$(foreach dir,$(notdir $(basename $(basename $(basename $(wildcard hashes/*))))),$(eval $(dir): $$(wildcard patches/$(dir) patches/$(dir)/*)))
|
||||
|
||||
extract_all: | $(SRC_DIRS)
|
||||
|
||||
|
||||
@ -185,5 +176,3 @@ install: | $(SRC_DIRS) $(BUILD_DIR) $(BUILD_DIR)/Makefile $(BUILD_DIR)/config.ma
|
||||
cd $(BUILD_DIR) && $(MAKE) OUTPUT=$(OUTPUT) $@
|
||||
|
||||
endif
|
||||
|
||||
.SECONDARY:
|
||||
|
||||
24
README.md
24
README.md
@ -56,7 +56,6 @@ believed to work:
|
||||
- `mips64[el]-linux-musl[n32][sf]`
|
||||
- `powerpc-linux-musl[sf]`
|
||||
- `powerpc64[le]-linux-musl`
|
||||
- `riscv64-linux-musl`
|
||||
- `s390x-linux-musl`
|
||||
- `sh*[eb]-linux-musl[fdpic][sf]`
|
||||
- `x86_64-linux-musl[x32]`
|
||||
@ -145,26 +144,3 @@ build systems, if desired.
|
||||
Some functionality (SH/FDPIC, and support for J2 specific features) is
|
||||
presently only available with gcc 5.2.0 and later, and binutils 2.25.1
|
||||
and later.
|
||||
|
||||
License
|
||||
-------
|
||||
|
||||
The musl-cross-make build tools and documentation are licensed under
|
||||
the MIT/Expat license as found in the `LICENSE` file.
|
||||
|
||||
Note that this license does not cover the patches (`patches/`) or
|
||||
resulting binary artifacts.
|
||||
|
||||
Each patch (`patches/`) is distributed under the terms of the license
|
||||
of the upstream project to which it is applied.
|
||||
|
||||
Similarly, any resulting binary artifacts produced using this build
|
||||
tooling retain the original licensing from the upstream projects. The
|
||||
authors of musl-cross-make do not make any additional copyright claims
|
||||
to these artifacts.
|
||||
|
||||
### Contribution
|
||||
|
||||
Unless you explicitly state otherwise, any contribution submitted for
|
||||
inclusion in musl-cross-make by you shall be licensed as above without
|
||||
any additional terms or conditions.
|
||||
|
||||
@ -46,13 +46,6 @@
|
||||
# DL_CMD = wget -c -O
|
||||
# DL_CMD = curl -C - -L -o
|
||||
|
||||
# Check sha-1 hashes of downloaded source archives. On gnu systems this is
|
||||
# usually done with sha1sum.
|
||||
|
||||
# SHA1_CMD = sha1sum -c
|
||||
# SHA1_CMD = sha1 -c
|
||||
# SHA1_CMD = shasum -a 1 -c
|
||||
|
||||
# Something like the following can be used to produce a static-linked
|
||||
# toolchain that's deployable to any system with matching arch, using
|
||||
# an existing musl-targeted cross compiler. This only works if the
|
||||
@ -65,20 +58,12 @@
|
||||
|
||||
# COMMON_CONFIG += CFLAGS="-g0 -Os" CXXFLAGS="-g0 -Os" LDFLAGS="-s"
|
||||
|
||||
# Options you can add for faster/simpler build at the expense of features:
|
||||
# Recommended options for faster/simpler build:
|
||||
|
||||
# COMMON_CONFIG += --disable-nls
|
||||
# GCC_CONFIG += --disable-libquadmath --disable-decimal-float
|
||||
# GCC_CONFIG += --disable-libitm
|
||||
# GCC_CONFIG += --disable-fixed-point
|
||||
# GCC_CONFIG += --disable-lto
|
||||
|
||||
# By default C and C++ are the only languages enabled, and these are
|
||||
# the only ones tested and known to be supported. You can uncomment the
|
||||
# following and add other languages if you want to try getting them to
|
||||
# work too.
|
||||
|
||||
# GCC_CONFIG += --enable-languages=c,c++
|
||||
# GCC_CONFIG += --disable-libquadmath --disable-decimal-float
|
||||
# GCC_CONFIG += --disable-multilib
|
||||
|
||||
# You can keep the local build path out of your toolchain binaries and
|
||||
# target libraries with the following, but then gdb needs to be told
|
||||
|
||||
103
cowpatch.sh
103
cowpatch.sh
@ -1,103 +0,0 @@
|
||||
#!/bin/sh
|
||||
#
|
||||
# cowpatch.sh, by Rich Felker
|
||||
#
|
||||
# Permission to use, copy, modify, and/or distribute this software for
|
||||
# any purpose with or without fee is hereby granted.
|
||||
#
|
||||
# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
|
||||
# WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
|
||||
# WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
|
||||
# AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
|
||||
# DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA
|
||||
# OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
|
||||
# TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
# PERFORMANCE OF THIS SOFTWARE.
|
||||
#
|
||||
# Take the above disclaimer seriously! This is an experimental tool
|
||||
# still and does not yet take precautions against malformed/malicious
|
||||
# patch files like patch(1) does. It may act out-of-tree and clobber
|
||||
# stuff you didn't intend for it to clobber.
|
||||
#
|
||||
|
||||
set -e
|
||||
|
||||
echo () { printf "%s\n" "$*" ; }
|
||||
|
||||
cow () {
|
||||
test -h "$1" || return 0
|
||||
if test -d "$1" ; then
|
||||
case "$1" in
|
||||
*/*) set -- "${1%/*}/" "${1##*/}" ;;
|
||||
*) set -- "" "$1" ;;
|
||||
esac
|
||||
mkdir "$1$2.tmp.$$"
|
||||
mv "$1$2" "$1.$2.orig"
|
||||
mv "$1$2.tmp.$$" "$1$2"
|
||||
( cd "$1$2" && ln -s ../".$2.orig"/* . )
|
||||
else
|
||||
cp "$1" "$1.tmp.$$"
|
||||
mv "$1.tmp.$$" "$1"
|
||||
fi
|
||||
}
|
||||
|
||||
cowp () {
|
||||
while test "$1" ; do
|
||||
case "$1" in
|
||||
*/*) set -- "${1#*/}" "$2${2:+/}${1%%/*}" ;;
|
||||
*) set -- "" "$2${2:+/}$1" ;;
|
||||
esac
|
||||
cow "$2"
|
||||
done
|
||||
}
|
||||
|
||||
cowpatch () {
|
||||
|
||||
plev=0
|
||||
OPTIND=1
|
||||
while getopts ":p:i:RNE" opt ; do
|
||||
test "$opt" = p && plev="$OPTARG"
|
||||
done
|
||||
|
||||
while IFS= read -r l ; do
|
||||
case "$l" in
|
||||
+++*)
|
||||
IFS=" " read -r junk pfile junk <<EOF
|
||||
$l
|
||||
EOF
|
||||
i=0; while test "$i" -lt "$plev" ; do pfile=${pfile#*/}; i=$((i+1)) ; done
|
||||
cowp "$pfile"
|
||||
echo "$l"
|
||||
;;
|
||||
@@*)
|
||||
echo "$l"
|
||||
IFS=" " read -r junk i j junk <<EOF
|
||||
$l
|
||||
EOF
|
||||
case "$i" in *,*) i=${i#*,} ;; *) i=1 ;; esac
|
||||
case "$j" in *,*) j=${j#*,} ;; *) j=1 ;; esac
|
||||
while test $i -gt 0 || test $j -gt 0 ; do
|
||||
IFS= read -r l
|
||||
echo "$l"
|
||||
case "$l" in
|
||||
+*) j=$((j-1)) ;;
|
||||
-*) i=$((i-1)) ;;
|
||||
*) i=$((i-1)) ; j=$((j-1)) ;;
|
||||
esac
|
||||
done ;;
|
||||
*) echo "$l" ;;
|
||||
esac
|
||||
done
|
||||
|
||||
}
|
||||
|
||||
gotcmd=0
|
||||
while getopts ":p:i:RNEI:S:" opt ; do
|
||||
case "$opt" in
|
||||
I) find "$OPTARG" -path "$OPTARG/*" -prune -exec sh -c 'ln -sf "$@" .' sh {} + ; gotcmd=1 ;;
|
||||
S) cowp "$OPTARG" ; gotcmd=1 ;;
|
||||
esac
|
||||
done
|
||||
test "$gotcmd" -eq 0 || exit 0
|
||||
|
||||
cowpatch "$@" | patch "$@"
|
||||
@ -1 +0,0 @@
|
||||
cd45a512af1c8a508976c1beb4f5825b3bb89f4d binutils-2.32.tar.xz
|
||||
@ -1 +0,0 @@
|
||||
06598868f5fa8efc98427dcb790d42c664f1a1a4 binutils-2.33.1.tar.xz
|
||||
@ -1 +0,0 @@
|
||||
fb51ed1660c065898c75951fb38e1ebad7d49feb gcc-10.3.0.tar.xz
|
||||
@ -1 +0,0 @@
|
||||
f902ccacecf8949978d6261e9f1d034cff73ffdb gcc-11.2.0.tar.xz
|
||||
@ -1 +0,0 @@
|
||||
a65b357c583e4ad8f95111d442ae51002c990f29 gcc-11.5.0.tar.xz
|
||||
@ -1 +0,0 @@
|
||||
b373d4ac29bb06ca64d288621906cbf63ab5a1f5 gcc-12.4.0.tar.xz
|
||||
@ -1 +0,0 @@
|
||||
6501872415823c95d48be28853ce3ebd6c1040c4 gcc-13.3.0.tar.xz
|
||||
@ -1 +0,0 @@
|
||||
d91ecc3d20ce6298bd95f9b09cc51dc6d3c73ae3 gcc-14.2.0.tar.xz
|
||||
1
hashes/gcc-5.2.0.tar.bz2.sha1
Normal file
1
hashes/gcc-5.2.0.tar.bz2.sha1
Normal file
@ -0,0 +1 @@
|
||||
fe3f5390949d47054b613edc36c557eb1d51c18e gcc-5.2.0.tar.bz2
|
||||
1
hashes/gcc-6.2.0.tar.bz2.sha1
Normal file
1
hashes/gcc-6.2.0.tar.bz2.sha1
Normal file
@ -0,0 +1 @@
|
||||
583e29c7fe69d9a1031a89752c2551ab5aeacb91 gcc-6.2.0.tar.bz2
|
||||
1
hashes/gcc-6.3.0.tar.bz2.sha1
Normal file
1
hashes/gcc-6.3.0.tar.bz2.sha1
Normal file
@ -0,0 +1 @@
|
||||
928ab552666ee08eed645ff20ceb49d139205dea gcc-6.3.0.tar.bz2
|
||||
@ -1 +0,0 @@
|
||||
368b3f5d294b1a8727b372ac0a77703d8b41968a gcc-6.5.0.tar.xz
|
||||
1
hashes/gcc-7.2.0.tar.xz.sha1
Normal file
1
hashes/gcc-7.2.0.tar.xz.sha1
Normal file
@ -0,0 +1 @@
|
||||
08a88199ed94fdf4940d118ba3c07028245cd5b7 gcc-7.2.0.tar.xz
|
||||
@ -1 +0,0 @@
|
||||
9153345fa05adfa58b4759ccb9f37d09662dd101 gcc-7.5.0.tar.xz
|
||||
@ -1 +0,0 @@
|
||||
2e93f85672f57023d45c20fef9572b72f8a3e7f1 gcc-8.5.0.tar.xz
|
||||
@ -1 +0,0 @@
|
||||
bf6d6480fb32e5a28dac849449f533a84d4e6547 gcc-9.4.0.tar.xz
|
||||
@ -1 +0,0 @@
|
||||
366ded6a44cd108ba6b3f5b9a252eab3f3a95cdf gmp-6.1.2.tar.bz2
|
||||
@ -1 +0,0 @@
|
||||
33e366d59d32330432b5c7f2d0c2fb6664eff224 isl-0.21.tar.bz2
|
||||
1
hashes/linux-2.6.35.tar.xz.sha1
Normal file
1
hashes/linux-2.6.35.tar.xz.sha1
Normal file
@ -0,0 +1 @@
|
||||
4fc189bd50b734c08985c61bd16cc91cd3fc4e04 linux-2.6.35.tar.xz
|
||||
@ -1 +0,0 @@
|
||||
2663224361a984c8a62b9cf9fc8c82c0a75f9f3f linux-4.19.90.tar.xz
|
||||
1
hashes/linux-4.4.10.tar.xz.sha1
Normal file
1
hashes/linux-4.4.10.tar.xz.sha1
Normal file
@ -0,0 +1 @@
|
||||
03b45399a93ae8bc18f1f27ad72f3e98c6bba5c8 linux-4.4.10.tar.xz
|
||||
@ -1 +0,0 @@
|
||||
6faa91e98a8cd36901cbc3c29ca67e519de9e33b linux-5.8.5.tar.xz
|
||||
@ -1 +0,0 @@
|
||||
b35ef708c60381a566f6310a5abcb7a8f149db0d linux-headers-4.19.88-1.tar.xz
|
||||
@ -1 +0,0 @@
|
||||
9794861f8ec91398d07694fe8a5651f9a466b967 linux-headers-4.19.88-2.tar.xz
|
||||
@ -1 +0,0 @@
|
||||
de12b9c8ae2de9e85056a36be9f0fcc0a1e4abe9 linux-headers-4.19.88.tar.xz
|
||||
@ -1 +0,0 @@
|
||||
b019d9e1d27ec5fb99497159d43a3164995de2d0 mpc-1.1.0.tar.gz
|
||||
@ -1 +0,0 @@
|
||||
d6a313a3b1ceb9ff3be71cd18e45468837b7fd53 mpfr-4.0.2.tar.bz2
|
||||
@ -1 +0,0 @@
|
||||
0055c906d2cea2f5f2406f4d922b7d189d406c66 musl-1.1.19.tar.gz
|
||||
@ -1 +0,0 @@
|
||||
469b3af68a49188c8db4cc94077719152c0d41f1 musl-1.1.20.tar.gz
|
||||
@ -1 +0,0 @@
|
||||
de45b38c1efcfe9a4847e7224345a8df2275e462 musl-1.1.21.tar.gz
|
||||
@ -1 +0,0 @@
|
||||
657f359cb054492c56b378c4d8cec5a12bf93061 musl-1.1.22.tar.gz
|
||||
@ -1 +0,0 @@
|
||||
98f3991d67e0e11dd091eb65890285d8417c7d05 musl-1.1.23.tar.gz
|
||||
@ -1 +0,0 @@
|
||||
b0b5ddf6b65355ac02e2f11c3d262ac5dcf0bab5 musl-1.1.24.tar.gz
|
||||
@ -1 +0,0 @@
|
||||
140038a5376ca3a4e69168ed6c3879d1477b20d1 musl-1.2.0.tar.gz
|
||||
@ -1 +0,0 @@
|
||||
031062cf1a3c3e81e3dbae5ad2edbeff02ca198f musl-1.2.1.tar.gz
|
||||
@ -1 +0,0 @@
|
||||
e7ba5f0a5f89c13843b955e916f1d9a9d4b6ab9a musl-1.2.2.tar.gz
|
||||
@ -1 +0,0 @@
|
||||
3b6b673196c2dc96b24c5d6028c5fa922457dd26 musl-1.2.3.tar.gz
|
||||
@ -1 +0,0 @@
|
||||
78eb982244b857dbacb2ead25cc0f631ce44204d musl-1.2.4.tar.gz
|
||||
@ -1 +0,0 @@
|
||||
36210d3423172a40ddcf83c762207c5f760b60a6 musl-1.2.5.tar.gz
|
||||
@ -10,7 +10,7 @@ COMMON_CONFIG =
|
||||
GCC_CONFIG =
|
||||
TOOLCHAIN_CONFIG =
|
||||
|
||||
XGCC_DIR = ../obj_gcc/gcc
|
||||
XGCC_DIR = ../obj_toolchain/gcc
|
||||
XGCC = $(XGCC_DIR)/xgcc -B $(XGCC_DIR)
|
||||
|
||||
-include config.mak
|
||||
@ -35,10 +35,6 @@ GCC_CONFIG_FOR_TARGET += --with-abi=64
|
||||
endif
|
||||
endif
|
||||
|
||||
ifneq ($(findstring s390x,$(TARGET)),)
|
||||
GCC_CONFIG_FOR_TARGET += --with-long-double-128
|
||||
endif
|
||||
|
||||
ifneq ($(filter %sf,$(TARGET)),)
|
||||
GCC_CONFIG_FOR_TARGET += --with-float=soft
|
||||
endif
|
||||
@ -47,29 +43,15 @@ ifneq ($(filter %hf,$(TARGET)),)
|
||||
GCC_CONFIG_FOR_TARGET += --with-float=hard
|
||||
endif
|
||||
|
||||
ifneq ($(LIBTOOL),)
|
||||
LIBTOOL_ARG = LIBTOOL=$(LIBTOOL)
|
||||
endif
|
||||
|
||||
MAKE += MULTILIB_OSDIRNAMES=
|
||||
MAKE += INFO_DEPS= infodir=
|
||||
MAKE += ac_cv_prog_lex_root=lex.yy
|
||||
MAKE += ac_cv_prog_lex_root=lex.yy.c
|
||||
MAKE += MAKEINFO=false
|
||||
|
||||
FULL_BINUTILS_CONFIG = \
|
||||
--disable-separate-code \
|
||||
$(COMMON_CONFIG) $(BINUTILS_CONFIG) $(TOOLCHAIN_CONFIG) \
|
||||
--disable-werror \
|
||||
--target=$(TARGET) --prefix= \
|
||||
--libdir=/lib --disable-multilib \
|
||||
--with-sysroot=$(SYSROOT) \
|
||||
--enable-deterministic-archives
|
||||
|
||||
FULL_GCC_CONFIG = --enable-languages=c,c++ \
|
||||
FULL_TOOLCHAIN_CONFIG = --enable-languages=c,c++ \
|
||||
$(GCC_CONFIG_FOR_TARGET) \
|
||||
$(COMMON_CONFIG) $(GCC_CONFIG) $(TOOLCHAIN_CONFIG) \
|
||||
--disable-bootstrap \
|
||||
--disable-assembly \
|
||||
--disable-werror \
|
||||
--target=$(TARGET) --prefix= \
|
||||
--libdir=/lib --disable-multilib \
|
||||
@ -78,8 +60,8 @@ FULL_GCC_CONFIG = --enable-languages=c,c++ \
|
||||
--disable-libmudflap --disable-libsanitizer \
|
||||
--disable-gnu-indirect-function \
|
||||
--disable-libmpx \
|
||||
--enable-initfini-array \
|
||||
--enable-libstdcxx-time=rt
|
||||
--enable-deterministic-archives \
|
||||
--enable-libstdcxx-time
|
||||
|
||||
FULL_MUSL_CONFIG = $(MUSL_CONFIG) \
|
||||
--prefix= --host=$(TARGET)
|
||||
@ -88,38 +70,18 @@ ifneq ($(NATIVE),)
|
||||
HOST:=$(TARGET)
|
||||
endif
|
||||
|
||||
ifeq ($(BUILD),)
|
||||
GUESS = $(shell cd $(GCC_SRCDIR) && ./config.guess)
|
||||
TARGET_CANON = $(shell cd $(GCC_SRCDIR) && ./config.sub $(TARGET))
|
||||
BUILD = $(GUESS)$(if $(subst $(TARGET_CANON),,$(GUESS)),,xx)
|
||||
endif
|
||||
|
||||
ifeq ($(HOST),)
|
||||
SYSROOT = /$(TARGET)
|
||||
FULL_BINUTILS_CONFIG += --build=$(BUILD) --host=$(BUILD)
|
||||
FULL_GCC_CONFIG += --with-build-sysroot=$(CURDIR)/obj_sysroot \
|
||||
AR_FOR_TARGET=$(PWD)/obj_binutils/binutils/ar \
|
||||
AS_FOR_TARGET=$(PWD)/obj_binutils/gas/as-new \
|
||||
LD_FOR_TARGET=$(PWD)/obj_binutils/ld/ld-new \
|
||||
NM_FOR_TARGET=$(PWD)/obj_binutils/binutils/nm-new \
|
||||
OBJCOPY_FOR_TARGET=$(PWD)/obj_binutils/binutils/objcopy \
|
||||
OBJDUMP_FOR_TARGET=$(PWD)/obj_binutils/binutils/objdump \
|
||||
RANLIB_FOR_TARGET=$(PWD)/obj_binutils/binutils/ranlib \
|
||||
READELF_FOR_TARGET=$(PWD)/obj_binutils/binutils/readelf \
|
||||
STRIP_FOR_TARGET=$(PWD)/obj_binutils/binutils/strip-new \
|
||||
--build=$(BUILD) --host=$(BUILD) \
|
||||
# end
|
||||
FULL_MUSL_CONFIG += CC="$(XGCC)" LIBCC="../obj_gcc/$(TARGET)/libgcc/libgcc.a"
|
||||
MUSL_VARS = AR=../obj_binutils/binutils/ar RANLIB=../obj_binutils/binutils/ranlib
|
||||
obj_musl/.lc_configured: | obj_gcc/gcc/.lc_built
|
||||
obj_musl/.lc_built: | obj_gcc/$(TARGET)/libgcc/libgcc.a
|
||||
obj_gcc/gcc/.lc_built: | obj_sysroot/usr obj_sysroot/lib32 obj_sysroot/lib64 obj_sysroot/include
|
||||
obj_gcc/.lc_built: | obj_sysroot/.lc_libs obj_sysroot/.lc_headers
|
||||
obj_gcc/.lc_configured: obj_binutils/.lc_built
|
||||
FULL_TOOLCHAIN_CONFIG += --with-build-sysroot=$(CURDIR)/obj_sysroot
|
||||
FULL_MUSL_CONFIG += CC="$(XGCC)" LIBCC="../obj_toolchain/$(TARGET)/libgcc/libgcc.a"
|
||||
MUSL_VARS = AR=../obj_toolchain/binutils/ar RANLIB=../obj_toolchain/binutils/ranlib
|
||||
obj_musl/.lc_configured: | obj_toolchain/gcc/.lc_built
|
||||
obj_musl/.lc_built: | obj_toolchain/$(TARGET)/libgcc/libgcc.a
|
||||
obj_toolchain/gcc/.lc_built: | obj_sysroot/usr obj_sysroot/lib32 obj_sysroot/lib64 obj_sysroot/include
|
||||
obj_toolchain/.lc_built: | obj_sysroot/.lc_libs obj_sysroot/.lc_headers
|
||||
else
|
||||
SYSROOT = /
|
||||
FULL_BINUTILS_CONFIG += --build=$(BUILD) --host=$(HOST)
|
||||
FULL_GCC_CONFIG += --build=$(BUILD) --host=$(HOST)
|
||||
FULL_TOOLCHAIN_CONFIG += --host=$(HOST)
|
||||
MUSL_VARS =
|
||||
endif
|
||||
|
||||
@ -133,59 +95,54 @@ install: all
|
||||
|
||||
else
|
||||
|
||||
all: musl gcc binutils
|
||||
all: musl toolchain
|
||||
|
||||
install: install-musl install-gcc install-binutils
|
||||
install: install-musl install-toolchain
|
||||
|
||||
musl: obj_musl/.lc_built
|
||||
|
||||
toolchain: gcc binutils
|
||||
|
||||
install-toolchain: install-gcc install-binutils
|
||||
|
||||
gcc: obj_gcc/.lc_built
|
||||
|
||||
binutils: obj_binutils/.lc_built
|
||||
toolchain: obj_toolchain/.lc_built
|
||||
|
||||
.PHONY: all musl toolchain install-musl install-toolchain clean
|
||||
|
||||
src_binutils: | $(BINUTILS_SRCDIR)
|
||||
ln -sf $(BINUTILS_SRCDIR) $@
|
||||
|
||||
src_gcc_base: | $(GCC_SRCDIR)
|
||||
src_gcc: | $(GCC_SRCDIR)
|
||||
ln -sf $(GCC_SRCDIR) $@
|
||||
|
||||
src_musl: | $(MUSL_SRCDIR)
|
||||
ln -sf $(MUSL_SRCDIR) $@
|
||||
|
||||
ifneq ($(GMP_SRCDIR),)
|
||||
src_gcc: src_gmp
|
||||
src_toolchain: src_gmp
|
||||
src_gmp: | $(GMP_SRCDIR)
|
||||
ln -sf "$(GMP_SRCDIR)" $@
|
||||
endif
|
||||
|
||||
ifneq ($(MPC_SRCDIR),)
|
||||
src_gcc: src_mpc
|
||||
src_toolchain: src_mpc
|
||||
src_mpc: | $(MPC_SRCDIR)
|
||||
ln -sf "$(MPC_SRCDIR)" $@
|
||||
endif
|
||||
|
||||
ifneq ($(MPFR_SRCDIR),)
|
||||
src_gcc: src_mpfr
|
||||
src_toolchain: src_mpfr
|
||||
src_mpfr: | $(MPFR_SRCDIR)
|
||||
ln -sf "$(MPFR_SRCDIR)" $@
|
||||
endif
|
||||
|
||||
ifneq ($(ISL_SRCDIR),)
|
||||
src_gcc: src_isl
|
||||
src_toolchain: src_isl
|
||||
src_isl: | $(ISL_SRCDIR)
|
||||
ln -sf "$(ISL_SRCDIR)" $@
|
||||
endif
|
||||
|
||||
src_gcc: src_gcc_base
|
||||
src_toolchain: src_binutils src_gcc
|
||||
rm -rf $@ $@.tmp
|
||||
mkdir $@.tmp
|
||||
cd $@.tmp && ln -sf ../src_gcc_base/* .
|
||||
cd $@.tmp && ln -sf ../src_binutils/* .
|
||||
cd $@.tmp && ln -sf ../src_gcc/* .
|
||||
$(if $(GMP_SRCDIR),cd $@.tmp && ln -sf ../src_gmp gmp)
|
||||
$(if $(MPC_SRCDIR),cd $@.tmp && ln -sf ../src_mpc mpc)
|
||||
$(if $(MPFR_SRCDIR),cd $@.tmp && ln -sf ../src_mpfr mpfr)
|
||||
@ -207,20 +164,12 @@ obj_sysroot/lib32: | obj_sysroot
|
||||
obj_sysroot/lib64: | obj_sysroot
|
||||
ln -sf lib $@
|
||||
|
||||
obj_binutils/.lc_configured: | obj_binutils src_binutils
|
||||
cd obj_binutils && ../src_binutils/configure $(FULL_BINUTILS_CONFIG)
|
||||
obj_toolchain/.lc_configured: | obj_toolchain src_toolchain
|
||||
cd obj_toolchain && ../src_toolchain/configure $(FULL_TOOLCHAIN_CONFIG)
|
||||
touch $@
|
||||
|
||||
obj_binutils/.lc_built: | obj_binutils/.lc_configured
|
||||
cd obj_binutils && $(MAKE) MAKE="$(MAKE) $(LIBTOOL_ARG)" all
|
||||
touch $@
|
||||
|
||||
obj_gcc/.lc_configured: | obj_gcc src_gcc
|
||||
cd obj_gcc && ../src_gcc/configure $(FULL_GCC_CONFIG)
|
||||
touch $@
|
||||
|
||||
obj_gcc/gcc/.lc_built: | obj_gcc/.lc_configured
|
||||
cd obj_gcc && $(MAKE) MAKE="$(MAKE) $(LIBTOOL_ARG)" all-gcc
|
||||
obj_toolchain/gcc/.lc_built: | obj_toolchain/.lc_configured
|
||||
cd obj_toolchain && $(MAKE) MAKE="$(MAKE)" all-gcc
|
||||
touch $@
|
||||
|
||||
obj_musl/.lc_configured: | obj_musl src_musl
|
||||
@ -231,8 +180,8 @@ obj_sysroot/.lc_headers: | obj_musl/.lc_configured obj_sysroot
|
||||
cd obj_musl && $(MAKE) DESTDIR=$(CURDIR)/obj_sysroot install-headers
|
||||
touch $@
|
||||
|
||||
obj_gcc/$(TARGET)/libgcc/libgcc.a: | obj_sysroot/.lc_headers
|
||||
cd obj_gcc && $(MAKE) MAKE="$(MAKE) enable_shared=no $(LIBTOOL_ARG)" all-target-libgcc
|
||||
obj_toolchain/$(TARGET)/libgcc/libgcc.a: | obj_sysroot/.lc_headers
|
||||
cd obj_toolchain && $(MAKE) MAKE="$(MAKE) enable_shared=no" all-target-libgcc
|
||||
|
||||
obj_musl/.lc_built: | obj_musl/.lc_configured
|
||||
cd obj_musl && $(MAKE) $(MUSL_VARS)
|
||||
@ -242,18 +191,15 @@ obj_sysroot/.lc_libs: | obj_musl/.lc_built
|
||||
cd obj_musl && $(MAKE) $(MUSL_VARS) DESTDIR=$(CURDIR)/obj_sysroot install
|
||||
touch $@
|
||||
|
||||
obj_gcc/.lc_built: | obj_gcc/.lc_configured obj_gcc/gcc/.lc_built
|
||||
cd obj_gcc && $(MAKE) MAKE="$(MAKE) $(LIBTOOL_ARG)"
|
||||
obj_toolchain/.lc_built: | obj_toolchain/.lc_configured obj_toolchain/gcc/.lc_built
|
||||
cd obj_toolchain && $(MAKE) MAKE="$(MAKE)"
|
||||
touch $@
|
||||
|
||||
install-musl: | obj_musl/.lc_built
|
||||
cd obj_musl && $(MAKE) $(MUSL_VARS) DESTDIR=$(DESTDIR)$(OUTPUT)$(SYSROOT) install
|
||||
|
||||
install-binutils: | obj_binutils/.lc_built
|
||||
cd obj_binutils && $(MAKE) MAKE="$(MAKE) $(LIBTOOL_ARG)" DESTDIR=$(DESTDIR)$(OUTPUT) install
|
||||
|
||||
install-gcc: | obj_gcc/.lc_built
|
||||
cd obj_gcc && $(MAKE) MAKE="$(MAKE) $(LIBTOOL_ARG)" DESTDIR=$(DESTDIR)$(OUTPUT) install
|
||||
install-toolchain: | obj_toolchain/.lc_built
|
||||
cd obj_toolchain && $(MAKE) MAKE="$(MAKE)" DESTDIR=$(DESTDIR)$(OUTPUT) install
|
||||
ln -sf $(TARGET)-gcc $(DESTDIR)$(OUTPUT)/bin/$(TARGET)-cc
|
||||
|
||||
ifneq ($(LINUX_SRCDIR),)
|
||||
|
||||
@ -1,21 +0,0 @@
|
||||
diff -ur binutils-2.25.1.orig/bfd/elfxx-mips.c binutils-2.25.1/bfd/elfxx-mips.c
|
||||
--- binutils-2.25.1.orig/bfd/elfxx-mips.c 2018-01-31 11:26:12.000000000 -0500
|
||||
+++ binutils-2.25.1/bfd/elfxx-mips.c 2018-01-31 12:16:00.179841734 -0500
|
||||
@@ -3228,7 +3228,7 @@
|
||||
&& (!info->shared || !SYMBOL_REFERENCES_LOCAL (info, h)))
|
||||
indx = h->dynindx;
|
||||
|
||||
- if ((info->shared || indx != 0)
|
||||
+ if ((!info->executable || indx != 0)
|
||||
&& (h == NULL
|
||||
|| ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
|
||||
|| h->root.type != bfd_link_hash_undefweak))
|
||||
@@ -3338,7 +3338,7 @@
|
||||
if (entry->tls_initialized)
|
||||
return;
|
||||
|
||||
- if ((info->shared || indx != 0)
|
||||
+ if ((!info->executable || indx != 0)
|
||||
&& (h == NULL
|
||||
|| ELF_ST_VISIBILITY (h->root.other) == STV_DEFAULT
|
||||
|| h->root.type != bfd_link_hash_undefweak))
|
||||
@ -1,47 +0,0 @@
|
||||
--- binutils-2.25.1/bfd/elf32-arm.c.orig 2019-10-06 20:40:39.213623570 -0400
|
||||
+++ binutils-2.25.1/bfd/elf32-arm.c 2019-10-06 20:45:09.688207243 -0400
|
||||
@@ -4097,7 +4097,7 @@
|
||||
{
|
||||
int is_local = (h == NULL);
|
||||
|
||||
- if (info->shared || (h && h->root.type == bfd_link_hash_undefweak))
|
||||
+ if (!info->executable || (h && h->root.type == bfd_link_hash_undefweak))
|
||||
return r_type;
|
||||
|
||||
/* We do not support relaxations for Old TLS models. */
|
||||
@@ -9493,7 +9493,7 @@
|
||||
{
|
||||
/* If we don't know the module number, create a relocation
|
||||
for it. */
|
||||
- if (info->shared)
|
||||
+ if (!info->executable)
|
||||
{
|
||||
Elf_Internal_Rela outrel;
|
||||
|
||||
@@ -9581,7 +9581,7 @@
|
||||
now, and emit any relocations. If both an IE GOT and a
|
||||
GD GOT are necessary, we emit the GD first. */
|
||||
|
||||
- if ((info->shared || indx != 0)
|
||||
+ if ((!info->executable || indx != 0)
|
||||
&& (h == NULL
|
||||
|| ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
|
||||
|| h->root.type != bfd_link_hash_undefweak))
|
||||
@@ -9597,7 +9597,7 @@
|
||||
/* We should have relaxed, unless this is an undefined
|
||||
weak symbol. */
|
||||
BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak))
|
||||
- || info->shared);
|
||||
+ || !info->executable);
|
||||
BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8
|
||||
<= globals->root.sgotplt->size);
|
||||
|
||||
@@ -13504,7 +13504,7 @@
|
||||
indx = h->dynindx;
|
||||
|
||||
if (tls_type != GOT_NORMAL
|
||||
- && (info->shared || indx != 0)
|
||||
+ && (!info->executable || indx != 0)
|
||||
&& (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
|
||||
|| h->root.type != bfd_link_hash_undefweak))
|
||||
{
|
||||
@ -1,16 +0,0 @@
|
||||
diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c
|
||||
index bb53e039e3..d52c046979 100644
|
||||
--- a/bfd/elf32-arm.c
|
||||
+++ b/bfd/elf32-arm.c
|
||||
@@ -12027,9 +12027,9 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto,
|
||||
unsigned long data, insn;
|
||||
unsigned thumb;
|
||||
|
||||
- data = bfd_get_32 (input_bfd, hit_data);
|
||||
+ data = bfd_get_signed_32 (input_bfd, hit_data);
|
||||
thumb = data & 1;
|
||||
- data &= ~1u;
|
||||
+ data &= ~1ul;
|
||||
|
||||
if (thumb)
|
||||
{
|
||||
@ -1,33 +0,0 @@
|
||||
--- binutils-2.33.1/bfd/elf32-sh.c.orig 2024-04-04 23:11:28.739136261 +0900
|
||||
+++ binutils-2.33.1/bfd/elf32-sh.c 2024-04-08 23:14:24.496915074 +0900
|
||||
@@ -61,7 +61,7 @@
|
||||
not. If the symbol is protected, we want the local address, but
|
||||
its function descriptor must be assigned by the dynamic linker. */
|
||||
#define SYMBOL_FUNCDESC_LOCAL(INFO, H) \
|
||||
- (SYMBOL_REFERENCES_LOCAL (INFO, H) \
|
||||
+ (!(H) || (H)->dynindx < 0 || (H)->forced_local \
|
||||
|| ! elf_hash_table (INFO)->dynamic_sections_created)
|
||||
|
||||
#define SH_PARTIAL32 TRUE
|
||||
@@ -4405,20 +4405,6 @@
|
||||
/* Undefined weak symbol which will not be dynamically
|
||||
resolved later; leave it at zero. */
|
||||
goto funcdesc_leave_zero;
|
||||
- else if (SYMBOL_CALLS_LOCAL (info, h)
|
||||
- && ! SYMBOL_FUNCDESC_LOCAL (info, h))
|
||||
- {
|
||||
- /* If the symbol needs a non-local function descriptor
|
||||
- but binds locally (i.e., its visibility is
|
||||
- protected), emit a dynamic relocation decayed to
|
||||
- section+offset. This is an optimization; the dynamic
|
||||
- linker would resolve our function descriptor request
|
||||
- to our copy of the function anyway. */
|
||||
- dynindx = elf_section_data (h->root.u.def.section
|
||||
- ->output_section)->dynindx;
|
||||
- relocation += h->root.u.def.section->output_offset
|
||||
- + h->root.u.def.value;
|
||||
- }
|
||||
else if (! SYMBOL_FUNCDESC_LOCAL (info, h))
|
||||
{
|
||||
/* If the symbol is dynamic and there will be dynamic
|
||||
|
||||
@ -1,21 +0,0 @@
|
||||
diff -ur binutils-2.27.orig/bfd/elfxx-mips.c binutils-2.27/bfd/elfxx-mips.c
|
||||
--- binutils-2.27.orig/bfd/elfxx-mips.c 2016-08-03 03:36:51.000000000 -0400
|
||||
+++ binutils-2.27/bfd/elfxx-mips.c 2018-01-31 12:11:22.458824584 -0500
|
||||
@@ -3242,7 +3242,7 @@
|
||||
&& (!bfd_link_pic (info) || !SYMBOL_REFERENCES_LOCAL (info, h)))
|
||||
indx = h->dynindx;
|
||||
|
||||
- if ((bfd_link_pic (info) || indx != 0)
|
||||
+ if ((bfd_link_dll (info) || indx != 0)
|
||||
&& (h == NULL
|
||||
|| ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
|
||||
|| h->root.type != bfd_link_hash_undefweak))
|
||||
@@ -3354,7 +3354,7 @@
|
||||
if (entry->tls_initialized)
|
||||
return;
|
||||
|
||||
- if ((bfd_link_pic (info) || indx != 0)
|
||||
+ if ((bfd_link_dll (info) || indx != 0)
|
||||
&& (h == NULL
|
||||
|| ELF_ST_VISIBILITY (h->root.other) == STV_DEFAULT
|
||||
|| h->root.type != bfd_link_hash_undefweak))
|
||||
@ -1,21 +0,0 @@
|
||||
[PATCH] fix deterministic output for mips archiver
|
||||
|
||||
for historical reasons mips uses a slightly different archive format,
|
||||
and when the --enable-deterministic-archives option was implemented,
|
||||
it was only done for the generic archive format, but not for the one
|
||||
used by mips.
|
||||
|
||||
Signed-off-by: John Spencer <maillist-binutils@barfooze.de>
|
||||
|
||||
--- binutils-2.24.90.org/bfd/archive64.c
|
||||
+++ binutils-2.24.90/bfd/archive64.c
|
||||
@@ -171,7 +171,8 @@
|
||||
if (!_bfd_ar_sizepad (hdr.ar_size, sizeof (hdr.ar_size), mapsize))
|
||||
return FALSE;
|
||||
_bfd_ar_spacepad (hdr.ar_date, sizeof (hdr.ar_date), "%ld",
|
||||
- time (NULL));
|
||||
+ ((arch->flags & BFD_DETERMINISTIC_OUTPUT) == 0
|
||||
+ ? time (NULL) : 0));
|
||||
/* This, at least, is what Intel coff sets the values to.: */
|
||||
_bfd_ar_spacepad (hdr.ar_uid, sizeof (hdr.ar_uid), "%ld", 0);
|
||||
_bfd_ar_spacepad (hdr.ar_gid, sizeof (hdr.ar_gid), "%ld", 0);
|
||||
@ -1,83 +0,0 @@
|
||||
From 7d6e280a0f3b9978b0edb20173d067d071531a3d Mon Sep 17 00:00:00 2001
|
||||
From: Szabolcs Nagy <szabolcs.nagy@arm.com>
|
||||
Date: Wed, 2 Oct 2019 19:46:46 +0100
|
||||
Subject: [PATCH] [PR ld/22263][PR ld/25056] arm: Avoid dynamic TLS relocs in
|
||||
PIE
|
||||
|
||||
Dynamic relocs are only needed in an executable for TLS symbols if
|
||||
those are defined in an external module and even then TLS access
|
||||
can be relaxed to use IE model instead of GD.
|
||||
|
||||
Several bfd_link_pic checks are turned into bfd_link_dll checks
|
||||
to fix TLS handling in PIE, for the same fix some other targets
|
||||
used !bfd_link_executable checks, but that includes relocatable
|
||||
objects so dll seems safer (in most cases either should work, since
|
||||
dynamic relocations are not applied in relocatable objects).
|
||||
|
||||
On arm* fixes
|
||||
FAIL: Build pr22263-1
|
||||
|
||||
bfd/
|
||||
2019-10-02 Szabolcs Nagy <szabolcs.nagy@arm.com>
|
||||
PR ld/22263
|
||||
PR ld/25056
|
||||
* elf32-arm.c (elf32_arm_tls_transition): Use bfd_link_dll instead of
|
||||
bfd_link_pic for TLS checks.
|
||||
(elf32_arm_final_link_relocate): Likewise.
|
||||
(allocate_dynrelocs_for_symbol): Likewise.
|
||||
---
|
||||
bfd/elf32-arm.c | 10 +++++-----
|
||||
1 file changed, 5 insertions(+), 5 deletions(-)
|
||||
|
||||
diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c
|
||||
index bb53e039e3..451949d278 100644
|
||||
--- a/bfd/elf32-arm.c
|
||||
+++ b/bfd/elf32-arm.c
|
||||
@@ -4914,7 +4914,7 @@ elf32_arm_tls_transition (struct bfd_link_info *info, int r_type,
|
||||
{
|
||||
int is_local = (h == NULL);
|
||||
|
||||
- if (bfd_link_pic (info)
|
||||
+ if (bfd_link_dll (info)
|
||||
|| (h && h->root.type == bfd_link_hash_undefweak))
|
||||
return r_type;
|
||||
|
||||
@@ -11700,7 +11700,7 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto,
|
||||
{
|
||||
/* If we don't know the module number, create a relocation
|
||||
for it. */
|
||||
- if (bfd_link_pic (info))
|
||||
+ if (bfd_link_dll (info))
|
||||
{
|
||||
Elf_Internal_Rela outrel;
|
||||
|
||||
@@ -11804,7 +11804,7 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto,
|
||||
now, and emit any relocations. If both an IE GOT and a
|
||||
GD GOT are necessary, we emit the GD first. */
|
||||
|
||||
- if ((bfd_link_pic (info) || indx != 0)
|
||||
+ if ((bfd_link_dll (info) || indx != 0)
|
||||
&& (h == NULL
|
||||
|| (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
|
||||
&& !resolved_to_zero)
|
||||
@@ -11821,7 +11821,7 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto,
|
||||
/* We should have relaxed, unless this is an undefined
|
||||
weak symbol. */
|
||||
BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak))
|
||||
- || bfd_link_pic (info));
|
||||
+ || bfd_link_dll (info));
|
||||
BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8
|
||||
<= globals->root.sgotplt->size);
|
||||
|
||||
@@ -16494,7 +16494,7 @@ allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
|
||||
indx = h->dynindx;
|
||||
|
||||
if (tls_type != GOT_NORMAL
|
||||
- && (bfd_link_pic (info) || indx != 0)
|
||||
+ && (bfd_link_dll (info) || indx != 0)
|
||||
&& (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
|
||||
|| h->root.type != bfd_link_hash_undefweak))
|
||||
{
|
||||
--
|
||||
2.17.1
|
||||
|
||||
@ -1,16 +0,0 @@
|
||||
diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c
|
||||
index bb53e039e3..d52c046979 100644
|
||||
--- a/bfd/elf32-arm.c
|
||||
+++ b/bfd/elf32-arm.c
|
||||
@@ -12027,9 +12027,9 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto,
|
||||
unsigned long data, insn;
|
||||
unsigned thumb;
|
||||
|
||||
- data = bfd_get_32 (input_bfd, hit_data);
|
||||
+ data = bfd_get_signed_32 (input_bfd, hit_data);
|
||||
thumb = data & 1;
|
||||
- data &= ~1u;
|
||||
+ data &= ~1ul;
|
||||
|
||||
if (thumb)
|
||||
{
|
||||
@ -1,33 +0,0 @@
|
||||
--- binutils-2.33.1/bfd/elf32-sh.c.orig 2024-04-04 23:11:28.739136261 +0900
|
||||
+++ binutils-2.33.1/bfd/elf32-sh.c 2024-04-08 23:14:24.496915074 +0900
|
||||
@@ -61,7 +61,7 @@
|
||||
not. If the symbol is protected, we want the local address, but
|
||||
its function descriptor must be assigned by the dynamic linker. */
|
||||
#define SYMBOL_FUNCDESC_LOCAL(INFO, H) \
|
||||
- (SYMBOL_REFERENCES_LOCAL (INFO, H) \
|
||||
+ (!(H) || (H)->dynindx < 0 || (H)->forced_local \
|
||||
|| ! elf_hash_table (INFO)->dynamic_sections_created)
|
||||
|
||||
#define SH_PARTIAL32 TRUE
|
||||
@@ -4405,20 +4405,6 @@
|
||||
/* Undefined weak symbol which will not be dynamically
|
||||
resolved later; leave it at zero. */
|
||||
goto funcdesc_leave_zero;
|
||||
- else if (SYMBOL_CALLS_LOCAL (info, h)
|
||||
- && ! SYMBOL_FUNCDESC_LOCAL (info, h))
|
||||
- {
|
||||
- /* If the symbol needs a non-local function descriptor
|
||||
- but binds locally (i.e., its visibility is
|
||||
- protected), emit a dynamic relocation decayed to
|
||||
- section+offset. This is an optimization; the dynamic
|
||||
- linker would resolve our function descriptor request
|
||||
- to our copy of the function anyway. */
|
||||
- dynindx = elf_section_data (h->root.u.def.section
|
||||
- ->output_section)->dynindx;
|
||||
- relocation += h->root.u.def.section->output_offset
|
||||
- + h->root.u.def.value;
|
||||
- }
|
||||
else if (! SYMBOL_FUNCDESC_LOCAL (info, h))
|
||||
{
|
||||
/* If the symbol is dynamic and there will be dynamic
|
||||
|
||||
@ -1,620 +0,0 @@
|
||||
diff -ur binutils-2.32.orig/bfd/archures.c binutils-2.32/bfd/archures.c
|
||||
--- binutils-2.32.orig/bfd/archures.c 2019-01-19 11:01:32.000000000 -0500
|
||||
+++ binutils-2.32/bfd/archures.c 2019-05-26 15:09:15.968501965 -0400
|
||||
@@ -298,6 +298,8 @@
|
||||
.#define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2
|
||||
.#define bfd_mach_sh2a_or_sh4 0x2a3
|
||||
.#define bfd_mach_sh2a_or_sh3e 0x2a4
|
||||
+.#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5
|
||||
+.#define bfd_mach_shj2 0x2c
|
||||
.#define bfd_mach_sh2e 0x2e
|
||||
.#define bfd_mach_sh3 0x30
|
||||
.#define bfd_mach_sh3_nommu 0x31
|
||||
Only in binutils-2.32/bfd: archures.c.orig
|
||||
Only in binutils-2.32/bfd: archures.c.rej
|
||||
diff -ur binutils-2.32.orig/bfd/bfd-in2.h binutils-2.32/bfd/bfd-in2.h
|
||||
--- binutils-2.32.orig/bfd/bfd-in2.h 2019-01-19 11:01:32.000000000 -0500
|
||||
+++ binutils-2.32/bfd/bfd-in2.h 2019-05-26 15:10:21.005775819 -0400
|
||||
@@ -2197,6 +2197,8 @@
|
||||
#define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2
|
||||
#define bfd_mach_sh2a_or_sh4 0x2a3
|
||||
#define bfd_mach_sh2a_or_sh3e 0x2a4
|
||||
+#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5
|
||||
+#define bfd_mach_shj2 0x2c
|
||||
#define bfd_mach_sh2e 0x2e
|
||||
#define bfd_mach_sh3 0x30
|
||||
#define bfd_mach_sh3_nommu 0x31
|
||||
Only in binutils-2.32/bfd: bfd-in2.h.orig
|
||||
Only in binutils-2.32/bfd: bfd-in2.h.rej
|
||||
diff -ur binutils-2.32.orig/bfd/cpu-sh.c binutils-2.32/bfd/cpu-sh.c
|
||||
--- binutils-2.32.orig/bfd/cpu-sh.c 2019-01-19 11:01:32.000000000 -0500
|
||||
+++ binutils-2.32/bfd/cpu-sh.c 2019-05-26 15:13:00.461455381 -0400
|
||||
@@ -43,7 +43,10 @@
|
||||
#define SH2A_NOFPU_OR_SH4_NOMMU_NOFPU_NEXT arch_info_struct + 16
|
||||
#define SH2A_NOFPU_OR_SH3_NOMMU_NEXT arch_info_struct + 17
|
||||
#define SH2A_OR_SH4_NEXT arch_info_struct + 18
|
||||
-#define SH2A_OR_SH3E_NEXT NULL
|
||||
+#define SH2A_OR_SH3E_NEXT arch_info_struct + 19
|
||||
+#define SHJ2_NEXT arch_info_struct + 20
|
||||
+#define SH2A_NOFPU_OR_SH3_NOMMU_OR_SHJ2_NOFPU_NEXT NULL
|
||||
+
|
||||
|
||||
static const bfd_arch_info_type arch_info_struct[] =
|
||||
{
|
||||
@@ -332,6 +335,36 @@
|
||||
bfd_arch_default_fill,
|
||||
SH2A_OR_SH3E_NEXT
|
||||
},
|
||||
+ {
|
||||
+ 32, /* 32 bits in a word. */
|
||||
+ 32, /* 32 bits in an address. */
|
||||
+ 8, /* 8 bits in a byte. */
|
||||
+ bfd_arch_sh,
|
||||
+ bfd_mach_shj2,
|
||||
+ "sh", /* Architecture name. . */
|
||||
+ "j2", /* Machine name. */
|
||||
+ 1,
|
||||
+ FALSE, /* Not the default. */
|
||||
+ bfd_default_compatible,
|
||||
+ bfd_default_scan,
|
||||
+ bfd_arch_default_fill,
|
||||
+ SHJ2_NEXT
|
||||
+ },
|
||||
+ {
|
||||
+ 32, /* 32 bits in a word. */
|
||||
+ 32, /* 32 bits in an address. */
|
||||
+ 8, /* 8 bits in a byte. */
|
||||
+ bfd_arch_sh,
|
||||
+ bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu,
|
||||
+ "sh", /* Architecture name. . */
|
||||
+ "sh2a-or-sh3e-or-j2", /* Machine name. */
|
||||
+ 1,
|
||||
+ FALSE, /* Not the default. */
|
||||
+ bfd_default_compatible,
|
||||
+ bfd_default_scan,
|
||||
+ bfd_arch_default_fill,
|
||||
+ SH2A_NOFPU_OR_SH3_NOMMU_OR_SHJ2_NOFPU_NEXT
|
||||
+ },
|
||||
};
|
||||
|
||||
const bfd_arch_info_type bfd_sh_arch =
|
||||
@@ -382,6 +415,8 @@
|
||||
{ bfd_mach_sh4_nofpu, arch_sh4_nofpu, arch_sh4_nofpu_up },
|
||||
{ bfd_mach_sh4_nommu_nofpu, arch_sh4_nommu_nofpu, arch_sh4_nommu_nofpu_up },
|
||||
{ bfd_mach_sh4a_nofpu, arch_sh4a_nofpu, arch_sh4a_nofpu_up },
|
||||
+ { bfd_mach_shj2, arch_shj2, arch_shj2_up },
|
||||
+ { bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up },
|
||||
{ 0, 0, 0 } /* Terminator. */
|
||||
};
|
||||
|
||||
Only in binutils-2.32/bfd: cpu-sh.c.orig
|
||||
Only in binutils-2.32/bfd: cpu-sh.c.rej
|
||||
diff -ur binutils-2.32.orig/binutils/readelf.c binutils-2.32/binutils/readelf.c
|
||||
--- binutils-2.32.orig/binutils/readelf.c 2019-01-19 11:01:33.000000000 -0500
|
||||
+++ binutils-2.32/binutils/readelf.c 2019-05-26 15:07:03.563950564 -0400
|
||||
@@ -3528,6 +3528,8 @@
|
||||
case EF_SH2A_SH3_NOFPU: strcat (buf, ", sh2a-nofpu-or-sh3-nommu"); break;
|
||||
case EF_SH2A_SH4: strcat (buf, ", sh2a-or-sh4"); break;
|
||||
case EF_SH2A_SH3E: strcat (buf, ", sh2a-or-sh3e"); break;
|
||||
+ case EF_SHJ2: strcat (buf, ", j2"); break;
|
||||
+ case EF_SH2A_SH3_SHJ2: strcat (buf, ", sh2a-nofpu-or-sh3-nommu-or-shj2 -nofpu"); break;
|
||||
default: strcat (buf, _(", unknown ISA")); break;
|
||||
}
|
||||
|
||||
Only in binutils-2.32/binutils: readelf.c.orig
|
||||
diff -ur binutils-2.32.orig/gas/config/tc-sh.c binutils-2.32/gas/config/tc-sh.c
|
||||
--- binutils-2.32.orig/gas/config/tc-sh.c 2019-01-19 11:01:33.000000000 -0500
|
||||
+++ binutils-2.32/gas/config/tc-sh.c 2019-05-26 15:07:03.567950581 -0400
|
||||
@@ -1251,6 +1251,8 @@
|
||||
ptr++;
|
||||
}
|
||||
get_operand (&ptr, operand + 2);
|
||||
+ if (strcmp (info->name,"cas") == 0)
|
||||
+ operand[2].type = A_IND_0;
|
||||
}
|
||||
else
|
||||
{
|
||||
@@ -1790,7 +1792,10 @@
|
||||
goto fail;
|
||||
reg_m = 4;
|
||||
break;
|
||||
-
|
||||
+ case A_IND_0:
|
||||
+ if (user->reg != 0)
|
||||
+ goto fail;
|
||||
+ break;
|
||||
default:
|
||||
printf (_("unhandled %d\n"), arg);
|
||||
goto fail;
|
||||
Only in binutils-2.32/gas/config: tc-sh.c.orig
|
||||
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s
|
||||
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s 2019-01-19 11:01:33.000000000 -0500
|
||||
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s 2019-05-26 15:07:03.568950585 -0400
|
||||
@@ -12,8 +12,6 @@
|
||||
sh2a_nofpu_or_sh3_nommu:
|
||||
! Instructions introduced into sh2a-nofpu-or-sh3-nommu
|
||||
pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
|
||||
! Instructions inherited from ancestors: sh sh2
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s
|
||||
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s 2019-01-19 11:01:33.000000000 -0500
|
||||
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s 2019-05-26 15:07:03.570950593 -0400
|
||||
@@ -12,7 +12,7 @@
|
||||
sh2a_nofpu_or_sh4_nommu_nofpu:
|
||||
! Instructions introduced into sh2a-nofpu-or-sh4-nommu-nofpu
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -119,8 +119,8 @@
|
||||
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu.s binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-nofpu.s
|
||||
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu.s 2019-01-19 11:01:33.000000000 -0500
|
||||
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-nofpu.s 2019-05-26 15:07:03.571950597 -0400
|
||||
@@ -64,7 +64,7 @@
|
||||
movu.b @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1000dddddddddddd movu.b @(<DISP12>,<REG_M>),<REG_N> */ {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32}
|
||||
movu.w @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */ {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -171,8 +171,8 @@
|
||||
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s
|
||||
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s 2019-01-19 11:01:33.000000000 -0500
|
||||
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s 2019-05-26 15:07:03.572950601 -0400
|
||||
@@ -13,7 +13,7 @@
|
||||
! Instructions introduced into sh2a-or-sh3e
|
||||
fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2e
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2e
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -124,8 +124,8 @@
|
||||
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s
|
||||
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s 2019-01-19 11:01:33.000000000 -0500
|
||||
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s 2019-05-26 15:07:03.574950610 -0400
|
||||
@@ -39,7 +39,7 @@
|
||||
fsub dr4,dr2 ;!/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up}
|
||||
ftrc dr2,FPUL ;!/* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -150,8 +150,8 @@
|
||||
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a.s binutils-2.32/gas/testsuite/gas/sh/arch/sh2a.s
|
||||
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a.s 2019-01-19 11:01:33.000000000 -0500
|
||||
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh2a.s 2019-05-26 15:07:03.575950614 -0400
|
||||
@@ -16,7 +16,7 @@
|
||||
fmov.s fr2,@(2048,r4) ;!/* 0011nnnnmmmm0001 0011dddddddddddd fmov.s <F_REG_M>,@(<DISP12>,<REG_N>) */ {"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY4}, arch_sh2a_up | arch_op32}
|
||||
fmov.s @(2048,r5),fr1 ;!/* 0011nnnnmmmm0001 0111dddddddddddd fmov.s @(<DISP12>,<REG_M>),<F_REG_N> */ {"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -140,8 +140,8 @@
|
||||
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3-dsp.s binutils-2.32/gas/testsuite/gas/sh/arch/sh3-dsp.s
|
||||
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3-dsp.s 2019-01-19 11:01:33.000000000 -0500
|
||||
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh3-dsp.s 2019-05-26 15:07:03.577950622 -0400
|
||||
@@ -12,7 +12,7 @@
|
||||
sh3_dsp:
|
||||
! Instructions introduced into sh3-dsp
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh3 sh3-nommu
|
||||
+! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3 sh3-nommu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -152,8 +152,8 @@
|
||||
setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}
|
||||
repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
|
||||
repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3-nommu.s binutils-2.32/gas/testsuite/gas/sh/arch/sh3-nommu.s
|
||||
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3-nommu.s 2019-01-19 11:01:33.000000000 -0500
|
||||
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh3-nommu.s 2019-05-26 15:07:03.578950626 -0400
|
||||
@@ -26,7 +26,7 @@
|
||||
stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
|
||||
stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -133,8 +133,8 @@
|
||||
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3.s binutils-2.32/gas/testsuite/gas/sh/arch/sh3.s
|
||||
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3.s 2019-01-19 11:01:33.000000000 -0500
|
||||
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh3.s 2019-05-26 15:07:03.579950630 -0400
|
||||
@@ -13,7 +13,7 @@
|
||||
! Instructions introduced into sh3
|
||||
ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh3-nommu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3-nommu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -128,8 +128,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3e.s binutils-2.32/gas/testsuite/gas/sh/arch/sh3e.s
|
||||
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3e.s 2019-01-19 11:01:33.000000000 -0500
|
||||
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh3e.s 2019-05-26 15:07:03.581950639 -0400
|
||||
@@ -12,7 +12,7 @@
|
||||
sh3e:
|
||||
! Instructions introduced into sh3e
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-or-sh3e sh2e sh3 sh3-nommu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-or-sh3e sh2e sh3 sh3-nommu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -132,8 +132,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4-nofpu.s binutils-2.32/gas/testsuite/gas/sh/arch/sh4-nofpu.s
|
||||
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4-nofpu.s 2019-01-19 11:01:33.000000000 -0500
|
||||
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh4-nofpu.s 2019-05-26 15:07:03.582950643 -0400
|
||||
@@ -12,7 +12,7 @@
|
||||
sh4_nofpu:
|
||||
! Instructions introduced into sh4-nofpu
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -136,8 +136,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s binutils-2.32/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s
|
||||
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s 2019-01-19 11:01:33.000000000 -0500
|
||||
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s 2019-05-26 15:07:03.583950647 -0400
|
||||
@@ -24,7 +24,7 @@
|
||||
stc.l SGR,@-r4 ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up}
|
||||
stc.l DBR,@-r4 ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -139,8 +139,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4.s binutils-2.32/gas/testsuite/gas/sh/arch/sh4.s
|
||||
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4.s 2019-01-19 11:01:33.000000000 -0500
|
||||
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh4.s 2019-05-26 15:07:03.585950655 -0400
|
||||
@@ -17,7 +17,7 @@
|
||||
fsrra fr1 ;!/* 1111nnnn01111101 fsrra <F_REG_N> */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up}
|
||||
ftrv xmtrx,fv0 ;!/* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -145,8 +145,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4a-nofpu.s binutils-2.32/gas/testsuite/gas/sh/arch/sh4a-nofpu.s
|
||||
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4a-nofpu.s 2019-01-19 11:01:33.000000000 -0500
|
||||
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh4a-nofpu.s 2019-05-26 15:07:03.586950659 -0400
|
||||
@@ -19,7 +19,7 @@
|
||||
prefi @r4 ;!/* 0000nnnn11010011 prefi @<REG_N> */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofpu_up}
|
||||
synco ;!/* 0000000010101011 synco */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofpu_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -143,8 +143,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4a.s binutils-2.32/gas/testsuite/gas/sh/arch/sh4a.s
|
||||
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4a.s 2019-01-19 11:01:33.000000000 -0500
|
||||
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh4a.s 2019-05-26 15:07:03.588950668 -0400
|
||||
@@ -13,7 +13,7 @@
|
||||
! Instructions introduced into sh4a
|
||||
fpchg ;!/* 1111011111111101 fpchg */{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -147,8 +147,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4al-dsp.s binutils-2.32/gas/testsuite/gas/sh/arch/sh4al-dsp.s
|
||||
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4al-dsp.s 2019-01-19 11:01:33.000000000 -0500
|
||||
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh4al-dsp.s 2019-05-26 15:07:03.589950672 -0400
|
||||
@@ -48,7 +48,7 @@
|
||||
dct pswap x1,m0 ;!/* 10011101xx01zzzz pswap <DSP_REG_X>,<DSP_REG_N> */ {"pswap", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_1}, arch_sh4al_dsp_up}
|
||||
dct pswap y0,m0 ;!/* 1011110101yyzzzz pswap <DSP_REG_Y>,<DSP_REG_N> */ {"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
|
||||
+! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -202,8 +202,8 @@
|
||||
setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}
|
||||
repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
|
||||
repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -ur binutils-2.32.orig/include/elf/sh.h binutils-2.32/include/elf/sh.h
|
||||
--- binutils-2.32.orig/include/elf/sh.h 2019-01-19 11:01:33.000000000 -0500
|
||||
+++ binutils-2.32/include/elf/sh.h 2019-05-26 15:07:03.590950676 -0400
|
||||
@@ -39,6 +39,7 @@
|
||||
#define EF_SH2E 11
|
||||
#define EF_SH4A 12
|
||||
#define EF_SH2A 13
|
||||
+#define EF_SHJ2 14
|
||||
|
||||
#define EF_SH4_NOFPU 16
|
||||
#define EF_SH4A_NOFPU 17
|
||||
@@ -50,6 +51,7 @@
|
||||
#define EF_SH2A_SH3_NOFPU 22
|
||||
#define EF_SH2A_SH4 23
|
||||
#define EF_SH2A_SH3E 24
|
||||
+#define EF_SH2A_SH3_SHJ2 25
|
||||
|
||||
/* This one can only mix in objects from other EF_SH5 objects. */
|
||||
#define EF_SH5 10
|
||||
@@ -72,7 +74,8 @@
|
||||
/* EF_SH2E */ bfd_mach_sh2e , \
|
||||
/* EF_SH4A */ bfd_mach_sh4a , \
|
||||
/* EF_SH2A */ bfd_mach_sh2a , \
|
||||
-/* 14, 15 */ 0, 0, \
|
||||
+/* EF_SHJ2 */ bfd_mach_shj2 , \
|
||||
+/* 15 */ 0, \
|
||||
/* EF_SH4_NOFPU */ bfd_mach_sh4_nofpu , \
|
||||
/* EF_SH4A_NOFPU */ bfd_mach_sh4a_nofpu , \
|
||||
/* EF_SH4_NOMMU_NOFPU */ bfd_mach_sh4_nommu_nofpu, \
|
||||
@@ -81,7 +84,8 @@
|
||||
/* EF_SH2A_SH4_NOFPU */ bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu, \
|
||||
/* EF_SH2A_SH3_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu, \
|
||||
/* EF_SH2A_SH4 */ bfd_mach_sh2a_or_sh4 , \
|
||||
-/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e
|
||||
+/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e, \
|
||||
+/* EF_SH2A_SH3_SHJ2_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu
|
||||
|
||||
/* Convert arch_sh* into EF_SH*. */
|
||||
int sh_find_elf_flags (unsigned int arch_set);
|
||||
diff -ur binutils-2.32.orig/opcodes/sh-dis.c binutils-2.32/opcodes/sh-dis.c
|
||||
--- binutils-2.32.orig/opcodes/sh-dis.c 2019-01-19 11:01:34.000000000 -0500
|
||||
+++ binutils-2.32/opcodes/sh-dis.c 2019-05-26 15:07:03.593950688 -0400
|
||||
@@ -856,6 +856,9 @@
|
||||
case XMTRX_M4:
|
||||
fprintf_fn (stream, "xmtrx");
|
||||
break;
|
||||
+ case A_IND_0:
|
||||
+ fprintf_fn (stream, "@r0");
|
||||
+ break;
|
||||
default:
|
||||
abort ();
|
||||
}
|
||||
Only in binutils-2.32/opcodes: sh-dis.c.orig
|
||||
diff -ur binutils-2.32.orig/opcodes/sh-opc.h binutils-2.32/opcodes/sh-opc.h
|
||||
--- binutils-2.32.orig/opcodes/sh-opc.h 2019-01-19 11:01:34.000000000 -0500
|
||||
+++ binutils-2.32/opcodes/sh-opc.h 2019-05-26 15:07:03.597950705 -0400
|
||||
@@ -191,7 +191,8 @@
|
||||
FPUL_N,
|
||||
FPUL_M,
|
||||
FPSCR_N,
|
||||
- FPSCR_M
|
||||
+ FPSCR_M,
|
||||
+ A_IND_0
|
||||
}
|
||||
sh_arg_type;
|
||||
|
||||
@@ -215,9 +216,11 @@
|
||||
#define arch_sh4_base (1 << 5)
|
||||
#define arch_sh4a_base (1 << 6)
|
||||
#define arch_sh2a_base (1 << 7)
|
||||
-#define arch_sh_base_mask MASK (0, 7)
|
||||
+#define arch_shj2_base (1 << 8)
|
||||
+#define arch_sh2a_sh3_shj2_base (1 << 9)
|
||||
+#define arch_sh_base_mask MASK (0, 9)
|
||||
|
||||
-/* Bits 8 ... 24 are currently free. */
|
||||
+/* Bits 10 ... 24 are currently free. */
|
||||
|
||||
/* This is an annotation on instruction types, but we
|
||||
abuse the arch field in instructions to denote it. */
|
||||
@@ -255,6 +258,8 @@
|
||||
#define arch_sh2a_nofpu_or_sh3_nommu (arch_sh2a_sh3_base|arch_sh_no_mmu |arch_sh_no_co)
|
||||
#define arch_sh2a_or_sh3e (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_sp_fpu)
|
||||
#define arch_sh2a_or_sh4 (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_dp_fpu)
|
||||
+#define arch_shj2 (arch_shj2_base |arch_sh_no_mmu |arch_sh_no_co)
|
||||
+#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu (arch_sh2a_sh3_shj2_base|arch_sh_no_mmu |arch_sh_no_co)
|
||||
|
||||
#define SH_MERGE_ARCH_SET(SET1, SET2) ((SET1) & (SET2))
|
||||
#define SH_VALID_BASE_ARCH_SET(SET) (((SET) & arch_sh_base_mask) != 0)
|
||||
@@ -319,7 +324,8 @@
|
||||
#define arch_sh2_up (arch_sh2 \
|
||||
| arch_sh2e_up \
|
||||
| arch_sh2a_nofpu_or_sh3_nommu_up \
|
||||
- | arch_sh_dsp_up)
|
||||
+ | arch_sh_dsp_up \
|
||||
+ | arch_shj2_up)
|
||||
#define arch_sh2a_nofpu_or_sh3_nommu_up (arch_sh2a_nofpu_or_sh3_nommu \
|
||||
| arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \
|
||||
| arch_sh2a_or_sh3e_up \
|
||||
@@ -345,6 +351,12 @@
|
||||
#define arch_sh4a_nofpu_up (arch_sh4a_nofpu \
|
||||
| arch_sh4a_up \
|
||||
| arch_sh4al_dsp_up)
|
||||
+#define arch_shj2_up ( arch_shj2)
|
||||
+#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up (arch_sh2a_nofpu_or_sh3_nommu \
|
||||
+ | arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \
|
||||
+ | arch_sh2a_or_sh3e_up \
|
||||
+ | arch_sh3_nommu_up \
|
||||
+ | arch_shj2_up)
|
||||
|
||||
/* Right branches. */
|
||||
#define arch_sh2e_up (arch_sh2e \
|
||||
@@ -713,9 +725,9 @@
|
||||
|
||||
/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up},
|
||||
|
||||
-/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up},
|
||||
+/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up},
|
||||
|
||||
-/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up},
|
||||
+/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up},
|
||||
|
||||
/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up},
|
||||
|
||||
@@ -1193,7 +1205,7 @@
|
||||
{"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32},
|
||||
/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */
|
||||
{"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32},
|
||||
-
|
||||
+ /* 0010nnnnmmmm0011 cas.l Rm,Rn,@R0 */ {"cas.l", { A_REG_M,A_REG_N,A_IND_0},{HEX_2,REG_N,REG_M,HEX_3}, arch_shj2_up},
|
||||
{ 0, {0}, {0}, 0 }
|
||||
};
|
||||
|
||||
Only in binutils-2.32/opcodes: sh-opc.h.orig
|
||||
@ -1,83 +0,0 @@
|
||||
From 7d6e280a0f3b9978b0edb20173d067d071531a3d Mon Sep 17 00:00:00 2001
|
||||
From: Szabolcs Nagy <szabolcs.nagy@arm.com>
|
||||
Date: Wed, 2 Oct 2019 19:46:46 +0100
|
||||
Subject: [PATCH] [PR ld/22263][PR ld/25056] arm: Avoid dynamic TLS relocs in
|
||||
PIE
|
||||
|
||||
Dynamic relocs are only needed in an executable for TLS symbols if
|
||||
those are defined in an external module and even then TLS access
|
||||
can be relaxed to use IE model instead of GD.
|
||||
|
||||
Several bfd_link_pic checks are turned into bfd_link_dll checks
|
||||
to fix TLS handling in PIE, for the same fix some other targets
|
||||
used !bfd_link_executable checks, but that includes relocatable
|
||||
objects so dll seems safer (in most cases either should work, since
|
||||
dynamic relocations are not applied in relocatable objects).
|
||||
|
||||
On arm* fixes
|
||||
FAIL: Build pr22263-1
|
||||
|
||||
bfd/
|
||||
2019-10-02 Szabolcs Nagy <szabolcs.nagy@arm.com>
|
||||
PR ld/22263
|
||||
PR ld/25056
|
||||
* elf32-arm.c (elf32_arm_tls_transition): Use bfd_link_dll instead of
|
||||
bfd_link_pic for TLS checks.
|
||||
(elf32_arm_final_link_relocate): Likewise.
|
||||
(allocate_dynrelocs_for_symbol): Likewise.
|
||||
---
|
||||
bfd/elf32-arm.c | 10 +++++-----
|
||||
1 file changed, 5 insertions(+), 5 deletions(-)
|
||||
|
||||
diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c
|
||||
index bb53e039e3..451949d278 100644
|
||||
--- a/bfd/elf32-arm.c
|
||||
+++ b/bfd/elf32-arm.c
|
||||
@@ -4914,7 +4914,7 @@ elf32_arm_tls_transition (struct bfd_link_info *info, int r_type,
|
||||
{
|
||||
int is_local = (h == NULL);
|
||||
|
||||
- if (bfd_link_pic (info)
|
||||
+ if (bfd_link_dll (info)
|
||||
|| (h && h->root.type == bfd_link_hash_undefweak))
|
||||
return r_type;
|
||||
|
||||
@@ -11700,7 +11700,7 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto,
|
||||
{
|
||||
/* If we don't know the module number, create a relocation
|
||||
for it. */
|
||||
- if (bfd_link_pic (info))
|
||||
+ if (bfd_link_dll (info))
|
||||
{
|
||||
Elf_Internal_Rela outrel;
|
||||
|
||||
@@ -11804,7 +11804,7 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto,
|
||||
now, and emit any relocations. If both an IE GOT and a
|
||||
GD GOT are necessary, we emit the GD first. */
|
||||
|
||||
- if ((bfd_link_pic (info) || indx != 0)
|
||||
+ if ((bfd_link_dll (info) || indx != 0)
|
||||
&& (h == NULL
|
||||
|| (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
|
||||
&& !resolved_to_zero)
|
||||
@@ -11821,7 +11821,7 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto,
|
||||
/* We should have relaxed, unless this is an undefined
|
||||
weak symbol. */
|
||||
BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak))
|
||||
- || bfd_link_pic (info));
|
||||
+ || bfd_link_dll (info));
|
||||
BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8
|
||||
<= globals->root.sgotplt->size);
|
||||
|
||||
@@ -16494,7 +16494,7 @@ allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
|
||||
indx = h->dynindx;
|
||||
|
||||
if (tls_type != GOT_NORMAL
|
||||
- && (bfd_link_pic (info) || indx != 0)
|
||||
+ && (bfd_link_dll (info) || indx != 0)
|
||||
&& (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
|
||||
|| h->root.type != bfd_link_hash_undefweak))
|
||||
{
|
||||
--
|
||||
2.17.1
|
||||
|
||||
@ -1,16 +0,0 @@
|
||||
diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c
|
||||
index bb53e039e3..d52c046979 100644
|
||||
--- a/bfd/elf32-arm.c
|
||||
+++ b/bfd/elf32-arm.c
|
||||
@@ -12027,9 +12027,9 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto,
|
||||
unsigned long data, insn;
|
||||
unsigned thumb;
|
||||
|
||||
- data = bfd_get_32 (input_bfd, hit_data);
|
||||
+ data = bfd_get_signed_32 (input_bfd, hit_data);
|
||||
thumb = data & 1;
|
||||
- data &= ~1u;
|
||||
+ data &= ~1ul;
|
||||
|
||||
if (thumb)
|
||||
{
|
||||
@ -1,55 +0,0 @@
|
||||
From: Szabolcs Nagy <szabolcs.nagy@arm.com>
|
||||
Date: Thu, 9 Jan 2020 17:20:56 +0000 (+0000)
|
||||
Subject: [PR ld/22269] arm: Avoid dynamic relocs for undefweak symbols in static PIE
|
||||
X-Git-Url: https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=commitdiff_plain;h=6fbcfe4762c3732339cffd82426d00d35382b858;hp=c06868784d819a45c43947180c69e168aecaf368
|
||||
|
||||
[PR ld/22269] arm: Avoid dynamic relocs for undefweak symbols in static PIE
|
||||
|
||||
With static PIE linking undefined weak symbols are resolved to 0, so no
|
||||
dynamic relocation is needed for them. The UNDEFWEAK_NO_DYNAMIC_RELOC
|
||||
macro was introduced so this case can be handled easily, but it was not
|
||||
applied consistently in the first attempt to fix ld/22269 for arm:
|
||||
|
||||
commit 95b03e4ad68e7a90f5096b47df595636344b783a
|
||||
arm: Check UNDEFWEAK_NO_DYNAMIC_RELOC
|
||||
|
||||
This patch fixes spurious relative relocs in static PIE binaries against
|
||||
GOT entries created for undefined weak symbols on arm*-*, this fixes
|
||||
|
||||
FAIL: pr22269-1 (static pie undefined weak)
|
||||
|
||||
bfd/ChangeLog:
|
||||
|
||||
Backported from master
|
||||
2020-01-10 Szabolcs Nagy <szabolcs.nagy@arm.com>
|
||||
|
||||
PR ld/22269
|
||||
* elf32-arm.c (elf32_arm_final_link_relocate): Use
|
||||
UNDEFWEAK_NO_DYNAMIC_RELOC.
|
||||
(allocate_dynrelocs_for_symbol): Likewise.
|
||||
---
|
||||
|
||||
diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c
|
||||
index cce796d..21cf4b0 100644
|
||||
--- a/bfd/elf32-arm.c
|
||||
+++ b/bfd/elf32-arm.c
|
||||
@@ -11572,8 +11572,7 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto,
|
||||
if (dynreloc_st_type == STT_GNU_IFUNC)
|
||||
outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
|
||||
else if (bfd_link_pic (info)
|
||||
- && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
|
||||
- || h->root.type != bfd_link_hash_undefweak))
|
||||
+ && !UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
|
||||
outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
|
||||
else
|
||||
{
|
||||
@@ -16527,8 +16526,7 @@ allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
|
||||
GOT entry's R_ARM_IRELATIVE relocation. */
|
||||
elf32_arm_allocate_irelocs (info, htab->root.srelgot, 1);
|
||||
else if (bfd_link_pic (info)
|
||||
- && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
|
||||
- || h->root.type != bfd_link_hash_undefweak))
|
||||
+ && !UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
|
||||
/* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
|
||||
elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
|
||||
else if (htab->fdpic_p && tls_type == GOT_NORMAL)
|
||||
@ -1,33 +0,0 @@
|
||||
--- binutils-2.33.1/bfd/elf32-sh.c.orig 2024-04-04 23:11:28.739136261 +0900
|
||||
+++ binutils-2.33.1/bfd/elf32-sh.c 2024-04-08 23:14:24.496915074 +0900
|
||||
@@ -61,7 +61,7 @@
|
||||
not. If the symbol is protected, we want the local address, but
|
||||
its function descriptor must be assigned by the dynamic linker. */
|
||||
#define SYMBOL_FUNCDESC_LOCAL(INFO, H) \
|
||||
- (SYMBOL_REFERENCES_LOCAL (INFO, H) \
|
||||
+ (!(H) || (H)->dynindx < 0 || (H)->forced_local \
|
||||
|| ! elf_hash_table (INFO)->dynamic_sections_created)
|
||||
|
||||
#define SH_PARTIAL32 TRUE
|
||||
@@ -4405,20 +4405,6 @@
|
||||
/* Undefined weak symbol which will not be dynamically
|
||||
resolved later; leave it at zero. */
|
||||
goto funcdesc_leave_zero;
|
||||
- else if (SYMBOL_CALLS_LOCAL (info, h)
|
||||
- && ! SYMBOL_FUNCDESC_LOCAL (info, h))
|
||||
- {
|
||||
- /* If the symbol needs a non-local function descriptor
|
||||
- but binds locally (i.e., its visibility is
|
||||
- protected), emit a dynamic relocation decayed to
|
||||
- section+offset. This is an optimization; the dynamic
|
||||
- linker would resolve our function descriptor request
|
||||
- to our copy of the function anyway. */
|
||||
- dynindx = elf_section_data (h->root.u.def.section
|
||||
- ->output_section)->dynindx;
|
||||
- relocation += h->root.u.def.section->output_offset
|
||||
- + h->root.u.def.value;
|
||||
- }
|
||||
else if (! SYMBOL_FUNCDESC_LOCAL (info, h))
|
||||
{
|
||||
/* If the symbol is dynamic and there will be dynamic
|
||||
|
||||
@ -1,620 +0,0 @@
|
||||
diff -ur binutils-2.32.orig/bfd/archures.c binutils-2.32/bfd/archures.c
|
||||
--- binutils-2.32.orig/bfd/archures.c 2019-01-19 11:01:32.000000000 -0500
|
||||
+++ binutils-2.32/bfd/archures.c 2019-05-26 15:09:15.968501965 -0400
|
||||
@@ -298,6 +298,8 @@
|
||||
.#define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2
|
||||
.#define bfd_mach_sh2a_or_sh4 0x2a3
|
||||
.#define bfd_mach_sh2a_or_sh3e 0x2a4
|
||||
+.#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5
|
||||
+.#define bfd_mach_shj2 0x2c
|
||||
.#define bfd_mach_sh2e 0x2e
|
||||
.#define bfd_mach_sh3 0x30
|
||||
.#define bfd_mach_sh3_nommu 0x31
|
||||
Only in binutils-2.32/bfd: archures.c.orig
|
||||
Only in binutils-2.32/bfd: archures.c.rej
|
||||
diff -ur binutils-2.32.orig/bfd/bfd-in2.h binutils-2.32/bfd/bfd-in2.h
|
||||
--- binutils-2.32.orig/bfd/bfd-in2.h 2019-01-19 11:01:32.000000000 -0500
|
||||
+++ binutils-2.32/bfd/bfd-in2.h 2019-05-26 15:10:21.005775819 -0400
|
||||
@@ -2197,6 +2197,8 @@
|
||||
#define bfd_mach_sh2a_nofpu_or_sh3_nommu 0x2a2
|
||||
#define bfd_mach_sh2a_or_sh4 0x2a3
|
||||
#define bfd_mach_sh2a_or_sh3e 0x2a4
|
||||
+#define bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu 0x2a5
|
||||
+#define bfd_mach_shj2 0x2c
|
||||
#define bfd_mach_sh2e 0x2e
|
||||
#define bfd_mach_sh3 0x30
|
||||
#define bfd_mach_sh3_nommu 0x31
|
||||
Only in binutils-2.32/bfd: bfd-in2.h.orig
|
||||
Only in binutils-2.32/bfd: bfd-in2.h.rej
|
||||
diff -ur binutils-2.32.orig/bfd/cpu-sh.c binutils-2.32/bfd/cpu-sh.c
|
||||
--- binutils-2.32.orig/bfd/cpu-sh.c 2019-01-19 11:01:32.000000000 -0500
|
||||
+++ binutils-2.32/bfd/cpu-sh.c 2019-05-26 15:13:00.461455381 -0400
|
||||
@@ -43,7 +43,10 @@
|
||||
#define SH2A_NOFPU_OR_SH4_NOMMU_NOFPU_NEXT arch_info_struct + 16
|
||||
#define SH2A_NOFPU_OR_SH3_NOMMU_NEXT arch_info_struct + 17
|
||||
#define SH2A_OR_SH4_NEXT arch_info_struct + 18
|
||||
-#define SH2A_OR_SH3E_NEXT NULL
|
||||
+#define SH2A_OR_SH3E_NEXT arch_info_struct + 19
|
||||
+#define SHJ2_NEXT arch_info_struct + 20
|
||||
+#define SH2A_NOFPU_OR_SH3_NOMMU_OR_SHJ2_NOFPU_NEXT NULL
|
||||
+
|
||||
|
||||
static const bfd_arch_info_type arch_info_struct[] =
|
||||
{
|
||||
@@ -332,6 +335,36 @@
|
||||
bfd_arch_default_fill,
|
||||
SH2A_OR_SH3E_NEXT
|
||||
},
|
||||
+ {
|
||||
+ 32, /* 32 bits in a word. */
|
||||
+ 32, /* 32 bits in an address. */
|
||||
+ 8, /* 8 bits in a byte. */
|
||||
+ bfd_arch_sh,
|
||||
+ bfd_mach_shj2,
|
||||
+ "sh", /* Architecture name. . */
|
||||
+ "j2", /* Machine name. */
|
||||
+ 1,
|
||||
+ FALSE, /* Not the default. */
|
||||
+ bfd_default_compatible,
|
||||
+ bfd_default_scan,
|
||||
+ bfd_arch_default_fill,
|
||||
+ SHJ2_NEXT
|
||||
+ },
|
||||
+ {
|
||||
+ 32, /* 32 bits in a word. */
|
||||
+ 32, /* 32 bits in an address. */
|
||||
+ 8, /* 8 bits in a byte. */
|
||||
+ bfd_arch_sh,
|
||||
+ bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu,
|
||||
+ "sh", /* Architecture name. . */
|
||||
+ "sh2a-or-sh3e-or-j2", /* Machine name. */
|
||||
+ 1,
|
||||
+ FALSE, /* Not the default. */
|
||||
+ bfd_default_compatible,
|
||||
+ bfd_default_scan,
|
||||
+ bfd_arch_default_fill,
|
||||
+ SH2A_NOFPU_OR_SH3_NOMMU_OR_SHJ2_NOFPU_NEXT
|
||||
+ },
|
||||
};
|
||||
|
||||
const bfd_arch_info_type bfd_sh_arch =
|
||||
@@ -382,6 +415,8 @@
|
||||
{ bfd_mach_sh4_nofpu, arch_sh4_nofpu, arch_sh4_nofpu_up },
|
||||
{ bfd_mach_sh4_nommu_nofpu, arch_sh4_nommu_nofpu, arch_sh4_nommu_nofpu_up },
|
||||
{ bfd_mach_sh4a_nofpu, arch_sh4a_nofpu, arch_sh4a_nofpu_up },
|
||||
+ { bfd_mach_shj2, arch_shj2, arch_shj2_up },
|
||||
+ { bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up },
|
||||
{ 0, 0, 0 } /* Terminator. */
|
||||
};
|
||||
|
||||
Only in binutils-2.32/bfd: cpu-sh.c.orig
|
||||
Only in binutils-2.32/bfd: cpu-sh.c.rej
|
||||
diff -ur binutils-2.32.orig/binutils/readelf.c binutils-2.32/binutils/readelf.c
|
||||
--- binutils-2.32.orig/binutils/readelf.c 2019-01-19 11:01:33.000000000 -0500
|
||||
+++ binutils-2.32/binutils/readelf.c 2019-05-26 15:07:03.563950564 -0400
|
||||
@@ -3528,6 +3528,8 @@
|
||||
case EF_SH2A_SH3_NOFPU: strcat (buf, ", sh2a-nofpu-or-sh3-nommu"); break;
|
||||
case EF_SH2A_SH4: strcat (buf, ", sh2a-or-sh4"); break;
|
||||
case EF_SH2A_SH3E: strcat (buf, ", sh2a-or-sh3e"); break;
|
||||
+ case EF_SHJ2: strcat (buf, ", j2"); break;
|
||||
+ case EF_SH2A_SH3_SHJ2: strcat (buf, ", sh2a-nofpu-or-sh3-nommu-or-shj2 -nofpu"); break;
|
||||
default: strcat (buf, _(", unknown ISA")); break;
|
||||
}
|
||||
|
||||
Only in binutils-2.32/binutils: readelf.c.orig
|
||||
diff -ur binutils-2.32.orig/gas/config/tc-sh.c binutils-2.32/gas/config/tc-sh.c
|
||||
--- binutils-2.32.orig/gas/config/tc-sh.c 2019-01-19 11:01:33.000000000 -0500
|
||||
+++ binutils-2.32/gas/config/tc-sh.c 2019-05-26 15:07:03.567950581 -0400
|
||||
@@ -1251,6 +1251,8 @@
|
||||
ptr++;
|
||||
}
|
||||
get_operand (&ptr, operand + 2);
|
||||
+ if (strcmp (info->name,"cas") == 0)
|
||||
+ operand[2].type = A_IND_0;
|
||||
}
|
||||
else
|
||||
{
|
||||
@@ -1790,7 +1792,10 @@
|
||||
goto fail;
|
||||
reg_m = 4;
|
||||
break;
|
||||
-
|
||||
+ case A_IND_0:
|
||||
+ if (user->reg != 0)
|
||||
+ goto fail;
|
||||
+ break;
|
||||
default:
|
||||
printf (_("unhandled %d\n"), arg);
|
||||
goto fail;
|
||||
Only in binutils-2.32/gas/config: tc-sh.c.orig
|
||||
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s
|
||||
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s 2019-01-19 11:01:33.000000000 -0500
|
||||
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh3-nommu.s 2019-05-26 15:07:03.568950585 -0400
|
||||
@@ -12,8 +12,6 @@
|
||||
sh2a_nofpu_or_sh3_nommu:
|
||||
! Instructions introduced into sh2a-nofpu-or-sh3-nommu
|
||||
pref @r4 ;!/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
|
||||
! Instructions inherited from ancestors: sh sh2
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s
|
||||
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s 2019-01-19 11:01:33.000000000 -0500
|
||||
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-nofpu-or-sh4-nommu-nofpu.s 2019-05-26 15:07:03.570950593 -0400
|
||||
@@ -12,7 +12,7 @@
|
||||
sh2a_nofpu_or_sh4_nommu_nofpu:
|
||||
! Instructions introduced into sh2a-nofpu-or-sh4-nommu-nofpu
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -119,8 +119,8 @@
|
||||
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu.s binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-nofpu.s
|
||||
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-nofpu.s 2019-01-19 11:01:33.000000000 -0500
|
||||
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-nofpu.s 2019-05-26 15:07:03.571950597 -0400
|
||||
@@ -64,7 +64,7 @@
|
||||
movu.b @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1000dddddddddddd movu.b @(<DISP12>,<REG_M>),<REG_N> */ {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32}
|
||||
movu.w @(2048,r5),r4 ;!/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */ {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -171,8 +171,8 @@
|
||||
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s
|
||||
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s 2019-01-19 11:01:33.000000000 -0500
|
||||
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-or-sh3e.s 2019-05-26 15:07:03.572950601 -0400
|
||||
@@ -13,7 +13,7 @@
|
||||
! Instructions introduced into sh2a-or-sh3e
|
||||
fsqrt fr1 ;!/* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh2a_or_sh3e_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2e
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2e
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -124,8 +124,8 @@
|
||||
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s
|
||||
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s 2019-01-19 11:01:33.000000000 -0500
|
||||
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh2a-or-sh4.s 2019-05-26 15:07:03.574950610 -0400
|
||||
@@ -39,7 +39,7 @@
|
||||
fsub dr4,dr2 ;!/* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2a_or_sh4_up}
|
||||
ftrc dr2,FPUL ;!/* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2a_or_sh4_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2e
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -150,8 +150,8 @@
|
||||
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a.s binutils-2.32/gas/testsuite/gas/sh/arch/sh2a.s
|
||||
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh2a.s 2019-01-19 11:01:33.000000000 -0500
|
||||
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh2a.s 2019-05-26 15:07:03.575950614 -0400
|
||||
@@ -16,7 +16,7 @@
|
||||
fmov.s fr2,@(2048,r4) ;!/* 0011nnnnmmmm0001 0011dddddddddddd fmov.s <F_REG_M>,@(<DISP12>,<REG_N>) */ {"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY4}, arch_sh2a_up | arch_op32}
|
||||
fmov.s @(2048,r5),fr1 ;!/* 0011nnnnmmmm0001 0111dddddddddddd fmov.s @(<DISP12>,<REG_M>),<F_REG_N> */ {"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -140,8 +140,8 @@
|
||||
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3-dsp.s binutils-2.32/gas/testsuite/gas/sh/arch/sh3-dsp.s
|
||||
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3-dsp.s 2019-01-19 11:01:33.000000000 -0500
|
||||
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh3-dsp.s 2019-05-26 15:07:03.577950622 -0400
|
||||
@@ -12,7 +12,7 @@
|
||||
sh3_dsp:
|
||||
! Instructions introduced into sh3-dsp
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh3 sh3-nommu
|
||||
+! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3 sh3-nommu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -152,8 +152,8 @@
|
||||
setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}
|
||||
repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
|
||||
repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3-nommu.s binutils-2.32/gas/testsuite/gas/sh/arch/sh3-nommu.s
|
||||
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3-nommu.s 2019-01-19 11:01:33.000000000 -0500
|
||||
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh3-nommu.s 2019-05-26 15:07:03.578950626 -0400
|
||||
@@ -26,7 +26,7 @@
|
||||
stc.l SPC,@-r4 ;!/* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up}
|
||||
stc.l r1_bank,@-r4 ;!/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -133,8 +133,8 @@
|
||||
rte ;!/* 0000000000101011 rte */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh_up}
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3.s binutils-2.32/gas/testsuite/gas/sh/arch/sh3.s
|
||||
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3.s 2019-01-19 11:01:33.000000000 -0500
|
||||
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh3.s 2019-05-26 15:07:03.579950630 -0400
|
||||
@@ -13,7 +13,7 @@
|
||||
! Instructions introduced into sh3
|
||||
ldtlb ;!/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh3-nommu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh3-nommu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -128,8 +128,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3e.s binutils-2.32/gas/testsuite/gas/sh/arch/sh3e.s
|
||||
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh3e.s 2019-01-19 11:01:33.000000000 -0500
|
||||
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh3e.s 2019-05-26 15:07:03.581950639 -0400
|
||||
@@ -12,7 +12,7 @@
|
||||
sh3e:
|
||||
! Instructions introduced into sh3e
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-or-sh3e sh2e sh3 sh3-nommu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-or-sh3e sh2e sh3 sh3-nommu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -132,8 +132,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4-nofpu.s binutils-2.32/gas/testsuite/gas/sh/arch/sh4-nofpu.s
|
||||
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4-nofpu.s 2019-01-19 11:01:33.000000000 -0500
|
||||
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh4-nofpu.s 2019-05-26 15:07:03.582950643 -0400
|
||||
@@ -12,7 +12,7 @@
|
||||
sh4_nofpu:
|
||||
! Instructions introduced into sh4-nofpu
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nommu-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -136,8 +136,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s binutils-2.32/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s
|
||||
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s 2019-01-19 11:01:33.000000000 -0500
|
||||
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh4-nommu-nofpu.s 2019-05-26 15:07:03.583950647 -0400
|
||||
@@ -24,7 +24,7 @@
|
||||
stc.l SGR,@-r4 ;!/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up}
|
||||
stc.l DBR,@-r4 ;!/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3-nommu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -139,8 +139,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4.s binutils-2.32/gas/testsuite/gas/sh/arch/sh4.s
|
||||
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4.s 2019-01-19 11:01:33.000000000 -0500
|
||||
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh4.s 2019-05-26 15:07:03.585950655 -0400
|
||||
@@ -17,7 +17,7 @@
|
||||
fsrra fr1 ;!/* 1111nnnn01111101 fsrra <F_REG_N> */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up}
|
||||
ftrv xmtrx,fv0 ;!/* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4-nofpu sh4-nommu-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -145,8 +145,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4a-nofpu.s binutils-2.32/gas/testsuite/gas/sh/arch/sh4a-nofpu.s
|
||||
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4a-nofpu.s 2019-01-19 11:01:33.000000000 -0500
|
||||
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh4a-nofpu.s 2019-05-26 15:07:03.586950659 -0400
|
||||
@@ -19,7 +19,7 @@
|
||||
prefi @r4 ;!/* 0000nnnn11010011 prefi @<REG_N> */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofpu_up}
|
||||
synco ;!/* 0000000010101011 synco */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofpu_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-nommu sh4-nofpu sh4-nommu-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -143,8 +143,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4a.s binutils-2.32/gas/testsuite/gas/sh/arch/sh4a.s
|
||||
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4a.s 2019-01-19 11:01:33.000000000 -0500
|
||||
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh4a.s 2019-05-26 15:07:03.588950668 -0400
|
||||
@@ -13,7 +13,7 @@
|
||||
! Instructions introduced into sh4a
|
||||
fpchg ;!/* 1111011111111101 fpchg */{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
|
||||
+! Instructions inherited from ancestors: sh sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh2a-or-sh3e sh2a-or-sh4 sh2e sh3 sh3-nommu sh3e sh4 sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -147,8 +147,8 @@
|
||||
rts ;!/* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh_up}
|
||||
sets ;!/* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh3_nommu_up}
|
||||
sett ;!/* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -ur binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4al-dsp.s binutils-2.32/gas/testsuite/gas/sh/arch/sh4al-dsp.s
|
||||
--- binutils-2.32.orig/gas/testsuite/gas/sh/arch/sh4al-dsp.s 2019-01-19 11:01:33.000000000 -0500
|
||||
+++ binutils-2.32/gas/testsuite/gas/sh/arch/sh4al-dsp.s 2019-05-26 15:07:03.589950672 -0400
|
||||
@@ -48,7 +48,7 @@
|
||||
dct pswap x1,m0 ;!/* 10011101xx01zzzz pswap <DSP_REG_X>,<DSP_REG_N> */ {"pswap", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_1}, arch_sh4al_dsp_up}
|
||||
dct pswap y0,m0 ;!/* 1011110101yyzzzz pswap <DSP_REG_Y>,<DSP_REG_N> */ {"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up}
|
||||
|
||||
-! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
|
||||
+! Instructions inherited from ancestors: sh sh-dsp sh2 sh2a-nofpu-or-sh3-nommu sh2a-nofpu-or-sh3-nommu-or-sh2j-nofpu sh2a-nofpu-or-sh4-nommu-nofpu sh3 sh3-dsp sh3-nommu sh4-nofpu sh4-nommu-nofpu sh4a-nofpu
|
||||
add #4,r4 ;!/* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh_up}
|
||||
add r5,r4 ;!/* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh_up}
|
||||
addc r5,r4 ;!/* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh_up}
|
||||
@@ -202,8 +202,8 @@
|
||||
setrc #4 ;!/* 10000010i8*1.... setrc #<imm> */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up}
|
||||
repeat 10 20 r4 ;!/* repeat start end <REG_N> */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up}
|
||||
repeat 10 20 #4 ;!/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up}
|
||||
- shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
- shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up}
|
||||
+ shad r5,r4 ;!/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
+ shld r5,r4 ;!/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_sh2j_nofpu_up}
|
||||
shal r4 ;!/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up}
|
||||
shar r4 ;!/* 0100nnnn00100001 shar <REG_N> */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh_up}
|
||||
shll r4 ;!/* 0100nnnn00000000 shll <REG_N> */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh_up}
|
||||
diff -ur binutils-2.32.orig/include/elf/sh.h binutils-2.32/include/elf/sh.h
|
||||
--- binutils-2.32.orig/include/elf/sh.h 2019-01-19 11:01:33.000000000 -0500
|
||||
+++ binutils-2.32/include/elf/sh.h 2019-05-26 15:07:03.590950676 -0400
|
||||
@@ -39,6 +39,7 @@
|
||||
#define EF_SH2E 11
|
||||
#define EF_SH4A 12
|
||||
#define EF_SH2A 13
|
||||
+#define EF_SHJ2 14
|
||||
|
||||
#define EF_SH4_NOFPU 16
|
||||
#define EF_SH4A_NOFPU 17
|
||||
@@ -50,6 +51,7 @@
|
||||
#define EF_SH2A_SH3_NOFPU 22
|
||||
#define EF_SH2A_SH4 23
|
||||
#define EF_SH2A_SH3E 24
|
||||
+#define EF_SH2A_SH3_SHJ2 25
|
||||
|
||||
/* This one can only mix in objects from other EF_SH5 objects. */
|
||||
#define EF_SH5 10
|
||||
@@ -72,7 +74,8 @@
|
||||
/* EF_SH2E */ bfd_mach_sh2e , \
|
||||
/* EF_SH4A */ bfd_mach_sh4a , \
|
||||
/* EF_SH2A */ bfd_mach_sh2a , \
|
||||
-/* 14, 15 */ 0, 0, \
|
||||
+/* EF_SHJ2 */ bfd_mach_shj2 , \
|
||||
+/* 15 */ 0, \
|
||||
/* EF_SH4_NOFPU */ bfd_mach_sh4_nofpu , \
|
||||
/* EF_SH4A_NOFPU */ bfd_mach_sh4a_nofpu , \
|
||||
/* EF_SH4_NOMMU_NOFPU */ bfd_mach_sh4_nommu_nofpu, \
|
||||
@@ -81,7 +84,8 @@
|
||||
/* EF_SH2A_SH4_NOFPU */ bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu, \
|
||||
/* EF_SH2A_SH3_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu, \
|
||||
/* EF_SH2A_SH4 */ bfd_mach_sh2a_or_sh4 , \
|
||||
-/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e
|
||||
+/* EF_SH2A_SH3E */ bfd_mach_sh2a_or_sh3e, \
|
||||
+/* EF_SH2A_SH3_SHJ2_NOFPU */ bfd_mach_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu
|
||||
|
||||
/* Convert arch_sh* into EF_SH*. */
|
||||
int sh_find_elf_flags (unsigned int arch_set);
|
||||
diff -ur binutils-2.32.orig/opcodes/sh-dis.c binutils-2.32/opcodes/sh-dis.c
|
||||
--- binutils-2.32.orig/opcodes/sh-dis.c 2019-01-19 11:01:34.000000000 -0500
|
||||
+++ binutils-2.32/opcodes/sh-dis.c 2019-05-26 15:07:03.593950688 -0400
|
||||
@@ -856,6 +856,9 @@
|
||||
case XMTRX_M4:
|
||||
fprintf_fn (stream, "xmtrx");
|
||||
break;
|
||||
+ case A_IND_0:
|
||||
+ fprintf_fn (stream, "@r0");
|
||||
+ break;
|
||||
default:
|
||||
abort ();
|
||||
}
|
||||
Only in binutils-2.32/opcodes: sh-dis.c.orig
|
||||
diff -ur binutils-2.32.orig/opcodes/sh-opc.h binutils-2.32/opcodes/sh-opc.h
|
||||
--- binutils-2.32.orig/opcodes/sh-opc.h 2019-01-19 11:01:34.000000000 -0500
|
||||
+++ binutils-2.32/opcodes/sh-opc.h 2019-05-26 15:07:03.597950705 -0400
|
||||
@@ -191,7 +191,8 @@
|
||||
FPUL_N,
|
||||
FPUL_M,
|
||||
FPSCR_N,
|
||||
- FPSCR_M
|
||||
+ FPSCR_M,
|
||||
+ A_IND_0
|
||||
}
|
||||
sh_arg_type;
|
||||
|
||||
@@ -215,9 +216,11 @@
|
||||
#define arch_sh4_base (1 << 5)
|
||||
#define arch_sh4a_base (1 << 6)
|
||||
#define arch_sh2a_base (1 << 7)
|
||||
-#define arch_sh_base_mask MASK (0, 7)
|
||||
+#define arch_shj2_base (1 << 8)
|
||||
+#define arch_sh2a_sh3_shj2_base (1 << 9)
|
||||
+#define arch_sh_base_mask MASK (0, 9)
|
||||
|
||||
-/* Bits 8 ... 24 are currently free. */
|
||||
+/* Bits 10 ... 24 are currently free. */
|
||||
|
||||
/* This is an annotation on instruction types, but we
|
||||
abuse the arch field in instructions to denote it. */
|
||||
@@ -255,6 +258,8 @@
|
||||
#define arch_sh2a_nofpu_or_sh3_nommu (arch_sh2a_sh3_base|arch_sh_no_mmu |arch_sh_no_co)
|
||||
#define arch_sh2a_or_sh3e (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_sp_fpu)
|
||||
#define arch_sh2a_or_sh4 (arch_sh2a_sh4_base|arch_sh_no_mmu |arch_sh_dp_fpu)
|
||||
+#define arch_shj2 (arch_shj2_base |arch_sh_no_mmu |arch_sh_no_co)
|
||||
+#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu (arch_sh2a_sh3_shj2_base|arch_sh_no_mmu |arch_sh_no_co)
|
||||
|
||||
#define SH_MERGE_ARCH_SET(SET1, SET2) ((SET1) & (SET2))
|
||||
#define SH_VALID_BASE_ARCH_SET(SET) (((SET) & arch_sh_base_mask) != 0)
|
||||
@@ -319,7 +324,8 @@
|
||||
#define arch_sh2_up (arch_sh2 \
|
||||
| arch_sh2e_up \
|
||||
| arch_sh2a_nofpu_or_sh3_nommu_up \
|
||||
- | arch_sh_dsp_up)
|
||||
+ | arch_sh_dsp_up \
|
||||
+ | arch_shj2_up)
|
||||
#define arch_sh2a_nofpu_or_sh3_nommu_up (arch_sh2a_nofpu_or_sh3_nommu \
|
||||
| arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \
|
||||
| arch_sh2a_or_sh3e_up \
|
||||
@@ -345,6 +351,12 @@
|
||||
#define arch_sh4a_nofpu_up (arch_sh4a_nofpu \
|
||||
| arch_sh4a_up \
|
||||
| arch_sh4al_dsp_up)
|
||||
+#define arch_shj2_up ( arch_shj2)
|
||||
+#define arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up (arch_sh2a_nofpu_or_sh3_nommu \
|
||||
+ | arch_sh2a_nofpu_or_sh4_nommu_nofpu_up \
|
||||
+ | arch_sh2a_or_sh3e_up \
|
||||
+ | arch_sh3_nommu_up \
|
||||
+ | arch_shj2_up)
|
||||
|
||||
/* Right branches. */
|
||||
#define arch_sh2e_up (arch_sh2e \
|
||||
@@ -713,9 +725,9 @@
|
||||
|
||||
/* repeat start end #<imm> */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up},
|
||||
|
||||
-/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_up},
|
||||
+/* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up},
|
||||
|
||||
-/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_up},
|
||||
+/* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh2a_nofpu_or_sh3_nommu_or_shj2_nofpu_up},
|
||||
|
||||
/* 0100nnnn00100000 shal <REG_N> */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh_up},
|
||||
|
||||
@@ -1193,7 +1205,7 @@
|
||||
{"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32},
|
||||
/* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */
|
||||
{"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32},
|
||||
-
|
||||
+ /* 0010nnnnmmmm0011 cas.l Rm,Rn,@R0 */ {"cas.l", { A_REG_M,A_REG_N,A_IND_0},{HEX_2,REG_N,REG_M,HEX_3}, arch_shj2_up},
|
||||
{ 0, {0}, {0}, 0 }
|
||||
};
|
||||
|
||||
Only in binutils-2.32/opcodes: sh-opc.h.orig
|
||||
@ -1,249 +0,0 @@
|
||||
From: Stafford Horne <shorne@gmail.com>
|
||||
To: GNU Binutils <binutils@sourceware.org>
|
||||
Cc: Openrisc <openrisc@lists.librecores.org>, dalias@libc.org, Stafford Horne <shorne@gmail.com>
|
||||
Subject: [PATCH 1/2] or1k: Remove 64-bit support, it's not used and it breaks 32-bit hosts
|
||||
Date: Wed, 11 Dec 2019 06:49:05 +0900
|
||||
|
||||
Reported by Rich Felker when building on 32-bit hosts. Backwards jump
|
||||
negative offsets were not calculated correctly due to improper 32-bit
|
||||
to 64-bit zero-extension. The 64-bit fields are present because we
|
||||
are mixing 32-bit and 64-bit architectures in our cpu descriptions.
|
||||
|
||||
Removing 64-bit fixes the issue. We don't use 64-bit, there is an architecture
|
||||
spec for 64-bit but no implementations or simulators. My thought is if
|
||||
we need them in the future we should do the proper work to support both
|
||||
32-bit and 64-bit implementations co-existing then.
|
||||
|
||||
cpu/ChangeLog:
|
||||
|
||||
yyyy-mm-dd Stafford Horne <shorne@gmail.com>
|
||||
|
||||
PR 25184
|
||||
* or1k.cpu (arch or1k): Remove or64 and or64nd machs.
|
||||
(ORBIS-MACHS, ORFPX32-MACHS): Remove pmacros.
|
||||
(cpu or1k64bf, mach or64, mach or64nd): Remove definitions.
|
||||
* or1kcommon.cpu (h-fdr): Remove hardware.
|
||||
* or1korfpx.cpu (rDDF, rADF, rBDF): Remove operand definitions.
|
||||
(float-regreg-insn): Remove lf- mnemonic -d instruction pattern.
|
||||
(float-setflag-insn-base): Remove lf-sf mnemonic -d pattern.
|
||||
(float-cust-insn): Remove "lf-cust" cust-num "-d" pattern.
|
||||
(lf-rem-d, lf-itof-d, lf-ftoi-d, lf-madd-d): Remove.
|
||||
---
|
||||
cpu/or1k.cpu | 35 +++----------------------
|
||||
cpu/or1kcommon.cpu | 14 ----------
|
||||
cpu/or1korfpx.cpu | 64 ----------------------------------------------
|
||||
3 files changed, 3 insertions(+), 110 deletions(-)
|
||||
|
||||
diff --git a/cpu/or1k.cpu b/cpu/or1k.cpu
|
||||
index b796862d1b..9784f7a0fa 100644
|
||||
--- a/cpu/or1k.cpu
|
||||
+++ b/cpu/or1k.cpu
|
||||
@@ -31,7 +31,7 @@
|
||||
(comment "OpenRISC 1000")
|
||||
(default-alignment aligned)
|
||||
(insn-lsb0? #t)
|
||||
- (machs or32 or32nd or64 or64nd)
|
||||
+ (machs or32 or32nd)
|
||||
(isas openrisc)
|
||||
)
|
||||
|
||||
@@ -44,10 +44,8 @@
|
||||
)
|
||||
|
||||
(define-pmacro OR32-MACHS or32,or32nd)
|
||||
-(define-pmacro OR64-MACHS or64,or64nd)
|
||||
-(define-pmacro ORBIS-MACHS or32,or32nd,or64,or64nd)
|
||||
-(define-pmacro ORFPX32-MACHS or32,or32nd,or64,or64nd)
|
||||
-(define-pmacro ORFPX64-MACHS or64,or64nd)
|
||||
+(define-pmacro ORBIS-MACHS or32,or32nd)
|
||||
+(define-pmacro ORFPX32-MACHS or32,or32nd)
|
||||
(define-pmacro ORFPX64A32-MACHS or32,or32nd) ; float64 for 32-bit machs
|
||||
|
||||
(define-attr
|
||||
@@ -100,33 +98,6 @@
|
||||
)
|
||||
)
|
||||
|
||||
-(if (keep-mach? (or64 or64nd))
|
||||
- (begin
|
||||
- (define-cpu
|
||||
- (name or1k64bf)
|
||||
- (comment "OpenRISC 1000 64-bit CPU family")
|
||||
- (insn-endian big)
|
||||
- (data-endian big)
|
||||
- (word-bitsize 64)
|
||||
- (file-transform "64")
|
||||
- )
|
||||
-
|
||||
- (define-mach
|
||||
- (name or64)
|
||||
- (comment "Generic OpenRISC 1000 64-bit CPU")
|
||||
- (cpu or1k64bf)
|
||||
- (bfd-name "or1k64")
|
||||
- )
|
||||
-
|
||||
- (define-mach
|
||||
- (name or64nd)
|
||||
- (comment "Generic OpenRISC 1000 ND 64-bit CPU with no branch delay slot")
|
||||
- (cpu or1k64bf)
|
||||
- (bfd-name "or1k64nd")
|
||||
- )
|
||||
- )
|
||||
- )
|
||||
-
|
||||
(include "or1kcommon.cpu")
|
||||
(include "or1korbis.cpu")
|
||||
(include "or1korfpx.cpu")
|
||||
diff --git a/cpu/or1kcommon.cpu b/cpu/or1kcommon.cpu
|
||||
index 65154407df..9f102c93a1 100644
|
||||
--- a/cpu/or1kcommon.cpu
|
||||
+++ b/cpu/or1kcommon.cpu
|
||||
@@ -114,20 +114,6 @@
|
||||
(set (index newval) (set UWI (reg h-gpr index) (zext UWI (subword SI newval 0))))
|
||||
)
|
||||
|
||||
-;
|
||||
-; Hardware: virtual registerts for FPU (double precision)
|
||||
-; mapped to GPRs
|
||||
-;
|
||||
-(define-hardware
|
||||
- (name h-fdr)
|
||||
- (comment "or64 floating point registers (double, virtual)")
|
||||
- (attrs VIRTUAL (MACH ORFPX64-MACHS))
|
||||
- (type register DF (32))
|
||||
- (indices keyword "" REG-INDICES)
|
||||
- (get (index) (subword DF (trunc DI (reg h-gpr index)) 0))
|
||||
- (set (index newval) (set UDI (reg h-gpr index) (zext UDI (subword DI newval 0))))
|
||||
- )
|
||||
-
|
||||
;
|
||||
; Register pairs are offset by 2 for registers r16 and above. This is to
|
||||
; be able to allow registers to be call saved in GCC across function calls.
|
||||
diff --git a/cpu/or1korfpx.cpu b/cpu/or1korfpx.cpu
|
||||
index f43522f2e6..0bd469cff5 100644
|
||||
--- a/cpu/or1korfpx.cpu
|
||||
+++ b/cpu/or1korfpx.cpu
|
||||
@@ -84,10 +84,6 @@
|
||||
(dnop rASF "source register A (single floating point mode)" ((MACH ORFPX32-MACHS)) h-fsr f-r2)
|
||||
(dnop rBSF "source register B (single floating point mode)" ((MACH ORFPX32-MACHS)) h-fsr f-r3)
|
||||
|
||||
-(dnop rDDF "or64 destination register (double floating point mode)" ((MACH ORFPX64-MACHS)) h-fdr f-r1)
|
||||
-(dnop rADF "or64 source register A (double floating point mode)" ((MACH ORFPX64-MACHS)) h-fdr f-r2)
|
||||
-(dnop rBDF "or64 source register B (double floating point mode)" ((MACH ORFPX64-MACHS)) h-fdr f-r3)
|
||||
-
|
||||
(define-pmacro (double-field-and-ops mnemonic reg offbit op-comment)
|
||||
(begin
|
||||
(define-multi-ifield
|
||||
@@ -152,14 +148,6 @@
|
||||
(set SF rDSF (mnemonic SF rASF rBSF))
|
||||
()
|
||||
)
|
||||
- (dni (.sym lf- mnemonic -d)
|
||||
- (.str "lf." mnemonic ".d reg/reg/reg")
|
||||
- ((MACH ORFPX64-MACHS))
|
||||
- (.str "lf." mnemonic ".d $rDDF,$rADF,$rBDF")
|
||||
- (+ OPC_FLOAT rDDF rADF rBDF (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_ (.upcase mnemonic) _D))
|
||||
- (set DF rDDF (mnemonic DF rADF rBDF))
|
||||
- ()
|
||||
- )
|
||||
(dni (.sym lf- mnemonic -d32)
|
||||
(.str "lf." mnemonic ".d regpair/regpair/regpair")
|
||||
((MACH ORFPX64A32-MACHS))
|
||||
@@ -185,15 +173,6 @@
|
||||
()
|
||||
)
|
||||
|
||||
-(dni lf-rem-d
|
||||
- "lf.rem.d reg/reg/reg"
|
||||
- ((MACH ORFPX64-MACHS))
|
||||
- "lf.rem.d $rDDF,$rADF,$rBDF"
|
||||
- (+ OPC_FLOAT rDDF rADF rBDF (f-resv-10-3 0) OPC_FLOAT_REGREG_REM_D)
|
||||
- (set DF rDDF (rem DF rADF rBDF))
|
||||
- ()
|
||||
- )
|
||||
-
|
||||
(dni lf-rem-d32
|
||||
"lf.rem.d regpair/regpair/regpair"
|
||||
((MACH ORFPX64A32-MACHS))
|
||||
@@ -221,15 +200,6 @@
|
||||
()
|
||||
)
|
||||
|
||||
-(dni lf-itof-d
|
||||
- "lf.itof.d reg/reg"
|
||||
- ((MACH ORFPX64-MACHS))
|
||||
- "lf.itof.d $rDDF,$rA"
|
||||
- (+ OPC_FLOAT rDDF rA (f-r3 0) (f-resv-10-3 0) OPC_FLOAT_REGREG_ITOF_D)
|
||||
- (set DF rDDF (float DF (get-rounding-mode) rA))
|
||||
- ()
|
||||
- )
|
||||
-
|
||||
(dni lf-itof-d32
|
||||
"lf.itof.d regpair/regpair"
|
||||
((MACH ORFPX64A32-MACHS))
|
||||
@@ -248,15 +218,6 @@
|
||||
()
|
||||
)
|
||||
|
||||
-(dni lf-ftoi-d
|
||||
- "lf.ftoi.d reg/reg"
|
||||
- ((MACH ORFPX64-MACHS))
|
||||
- "lf.ftoi.d $rD,$rADF"
|
||||
- (+ OPC_FLOAT rD rADF (f-r3 0) (f-resv-10-3 0) OPC_FLOAT_REGREG_FTOI_D)
|
||||
- (set WI rD (fix WI (get-rounding-mode) rADF))
|
||||
- ()
|
||||
- )
|
||||
-
|
||||
(dni lf-ftoi-d32
|
||||
"lf.ftoi.d regpair/regpair"
|
||||
((MACH ORFPX64A32-MACHS))
|
||||
@@ -276,14 +237,6 @@
|
||||
(symantics rtx-mnemonic SF rASF rBSF)
|
||||
()
|
||||
)
|
||||
- (dni (.sym lf-sf mnemonic -d)
|
||||
- (.str "lf.sf" mnemonic ".d reg/reg")
|
||||
- ((MACH ORFPX64-MACHS))
|
||||
- (.str "lf.sf" mnemonic ".d $rADF,$rBDF")
|
||||
- (+ OPC_FLOAT (f-r1 0) rADF rBDF (f-resv-10-3 0) (.sym OPC_FLOAT_REGREG_SF (.upcase mnemonic) _D))
|
||||
- (symantics rtx-mnemonic DF rADF rBDF)
|
||||
- ()
|
||||
- )
|
||||
(dni (.sym lf-sf mnemonic -d32)
|
||||
(.str "lf.sf" mnemonic ".d regpair/regpair")
|
||||
((MACH ORFPX64A32-MACHS))
|
||||
@@ -336,15 +289,6 @@
|
||||
()
|
||||
)
|
||||
|
||||
-(dni lf-madd-d
|
||||
- "lf.madd.d reg/reg/reg"
|
||||
- ((MACH ORFPX64-MACHS))
|
||||
- "lf.madd.d $rDDF,$rADF,$rBDF"
|
||||
- (+ OPC_FLOAT rDDF rADF rBDF (f-resv-10-3 0) OPC_FLOAT_REGREG_MADD_D)
|
||||
- (set DF rDDF (add DF (mul DF rADF rBDF) rDDF))
|
||||
- ()
|
||||
- )
|
||||
-
|
||||
(dni lf-madd-d32
|
||||
"lf.madd.d regpair/regpair/regpair"
|
||||
((MACH ORFPX64A32-MACHS))
|
||||
@@ -364,14 +308,6 @@
|
||||
(nop)
|
||||
()
|
||||
)
|
||||
- (dni (.sym "lf-cust" cust-num "-d")
|
||||
- (.str "lf.cust" cust-num ".d")
|
||||
- ((MACH ORFPX64-MACHS))
|
||||
- (.str "lf.cust" cust-num ".d")
|
||||
- (+ OPC_FLOAT (f-resv-25-5 0) rADF rBDF (f-resv-10-3 0) (.sym "OPC_FLOAT_REGREG_CUST" cust-num "_D"))
|
||||
- (nop)
|
||||
- ()
|
||||
- )
|
||||
(dni (.sym "lf-cust" cust-num "-d32")
|
||||
(.str "lf.cust" cust-num ".d")
|
||||
((MACH ORFPX64A32-MACHS))
|
||||
--
|
||||
2.21.0
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,55 +0,0 @@
|
||||
From: Szabolcs Nagy <szabolcs.nagy@arm.com>
|
||||
Date: Thu, 9 Jan 2020 17:20:56 +0000 (+0000)
|
||||
Subject: [PR ld/22269] arm: Avoid dynamic relocs for undefweak symbols in static PIE
|
||||
X-Git-Url: https://sourceware.org/git/gitweb.cgi?p=binutils-gdb.git;a=commitdiff_plain;h=6fbcfe4762c3732339cffd82426d00d35382b858;hp=c06868784d819a45c43947180c69e168aecaf368
|
||||
|
||||
[PR ld/22269] arm: Avoid dynamic relocs for undefweak symbols in static PIE
|
||||
|
||||
With static PIE linking undefined weak symbols are resolved to 0, so no
|
||||
dynamic relocation is needed for them. The UNDEFWEAK_NO_DYNAMIC_RELOC
|
||||
macro was introduced so this case can be handled easily, but it was not
|
||||
applied consistently in the first attempt to fix ld/22269 for arm:
|
||||
|
||||
commit 95b03e4ad68e7a90f5096b47df595636344b783a
|
||||
arm: Check UNDEFWEAK_NO_DYNAMIC_RELOC
|
||||
|
||||
This patch fixes spurious relative relocs in static PIE binaries against
|
||||
GOT entries created for undefined weak symbols on arm*-*, this fixes
|
||||
|
||||
FAIL: pr22269-1 (static pie undefined weak)
|
||||
|
||||
bfd/ChangeLog:
|
||||
|
||||
Backported from master
|
||||
2020-01-10 Szabolcs Nagy <szabolcs.nagy@arm.com>
|
||||
|
||||
PR ld/22269
|
||||
* elf32-arm.c (elf32_arm_final_link_relocate): Use
|
||||
UNDEFWEAK_NO_DYNAMIC_RELOC.
|
||||
(allocate_dynrelocs_for_symbol): Likewise.
|
||||
---
|
||||
|
||||
diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c
|
||||
index cce796d..21cf4b0 100644
|
||||
--- a/bfd/elf32-arm.c
|
||||
+++ b/bfd/elf32-arm.c
|
||||
@@ -11572,8 +11572,7 @@ elf32_arm_final_link_relocate (reloc_howto_type * howto,
|
||||
if (dynreloc_st_type == STT_GNU_IFUNC)
|
||||
outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
|
||||
else if (bfd_link_pic (info)
|
||||
- && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
|
||||
- || h->root.type != bfd_link_hash_undefweak))
|
||||
+ && !UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
|
||||
outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
|
||||
else
|
||||
{
|
||||
@@ -16527,8 +16526,7 @@ allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
|
||||
GOT entry's R_ARM_IRELATIVE relocation. */
|
||||
elf32_arm_allocate_irelocs (info, htab->root.srelgot, 1);
|
||||
else if (bfd_link_pic (info)
|
||||
- && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
|
||||
- || h->root.type != bfd_link_hash_undefweak))
|
||||
+ && !UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
|
||||
/* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
|
||||
elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
|
||||
else if (htab->fdpic_p && tls_type == GOT_NORMAL)
|
||||
@ -1,33 +0,0 @@
|
||||
--- binutils-2.33.1/bfd/elf32-sh.c.orig 2024-04-04 23:11:28.739136261 +0900
|
||||
+++ binutils-2.33.1/bfd/elf32-sh.c 2024-04-08 23:14:24.496915074 +0900
|
||||
@@ -61,7 +61,7 @@
|
||||
not. If the symbol is protected, we want the local address, but
|
||||
its function descriptor must be assigned by the dynamic linker. */
|
||||
#define SYMBOL_FUNCDESC_LOCAL(INFO, H) \
|
||||
- (SYMBOL_REFERENCES_LOCAL (INFO, H) \
|
||||
+ (!(H) || (H)->dynindx < 0 || (H)->forced_local \
|
||||
|| ! elf_hash_table (INFO)->dynamic_sections_created)
|
||||
|
||||
#define SH_PARTIAL32 TRUE
|
||||
@@ -4405,20 +4405,6 @@
|
||||
/* Undefined weak symbol which will not be dynamically
|
||||
resolved later; leave it at zero. */
|
||||
goto funcdesc_leave_zero;
|
||||
- else if (SYMBOL_CALLS_LOCAL (info, h)
|
||||
- && ! SYMBOL_FUNCDESC_LOCAL (info, h))
|
||||
- {
|
||||
- /* If the symbol needs a non-local function descriptor
|
||||
- but binds locally (i.e., its visibility is
|
||||
- protected), emit a dynamic relocation decayed to
|
||||
- section+offset. This is an optimization; the dynamic
|
||||
- linker would resolve our function descriptor request
|
||||
- to our copy of the function anyway. */
|
||||
- dynindx = elf_section_data (h->root.u.def.section
|
||||
- ->output_section)->dynindx;
|
||||
- relocation += h->root.u.def.section->output_offset
|
||||
- + h->root.u.def.value;
|
||||
- }
|
||||
else if (! SYMBOL_FUNCDESC_LOCAL (info, h))
|
||||
{
|
||||
/* If the symbol is dynamic and there will be dynamic
|
||||
|
||||
@ -1,14 +0,0 @@
|
||||
diff --git a/gcc/gcc.c b/gcc/gcc.c
|
||||
index 9f790db0daf..e6887590ae2 100644
|
||||
--- a/gcc/gcc.c
|
||||
+++ b/gcc/gcc.c
|
||||
@@ -877,7 +877,8 @@ proper position among the other output files. */
|
||||
#ifndef LINK_SSP_SPEC
|
||||
#ifdef TARGET_LIBC_PROVIDES_SSP
|
||||
#define LINK_SSP_SPEC "%{fstack-protector|fstack-protector-all" \
|
||||
- "|fstack-protector-strong|fstack-protector-explicit:}"
|
||||
+ "|fstack-protector-strong|fstack-protector-explicit" \
|
||||
+ ":-lssp_nonshared}"
|
||||
#else
|
||||
#define LINK_SSP_SPEC "%{fstack-protector|fstack-protector-all" \
|
||||
"|fstack-protector-strong|fstack-protector-explicit" \
|
||||
@ -1,92 +0,0 @@
|
||||
diff --git a/gcc/common.opt b/gcc/common.opt
|
||||
index ec5235c3a41..dcee05500ba 100644
|
||||
--- a/gcc/common.opt
|
||||
+++ b/gcc/common.opt
|
||||
@@ -3401,11 +3401,11 @@ Driver
|
||||
|
||||
no-pie
|
||||
Driver RejectNegative Negative(shared)
|
||||
-Don't create a dynamically linked position independent executable.
|
||||
+Don't create a position independent executable.
|
||||
|
||||
pie
|
||||
Driver RejectNegative Negative(no-pie)
|
||||
-Create a dynamically linked position independent executable.
|
||||
+Create a position independent executable.
|
||||
|
||||
static-pie
|
||||
Driver RejectNegative Negative(pie)
|
||||
diff --git a/gcc/config/gnu-user.h b/gcc/config/gnu-user.h
|
||||
index ff2e880b1fa..bafde149202 100644
|
||||
--- a/gcc/config/gnu-user.h
|
||||
+++ b/gcc/config/gnu-user.h
|
||||
@@ -51,13 +51,12 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
|
||||
#define GNU_USER_TARGET_STARTFILE_SPEC \
|
||||
"%{shared:; \
|
||||
pg|p|profile:%{static-pie:grcrt1.o%s;:gcrt1.o%s}; \
|
||||
- static:crt1.o%s; \
|
||||
- static-pie:rcrt1.o%s; \
|
||||
+ static|static-pie:%{" PIE_SPEC ":rcrt1.o%s;:crt1.o%s}; \
|
||||
" PIE_SPEC ":Scrt1.o%s; \
|
||||
:crt1.o%s} " \
|
||||
GNU_USER_TARGET_CRTI " \
|
||||
- %{static:crtbeginT.o%s; \
|
||||
- shared|static-pie|" PIE_SPEC ":crtbeginS.o%s; \
|
||||
+ %{shared|" PIE_SPEC ":crtbeginS.o%s; \
|
||||
+ static:crtbeginT.o%s; \
|
||||
:crtbegin.o%s} \
|
||||
%{fvtable-verify=none:%s; \
|
||||
fvtable-verify=preinit:vtv_start_preinit.o%s; \
|
||||
@@ -73,11 +72,11 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
|
||||
GNU userspace "finalizer" file, `crtn.o'. */
|
||||
|
||||
#define GNU_USER_TARGET_ENDFILE_SPEC \
|
||||
- "%{!static:%{fvtable-verify=none:%s; \
|
||||
+ "%{static|static-pie:; \
|
||||
+ fvtable-verify=none:%s; \
|
||||
fvtable-verify=preinit:vtv_end_preinit.o%s; \
|
||||
- fvtable-verify=std:vtv_end.o%s}} \
|
||||
- %{static:crtend.o%s; \
|
||||
- shared|static-pie|" PIE_SPEC ":crtendS.o%s; \
|
||||
+ fvtable-verify=std:vtv_end.o%s} \
|
||||
+ %{shared|" PIE_SPEC ":crtendS.o%s; \
|
||||
:crtend.o%s} " \
|
||||
GNU_USER_TARGET_CRTN " " \
|
||||
CRTOFFLOADEND
|
||||
@@ -106,7 +105,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
|
||||
#define LIB_SPEC GNU_USER_TARGET_LIB_SPEC
|
||||
|
||||
#if defined(HAVE_LD_EH_FRAME_HDR)
|
||||
-#define LINK_EH_SPEC "%{!static|static-pie:--eh-frame-hdr} "
|
||||
+#define LINK_EH_SPEC "%{!static|" PIE_SPEC ":--eh-frame-hdr} "
|
||||
#endif
|
||||
|
||||
#define GNU_USER_TARGET_LINK_GCC_C_SEQUENCE_SPEC \
|
||||
diff --git a/gcc/gcc.c b/gcc/gcc.c
|
||||
index e6887590ae2..df6e3965f13 100644
|
||||
--- a/gcc/gcc.c
|
||||
+++ b/gcc/gcc.c
|
||||
@@ -907,7 +907,7 @@ proper position among the other output files. */
|
||||
#define NO_FPIE_AND_FPIC_SPEC NO_FPIE_SPEC "|" NO_FPIC_SPEC
|
||||
#define FPIE_OR_FPIC_SPEC NO_FPIE_AND_FPIC_SPEC ":;"
|
||||
#else
|
||||
-#define PIE_SPEC "pie"
|
||||
+#define PIE_SPEC "pie|static-pie"
|
||||
#define FPIE1_SPEC "fpie"
|
||||
#define NO_FPIE1_SPEC FPIE1_SPEC ":;"
|
||||
#define FPIE2_SPEC "fPIE"
|
||||
@@ -931,12 +931,12 @@ proper position among the other output files. */
|
||||
#ifndef LINK_PIE_SPEC
|
||||
#ifdef HAVE_LD_PIE
|
||||
#ifndef LD_PIE_SPEC
|
||||
-#define LD_PIE_SPEC "-pie"
|
||||
+#define LD_PIE_SPEC "-pie %{static|static-pie:--no-dynamic-linker -z text -Bsymbolic}"
|
||||
#endif
|
||||
#else
|
||||
#define LD_PIE_SPEC ""
|
||||
#endif
|
||||
-#define LINK_PIE_SPEC "%{static|shared|r:;" PIE_SPEC ":" LD_PIE_SPEC "} "
|
||||
+#define LINK_PIE_SPEC "%{shared|r:;" PIE_SPEC ":" LD_PIE_SPEC "} "
|
||||
#endif
|
||||
|
||||
#ifndef LINK_BUILDID_SPEC
|
||||
@ -1,30 +0,0 @@
|
||||
diff --git a/libstdc++-v3/src/c++11/futex.cc b/libstdc++-v3/src/c++11/futex.cc
|
||||
index 698737d9b21..230d32574c6 100644
|
||||
--- a/libstdc++-v3/src/c++11/futex.cc
|
||||
+++ b/libstdc++-v3/src/c++11/futex.cc
|
||||
@@ -46,13 +46,23 @@ _GLIBCXX_BEGIN_NAMESPACE_VERSION
|
||||
|
||||
namespace
|
||||
{
|
||||
+#if defined(SYS_futex_time64) && SYS_futex_time64 != SYS_futex
|
||||
+ typedef struct
|
||||
+ {
|
||||
+ long tv_sec;
|
||||
+ long tv_nsec;
|
||||
+ } sys_timespec;
|
||||
+#else
|
||||
+ typedef struct timespec sys_timespec;
|
||||
+#endif
|
||||
+
|
||||
// Return the relative duration from (now_s + now_ns) to (abs_s + abs_ns)
|
||||
// as a timespec.
|
||||
- struct timespec
|
||||
+ sys_timespec
|
||||
relative_timespec(chrono::seconds abs_s, chrono::nanoseconds abs_ns,
|
||||
time_t now_s, long now_ns)
|
||||
{
|
||||
- struct timespec rt;
|
||||
+ sys_timespec rt;
|
||||
|
||||
// Did we already time out?
|
||||
if (now_s > abs_s.count())
|
||||
@ -1,20 +0,0 @@
|
||||
diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md
|
||||
index 8e35357ea23..65c8b10b3eb 100644
|
||||
--- a/gcc/config/m68k/m68k.md
|
||||
+++ b/gcc/config/m68k/m68k.md
|
||||
@@ -4174,13 +4174,13 @@
|
||||
(define_expand "sqrt<mode>2"
|
||||
[(set (match_operand:FP 0 "nonimmediate_operand" "")
|
||||
(sqrt:FP (match_operand:FP 1 "general_operand" "")))]
|
||||
- "TARGET_HARD_FLOAT"
|
||||
+ "(TARGET_68881 && TARGET_68040) || TARGET_COLDFIRE_FPU"
|
||||
"")
|
||||
|
||||
(define_insn "sqrt<mode>2_68881"
|
||||
[(set (match_operand:FP 0 "nonimmediate_operand" "=f")
|
||||
(sqrt:FP (match_operand:FP 1 "general_operand" "f<FP:dreg>m")))]
|
||||
- "TARGET_68881"
|
||||
+ "TARGET_68881 && TARGET_68040"
|
||||
{
|
||||
if (FP_REG_P (operands[1]))
|
||||
return "f<FP:round>sqrt%.x %1,%0";
|
||||
@ -1,11 +0,0 @@
|
||||
--- a/libgcc/unwind-pe.h 2024-03-14 05:59:53.754073149 +0900
|
||||
+++ b/libgcc/unwind-pe.h 2024-03-14 06:00:41.226074492 +0900
|
||||
@@ -262,7 +262,7 @@
|
||||
|
||||
if (result != 0)
|
||||
{
|
||||
-#if __FDPIC__
|
||||
+#if __FDPIC__ && __arm__
|
||||
/* FDPIC relative addresses imply taking the GOT address
|
||||
into account. */
|
||||
if ((encoding & DW_EH_PE_pcrel) && (encoding & DW_EH_PE_indirect))
|
||||
@ -1,38 +0,0 @@
|
||||
--- a/libgcc/crtstuff.c 2023-05-29 17:46:32.000000000 +0900
|
||||
+++ b/libgcc/crtstuff.c 2024-03-14 06:03:42.398079615 +0900
|
||||
@@ -441,17 +441,9 @@
|
||||
#ifdef FINI_SECTION_ASM_OP
|
||||
CRT_CALL_STATIC_FUNCTION (FINI_SECTION_ASM_OP, __do_global_dtors_aux)
|
||||
#elif defined (FINI_ARRAY_SECTION_ASM_OP)
|
||||
-#if defined(__FDPIC__)
|
||||
-__asm__("\t.equ\t__do_global_dtors_aux_alias, __do_global_dtors_aux\n");
|
||||
-extern char __do_global_dtors_aux_alias;
|
||||
-static void *__do_global_dtors_aux_fini_array_entry[]
|
||||
-__attribute__ ((__used__, section(".fini_array"), aligned(sizeof(void *))))
|
||||
- = { &__do_global_dtors_aux_alias };
|
||||
-#else /* defined(__FDPIC__) */
|
||||
static func_ptr __do_global_dtors_aux_fini_array_entry[]
|
||||
__attribute__ ((__used__, section(".fini_array"),
|
||||
aligned(__alignof__(func_ptr)))) = { __do_global_dtors_aux };
|
||||
-#endif /* defined(__FDPIC__) */
|
||||
#else /* !FINI_SECTION_ASM_OP && !FINI_ARRAY_SECTION_ASM_OP */
|
||||
static void __attribute__((used))
|
||||
__do_global_dtors_aux_1 (void)
|
||||
@@ -494,17 +486,9 @@
|
||||
#ifdef __LIBGCC_INIT_SECTION_ASM_OP__
|
||||
CRT_CALL_STATIC_FUNCTION (__LIBGCC_INIT_SECTION_ASM_OP__, frame_dummy)
|
||||
#else /* defined(__LIBGCC_INIT_SECTION_ASM_OP__) */
|
||||
-#if defined(__FDPIC__)
|
||||
-__asm__("\t.equ\t__frame_dummy_alias, frame_dummy\n");
|
||||
-extern char __frame_dummy_alias;
|
||||
-static void *__frame_dummy_init_array_entry[]
|
||||
-__attribute__ ((__used__, section(".init_array"), aligned(sizeof(void *))))
|
||||
- = { &__frame_dummy_alias };
|
||||
-#else /* defined(__FDPIC__) */
|
||||
static func_ptr __frame_dummy_init_array_entry[]
|
||||
__attribute__ ((__used__, section(".init_array"),
|
||||
aligned(__alignof__(func_ptr)))) = { frame_dummy };
|
||||
-#endif /* defined(__FDPIC__) */
|
||||
#endif /* !defined(__LIBGCC_INIT_SECTION_ASM_OP__) */
|
||||
#endif /* USE_EH_FRAME_REGISTRY || USE_TM_CLONE_REGISTRY */
|
||||
|
||||
@ -1,12 +0,0 @@
|
||||
--- gcc-11.4.0/gcc/config/sh/sh.c.orig 2024-04-04 05:52:42.125373614 +0900
|
||||
+++ gcc-11.4.0/gcc/config/sh/sh.c 2024-04-04 22:54:01.875106654 +0900
|
||||
@@ -9147,7 +9147,7 @@
|
||||
{
|
||||
/* Weak functions may be NULL which doesn't work with
|
||||
GOTOFFFUNCDESC because the runtime offset is not known. */
|
||||
- if (SYMBOL_REF_WEAK (orig))
|
||||
+ if (SYMBOL_REF_WEAK (orig) || (TREE_PUBLIC(SYMBOL_REF_DECL(orig)) && DECL_VISIBILITY (SYMBOL_REF_DECL(orig)) != VISIBILITY_HIDDEN))
|
||||
emit_insn (gen_symGOTFUNCDESC2reg (reg, orig));
|
||||
else
|
||||
emit_insn (gen_symGOTOFFFUNCDESC2reg (reg, orig));
|
||||
|
||||
@ -1,14 +0,0 @@
|
||||
diff --git a/gcc/gcc.c b/gcc/gcc.c
|
||||
index 7837553958b..3c81c5798d8 100644
|
||||
--- a/gcc/gcc.c
|
||||
+++ b/gcc/gcc.c
|
||||
@@ -980,7 +980,8 @@ proper position among the other output files. */
|
||||
#ifndef LINK_SSP_SPEC
|
||||
#ifdef TARGET_LIBC_PROVIDES_SSP
|
||||
#define LINK_SSP_SPEC "%{fstack-protector|fstack-protector-all" \
|
||||
- "|fstack-protector-strong|fstack-protector-explicit:}"
|
||||
+ "|fstack-protector-strong|fstack-protector-explicit" \
|
||||
+ ":-lssp_nonshared}"
|
||||
#else
|
||||
#define LINK_SSP_SPEC "%{fstack-protector|fstack-protector-all" \
|
||||
"|fstack-protector-strong|fstack-protector-explicit" \
|
||||
@ -1,30 +0,0 @@
|
||||
diff --git a/gcc/config/i386/pmm_malloc.h b/gcc/config/i386/pmm_malloc.h
|
||||
index 1b0bfe37852..d7b2b19bb3c 100644
|
||||
--- a/gcc/config/i386/pmm_malloc.h
|
||||
+++ b/gcc/config/i386/pmm_malloc.h
|
||||
@@ -27,12 +27,13 @@
|
||||
#include <stdlib.h>
|
||||
|
||||
/* We can't depend on <stdlib.h> since the prototype of posix_memalign
|
||||
- may not be visible. */
|
||||
+ may not be visible and we can't pollute the namespace either. */
|
||||
#ifndef __cplusplus
|
||||
-extern int posix_memalign (void **, size_t, size_t);
|
||||
+extern int _mm_posix_memalign (void **, size_t, size_t)
|
||||
#else
|
||||
-extern "C" int posix_memalign (void **, size_t, size_t) throw ();
|
||||
+extern "C" int _mm_posix_memalign (void **, size_t, size_t) throw ()
|
||||
#endif
|
||||
+__asm__("posix_memalign");
|
||||
|
||||
static __inline void *
|
||||
_mm_malloc (size_t __size, size_t __alignment)
|
||||
@@ -42,7 +43,7 @@ _mm_malloc (size_t __size, size_t __alignment)
|
||||
return malloc (__size);
|
||||
if (__alignment == 2 || (sizeof (void *) == 8 && __alignment == 4))
|
||||
__alignment = sizeof (void *);
|
||||
- if (posix_memalign (&__ptr, __alignment, __size) == 0)
|
||||
+ if (_mm_posix_memalign (&__ptr, __alignment, __size) == 0)
|
||||
return __ptr;
|
||||
else
|
||||
return NULL;
|
||||
@ -1,346 +0,0 @@
|
||||
diff --git a/gcc/config.gcc b/gcc/config.gcc
|
||||
index 357b0bed067..528add999f2 100644
|
||||
--- a/gcc/config.gcc
|
||||
+++ b/gcc/config.gcc
|
||||
@@ -556,7 +556,7 @@ s390*-*-*)
|
||||
extra_headers="s390intrin.h htmintrin.h htmxlintrin.h vecintrin.h"
|
||||
;;
|
||||
# Note the 'l'; we need to be able to match e.g. "shle" or "shl".
|
||||
-sh[123456789lbe]*-*-* | sh-*-*)
|
||||
+sh[123456789lbej]*-*-* | sh-*-*)
|
||||
cpu_type=sh
|
||||
extra_options="${extra_options} fused-madd.opt"
|
||||
extra_objs="${extra_objs} sh_treg_combine.o sh-mem.o sh_optimize_sett_clrt.o"
|
||||
@@ -3202,18 +3202,18 @@ s390x-ibm-tpf*)
|
||||
extra_options="${extra_options} s390/tpf.opt"
|
||||
tmake_file="${tmake_file} s390/t-s390"
|
||||
;;
|
||||
-sh-*-elf* | sh[12346l]*-*-elf* | \
|
||||
- sh-*-linux* | sh[2346lbe]*-*-linux* | \
|
||||
+sh-*-elf* | sh[12346lj]*-*-elf* | \
|
||||
+ sh-*-linux* | sh[2346lbej]*-*-linux* | \
|
||||
sh-*-netbsdelf* | shl*-*-netbsdelf*)
|
||||
tmake_file="${tmake_file} sh/t-sh sh/t-elf"
|
||||
if test x${with_endian} = x; then
|
||||
case ${target} in
|
||||
- sh[1234]*be-*-* | sh[1234]*eb-*-*) with_endian=big ;;
|
||||
+ sh[j1234]*be-*-* | sh[j1234]*eb-*-*) with_endian=big ;;
|
||||
shbe-*-* | sheb-*-*) with_endian=big,little ;;
|
||||
sh[1234]l* | sh[34]*-*-linux*) with_endian=little ;;
|
||||
shl* | sh*-*-linux* | \
|
||||
sh-superh-elf) with_endian=little,big ;;
|
||||
- sh[1234]*-*-*) with_endian=big ;;
|
||||
+ sh[j1234]*-*-*) with_endian=big ;;
|
||||
*) with_endian=big,little ;;
|
||||
esac
|
||||
fi
|
||||
@@ -3280,6 +3280,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
|
||||
sh2a_nofpu*) sh_cpu_target=sh2a-nofpu ;;
|
||||
sh2a*) sh_cpu_target=sh2a ;;
|
||||
sh2e*) sh_cpu_target=sh2e ;;
|
||||
+ shj2*) sh_cpu_target=shj2;;
|
||||
sh2*) sh_cpu_target=sh2 ;;
|
||||
*) sh_cpu_target=sh1 ;;
|
||||
esac
|
||||
@@ -3301,7 +3302,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
|
||||
sh2a-single-only | sh2a-single | sh2a-nofpu | sh2a | \
|
||||
sh4a-single-only | sh4a-single | sh4a-nofpu | sh4a | sh4al | \
|
||||
sh4-single-only | sh4-single | sh4-nofpu | sh4 | sh4-300 | \
|
||||
- sh3e | sh3 | sh2e | sh2 | sh1) ;;
|
||||
+ sh3e | sh3 | sh2e | sh2 | sh1 | shj2) ;;
|
||||
"") sh_cpu_default=${sh_cpu_target} ;;
|
||||
*) echo "with_cpu=$with_cpu not supported"; exit 1 ;;
|
||||
esac
|
||||
@@ -3310,9 +3311,9 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
|
||||
case ${target} in
|
||||
sh[1234]*) sh_multilibs=${sh_cpu_target} ;;
|
||||
sh-superh-*) sh_multilibs=m4,m4-single,m4-single-only,m4-nofpu ;;
|
||||
- sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4 ;;
|
||||
+ sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4,mj2 ;;
|
||||
sh*-*-netbsd*) sh_multilibs=m3,m3e,m4 ;;
|
||||
- *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single ;;
|
||||
+ *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single,mj2 ;;
|
||||
esac
|
||||
if test x$with_fp = xno; then
|
||||
sh_multilibs="`echo $sh_multilibs|sed -e s/m4/sh4-nofpu/ -e s/,m4-[^,]*//g -e s/,m[23]e// -e s/m2a,m2a-single/m2a-nofpu/ -e s/m5-..m....,//g`"
|
||||
@@ -3327,7 +3328,8 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
|
||||
m1 | m2 | m2e | m3 | m3e | \
|
||||
m4 | m4-single | m4-single-only | m4-nofpu | m4-300 |\
|
||||
m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al | \
|
||||
- m2a | m2a-single | m2a-single-only | m2a-nofpu)
|
||||
+ m2a | m2a-single | m2a-single-only | m2a-nofpu | \
|
||||
+ mj2)
|
||||
# TM_MULTILIB_CONFIG is used by t-sh for the non-endian multilib definition
|
||||
# It is passed to MULTIILIB_OPTIONS verbatim.
|
||||
TM_MULTILIB_CONFIG="${TM_MULTILIB_CONFIG}/${sh_multilib}"
|
||||
@@ -3344,7 +3346,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
|
||||
done
|
||||
TM_MULTILIB_CONFIG=`echo $TM_MULTILIB_CONFIG | sed 's:^/::'`
|
||||
if test x${enable_incomplete_targets} = xyes ; then
|
||||
- tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1"
|
||||
+ tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1 SUPPORT_SHJ2=1"
|
||||
fi
|
||||
tm_file="$tm_file ./sysroot-suffix.h"
|
||||
tmake_file="$tmake_file t-sysroot-suffix"
|
||||
@@ -5175,6 +5177,8 @@ case "${target}" in
|
||||
;;
|
||||
m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al)
|
||||
;;
|
||||
+ mj2)
|
||||
+ ;;
|
||||
*)
|
||||
echo "Unknown CPU used in --with-cpu=$with_cpu, known values:" 1>&2
|
||||
echo "m1 m2 m2e m3 m3e m4 m4-single m4-single-only m4-nofpu" 1>&2
|
||||
@@ -5385,7 +5389,7 @@ case ${target} in
|
||||
tmake_file="${cpu_type}/t-${cpu_type} ${tmake_file}"
|
||||
;;
|
||||
|
||||
- sh[123456ble]*-*-* | sh-*-*)
|
||||
+ sh[123456blej]*-*-* | sh-*-*)
|
||||
c_target_objs="${c_target_objs} sh-c.o"
|
||||
cxx_target_objs="${cxx_target_objs} sh-c.o"
|
||||
;;
|
||||
diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c
|
||||
index 1564109c942..798c1c1c1a3 100644
|
||||
--- a/gcc/config/sh/sh.c
|
||||
+++ b/gcc/config/sh/sh.c
|
||||
@@ -686,6 +686,7 @@ parse_validate_atomic_model_option (const char* str)
|
||||
model_names[sh_atomic_model::hard_llcs] = "hard-llcs";
|
||||
model_names[sh_atomic_model::soft_tcb] = "soft-tcb";
|
||||
model_names[sh_atomic_model::soft_imask] = "soft-imask";
|
||||
+ model_names[sh_atomic_model::hard_cas] = "hard-cas";
|
||||
|
||||
const char* model_cdef_names[sh_atomic_model::num_models];
|
||||
model_cdef_names[sh_atomic_model::none] = "NONE";
|
||||
@@ -693,6 +694,7 @@ parse_validate_atomic_model_option (const char* str)
|
||||
model_cdef_names[sh_atomic_model::hard_llcs] = "HARD_LLCS";
|
||||
model_cdef_names[sh_atomic_model::soft_tcb] = "SOFT_TCB";
|
||||
model_cdef_names[sh_atomic_model::soft_imask] = "SOFT_IMASK";
|
||||
+ model_cdef_names[sh_atomic_model::hard_cas] = "HARD_CAS";
|
||||
|
||||
sh_atomic_model ret;
|
||||
ret.type = sh_atomic_model::none;
|
||||
@@ -771,6 +773,9 @@ got_mode_name:;
|
||||
if (ret.type == sh_atomic_model::soft_imask && TARGET_USERMODE)
|
||||
err_ret ("cannot use atomic model %s in user mode", ret.name);
|
||||
|
||||
+ if (ret.type == sh_atomic_model::hard_cas && !TARGET_SHJ2)
|
||||
+ err_ret ("atomic model %s is only available J2 targets", ret.name);
|
||||
+
|
||||
return ret;
|
||||
|
||||
#undef err_ret
|
||||
@@ -827,6 +832,8 @@ sh_option_override (void)
|
||||
sh_cpu = PROCESSOR_SH2E;
|
||||
if (TARGET_SH2A)
|
||||
sh_cpu = PROCESSOR_SH2A;
|
||||
+ if (TARGET_SHJ2)
|
||||
+ sh_cpu = PROCESSOR_SHJ2;
|
||||
if (TARGET_SH3)
|
||||
sh_cpu = PROCESSOR_SH3;
|
||||
if (TARGET_SH3E)
|
||||
diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h
|
||||
index d2280e2ffe6..3a54a896721 100644
|
||||
--- a/gcc/config/sh/sh.h
|
||||
+++ b/gcc/config/sh/sh.h
|
||||
@@ -85,6 +85,7 @@ extern int code_for_indirect_jump_scratch;
|
||||
#define SUPPORT_SH4_SINGLE 1
|
||||
#define SUPPORT_SH2A 1
|
||||
#define SUPPORT_SH2A_SINGLE 1
|
||||
+#define SUPPORT_SHJ2 1
|
||||
#endif
|
||||
|
||||
#define TARGET_DIVIDE_CALL_DIV1 (sh_div_strategy == SH_DIV_CALL_DIV1)
|
||||
@@ -117,6 +118,7 @@ extern int code_for_indirect_jump_scratch;
|
||||
#define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY)
|
||||
#define SELECT_SH4A (MASK_SH4A | SELECT_SH4)
|
||||
#define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE)
|
||||
+#define SELECT_SHJ2 (MASK_SHJ2 | SELECT_SH2)
|
||||
|
||||
#if SUPPORT_SH1
|
||||
#define SUPPORT_SH2 1
|
||||
@@ -124,6 +126,7 @@ extern int code_for_indirect_jump_scratch;
|
||||
#if SUPPORT_SH2
|
||||
#define SUPPORT_SH3 1
|
||||
#define SUPPORT_SH2A_NOFPU 1
|
||||
+#define SUPPORT_SHJ2 1
|
||||
#endif
|
||||
#if SUPPORT_SH3
|
||||
#define SUPPORT_SH4_NOFPU 1
|
||||
@@ -156,7 +159,7 @@ extern int code_for_indirect_jump_scratch;
|
||||
#define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \
|
||||
| MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \
|
||||
| MASK_HARD_SH4 | MASK_FPU_SINGLE \
|
||||
- | MASK_FPU_SINGLE_ONLY)
|
||||
+ | MASK_FPU_SINGLE_ONLY | MASK_SHJ2)
|
||||
|
||||
/* This defaults us to big-endian. */
|
||||
#ifndef TARGET_ENDIAN_DEFAULT
|
||||
@@ -231,7 +234,8 @@ extern int code_for_indirect_jump_scratch;
|
||||
%{m2a-single:--isa=sh2a} \
|
||||
%{m2a-single-only:--isa=sh2a} \
|
||||
%{m2a-nofpu:--isa=sh2a-nofpu} \
|
||||
-%{m4al:-dsp}"
|
||||
+%{m4al:-dsp} \
|
||||
+%{mj2:-isa=j2}"
|
||||
|
||||
#define ASM_SPEC SH_ASM_SPEC
|
||||
|
||||
@@ -347,6 +351,7 @@ struct sh_atomic_model
|
||||
hard_llcs,
|
||||
soft_tcb,
|
||||
soft_imask,
|
||||
+ hard_cas,
|
||||
|
||||
num_models
|
||||
};
|
||||
@@ -390,6 +395,9 @@ extern const sh_atomic_model& selected_atomic_model (void);
|
||||
#define TARGET_ATOMIC_SOFT_IMASK \
|
||||
(selected_atomic_model ().type == sh_atomic_model::soft_imask)
|
||||
|
||||
+#define TARGET_ATOMIC_HARD_CAS \
|
||||
+ (selected_atomic_model ().type == sh_atomic_model::hard_cas)
|
||||
+
|
||||
#endif // __cplusplus
|
||||
|
||||
#define SUBTARGET_OVERRIDE_OPTIONS (void) 0
|
||||
@@ -1484,7 +1492,7 @@ extern bool current_function_interrupt;
|
||||
|
||||
/* Nonzero if the target supports dynamic shift instructions
|
||||
like shad and shld. */
|
||||
-#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A)
|
||||
+#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A || TARGET_SHJ2)
|
||||
|
||||
/* The cost of using the dynamic shift insns (shad, shld) are the same
|
||||
if they are available. If they are not available a library function will
|
||||
@@ -1747,6 +1755,7 @@ enum processor_type {
|
||||
PROCESSOR_SH2,
|
||||
PROCESSOR_SH2E,
|
||||
PROCESSOR_SH2A,
|
||||
+ PROCESSOR_SHJ2,
|
||||
PROCESSOR_SH3,
|
||||
PROCESSOR_SH3E,
|
||||
PROCESSOR_SH4,
|
||||
diff --git a/gcc/config/sh/sh.opt b/gcc/config/sh/sh.opt
|
||||
index b4755a812f3..0989a1c18da 100644
|
||||
--- a/gcc/config/sh/sh.opt
|
||||
+++ b/gcc/config/sh/sh.opt
|
||||
@@ -65,6 +65,10 @@ m2e
|
||||
Target RejectNegative Condition(SUPPORT_SH2E)
|
||||
Generate SH2e code.
|
||||
|
||||
+mj2
|
||||
+Target RejectNegative Mask(SHJ2) Condition(SUPPORT_SHJ2)
|
||||
+Generate J2 code.
|
||||
+
|
||||
m3
|
||||
Target RejectNegative Mask(SH3) Condition(SUPPORT_SH3)
|
||||
Generate SH3 code.
|
||||
diff --git a/gcc/config/sh/sync.md b/gcc/config/sh/sync.md
|
||||
index 2b43f8edb86..118fc5d06db 100644
|
||||
--- a/gcc/config/sh/sync.md
|
||||
+++ b/gcc/config/sh/sync.md
|
||||
@@ -240,6 +240,9 @@
|
||||
|| (TARGET_SH4A && <MODE>mode == SImode && !TARGET_ATOMIC_STRICT))
|
||||
atomic_insn = gen_atomic_compare_and_swap<mode>_hard (old_val, mem,
|
||||
exp_val, new_val);
|
||||
+ else if (TARGET_ATOMIC_HARD_CAS && <MODE>mode == SImode)
|
||||
+ atomic_insn = gen_atomic_compare_and_swap<mode>_cas (old_val, mem,
|
||||
+ exp_val, new_val);
|
||||
else if (TARGET_ATOMIC_SOFT_GUSA)
|
||||
atomic_insn = gen_atomic_compare_and_swap<mode>_soft_gusa (old_val, mem,
|
||||
exp_val, new_val);
|
||||
@@ -306,6 +309,57 @@
|
||||
}
|
||||
[(set_attr "length" "14")])
|
||||
|
||||
+(define_expand "atomic_compare_and_swapsi_cas"
|
||||
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
||||
+ (unspec_volatile:SI
|
||||
+ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra")
|
||||
+ (match_operand:SI 2 "register_operand" "r")
|
||||
+ (match_operand:SI 3 "register_operand" "r")]
|
||||
+ UNSPECV_CMPXCHG_1))]
|
||||
+ "TARGET_ATOMIC_HARD_CAS"
|
||||
+{
|
||||
+ rtx mem = gen_rtx_REG (SImode, 0);
|
||||
+ emit_move_insn (mem, force_reg (SImode, XEXP (operands[1], 0)));
|
||||
+ emit_insn (gen_shj2_cas (operands[0], mem, operands[2], operands[3]));
|
||||
+ DONE;
|
||||
+})
|
||||
+
|
||||
+(define_insn "shj2_cas"
|
||||
+ [(set (match_operand:SI 0 "register_operand" "=&r")
|
||||
+ (unspec_volatile:SI
|
||||
+ [(match_operand:SI 1 "register_operand" "=r")
|
||||
+ (match_operand:SI 2 "register_operand" "r")
|
||||
+ (match_operand:SI 3 "register_operand" "0")]
|
||||
+ UNSPECV_CMPXCHG_1))
|
||||
+ (set (reg:SI T_REG)
|
||||
+ (unspec_volatile:SI [(const_int 0)] UNSPECV_CMPXCHG_3))]
|
||||
+ "TARGET_ATOMIC_HARD_CAS"
|
||||
+ "cas.l %2,%0,@%1"
|
||||
+ [(set_attr "length" "2")]
|
||||
+)
|
||||
+
|
||||
+(define_expand "atomic_compare_and_swapqi_cas"
|
||||
+ [(set (match_operand:SI 0 "arith_reg_dest" "=&r")
|
||||
+ (unspec_volatile:SI
|
||||
+ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra")
|
||||
+ (match_operand:SI 2 "arith_operand" "rI08")
|
||||
+ (match_operand:SI 3 "arith_operand" "rI08")]
|
||||
+ UNSPECV_CMPXCHG_1))]
|
||||
+ "TARGET_ATOMIC_HARD_CAS"
|
||||
+{FAIL;}
|
||||
+)
|
||||
+
|
||||
+(define_expand "atomic_compare_and_swaphi_cas"
|
||||
+ [(set (match_operand:SI 0 "arith_reg_dest" "=&r")
|
||||
+ (unspec_volatile:SI
|
||||
+ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra")
|
||||
+ (match_operand:SI 2 "arith_operand" "rI08")
|
||||
+ (match_operand:SI 3 "arith_operand" "rI08")]
|
||||
+ UNSPECV_CMPXCHG_1))]
|
||||
+ "TARGET_ATOMIC_HARD_CAS"
|
||||
+{FAIL;}
|
||||
+)
|
||||
+
|
||||
;; The QIHImode llcs patterns modify the address register of the memory
|
||||
;; operand. In order to express that, we have to open code the memory
|
||||
;; operand. Initially the insn is expanded like every other atomic insn
|
||||
diff --git a/gcc/config/sh/t-sh b/gcc/config/sh/t-sh
|
||||
index 888f8ff7f25..29fd6ae45fd 100644
|
||||
--- a/gcc/config/sh/t-sh
|
||||
+++ b/gcc/config/sh/t-sh
|
||||
@@ -50,7 +50,8 @@ MULTILIB_MATCHES = $(shell \
|
||||
m2e,m3e,m4-single-only,m4-100-single-only,m4-200-single-only,m4-300-single-only,m4a-single-only \
|
||||
m2a-single,m2a-single-only \
|
||||
m4-single,m4-100-single,m4-200-single,m4-300-single,m4a-single \
|
||||
- m4,m4-100,m4-200,m4-300,m4a; do \
|
||||
+ m4,m4-100,m4-200,m4-300,m4a \
|
||||
+ mj2; do \
|
||||
subst= ; \
|
||||
for lib in `echo $$abi|tr , ' '` ; do \
|
||||
if test "`echo $$multilibs|sed s/$$lib//`" != "$$multilibs"; then \
|
||||
@@ -63,9 +64,9 @@ MULTILIB_MATCHES = $(shell \
|
||||
|
||||
# SH1 and SH2A support big endian only.
|
||||
ifeq ($(DEFAULT_ENDIAN),ml)
|
||||
-MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG)
|
||||
+MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG)
|
||||
else
|
||||
-MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG)
|
||||
+MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG)
|
||||
endif
|
||||
|
||||
MULTILIB_OSDIRNAMES = \
|
||||
@@ -87,7 +88,8 @@ MULTILIB_OSDIRNAMES = \
|
||||
m4a-single-only=!m4a-single-only $(OTHER_ENDIAN)/m4a-single-only=!$(OTHER_ENDIAN)/m4a-single-only \
|
||||
m4a-single=!m4a-single $(OTHER_ENDIAN)/m4a-single=!$(OTHER_ENDIAN)/m4a-single \
|
||||
m4a=!m4a $(OTHER_ENDIAN)/m4a=!$(OTHER_ENDIAN)/m4a \
|
||||
- m4al=!m4al $(OTHER_ENDIAN)/m4al=!$(OTHER_ENDIAN)/m4al
|
||||
+ m4al=!m4al $(OTHER_ENDIAN)/m4al=!$(OTHER_ENDIAN)/m4al \
|
||||
+ mj2=!j2
|
||||
|
||||
$(out_object_file): gt-sh.h
|
||||
gt-sh.h : s-gtype ; @true
|
||||
@ -1,92 +0,0 @@
|
||||
diff --git a/gcc/common.opt b/gcc/common.opt
|
||||
index a75b44ee47e..7c564818b49 100644
|
||||
--- a/gcc/common.opt
|
||||
+++ b/gcc/common.opt
|
||||
@@ -3473,11 +3473,11 @@ Driver
|
||||
|
||||
no-pie
|
||||
Driver RejectNegative Negative(shared)
|
||||
-Don't create a dynamically linked position independent executable.
|
||||
+Don't create a position independent executable.
|
||||
|
||||
pie
|
||||
Driver RejectNegative Negative(no-pie)
|
||||
-Create a dynamically linked position independent executable.
|
||||
+Create a position independent executable.
|
||||
|
||||
static-pie
|
||||
Driver RejectNegative Negative(pie)
|
||||
diff --git a/gcc/config/gnu-user.h b/gcc/config/gnu-user.h
|
||||
index 5ebbf42a13d..bb907d8e89a 100644
|
||||
--- a/gcc/config/gnu-user.h
|
||||
+++ b/gcc/config/gnu-user.h
|
||||
@@ -51,13 +51,12 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
|
||||
#define GNU_USER_TARGET_STARTFILE_SPEC \
|
||||
"%{shared:; \
|
||||
pg|p|profile:%{static-pie:grcrt1.o%s;:gcrt1.o%s}; \
|
||||
- static:crt1.o%s; \
|
||||
- static-pie:rcrt1.o%s; \
|
||||
+ static|static-pie:%{" PIE_SPEC ":rcrt1.o%s;:crt1.o%s}; \
|
||||
" PIE_SPEC ":Scrt1.o%s; \
|
||||
:crt1.o%s} " \
|
||||
GNU_USER_TARGET_CRTI " \
|
||||
- %{static:crtbeginT.o%s; \
|
||||
- shared|static-pie|" PIE_SPEC ":crtbeginS.o%s; \
|
||||
+ %{shared|" PIE_SPEC ":crtbeginS.o%s; \
|
||||
+ static:crtbeginT.o%s; \
|
||||
:crtbegin.o%s} \
|
||||
%{fvtable-verify=none:%s; \
|
||||
fvtable-verify=preinit:vtv_start_preinit.o%s; \
|
||||
@@ -73,11 +72,11 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
|
||||
GNU userspace "finalizer" file, `crtn.o'. */
|
||||
|
||||
#define GNU_USER_TARGET_ENDFILE_SPEC \
|
||||
- "%{!static:%{fvtable-verify=none:%s; \
|
||||
+ "%{static|static-pie:; \
|
||||
+ fvtable-verify=none:%s; \
|
||||
fvtable-verify=preinit:vtv_end_preinit.o%s; \
|
||||
- fvtable-verify=std:vtv_end.o%s}} \
|
||||
- %{static:crtend.o%s; \
|
||||
- shared|static-pie|" PIE_SPEC ":crtendS.o%s; \
|
||||
+ fvtable-verify=std:vtv_end.o%s} \
|
||||
+ %{shared|" PIE_SPEC ":crtendS.o%s; \
|
||||
:crtend.o%s} " \
|
||||
GNU_USER_TARGET_CRTN " " \
|
||||
CRTOFFLOADEND
|
||||
@@ -106,7 +105,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
|
||||
#define LIB_SPEC GNU_USER_TARGET_LIB_SPEC
|
||||
|
||||
#if defined(HAVE_LD_EH_FRAME_HDR)
|
||||
-#define LINK_EH_SPEC "%{!static|static-pie:--eh-frame-hdr} "
|
||||
+#define LINK_EH_SPEC "%{!static|" PIE_SPEC ":--eh-frame-hdr} "
|
||||
#endif
|
||||
|
||||
#define GNU_USER_TARGET_LINK_GCC_C_SEQUENCE_SPEC \
|
||||
diff --git a/gcc/gcc.c b/gcc/gcc.c
|
||||
index 3c81c5798d8..cd96eac5d12 100644
|
||||
--- a/gcc/gcc.c
|
||||
+++ b/gcc/gcc.c
|
||||
@@ -1010,7 +1010,7 @@ proper position among the other output files. */
|
||||
#define NO_FPIE_AND_FPIC_SPEC NO_FPIE_SPEC "|" NO_FPIC_SPEC
|
||||
#define FPIE_OR_FPIC_SPEC NO_FPIE_AND_FPIC_SPEC ":;"
|
||||
#else
|
||||
-#define PIE_SPEC "pie"
|
||||
+#define PIE_SPEC "pie|static-pie"
|
||||
#define FPIE1_SPEC "fpie"
|
||||
#define NO_FPIE1_SPEC FPIE1_SPEC ":;"
|
||||
#define FPIE2_SPEC "fPIE"
|
||||
@@ -1034,12 +1034,12 @@ proper position among the other output files. */
|
||||
#ifndef LINK_PIE_SPEC
|
||||
#ifdef HAVE_LD_PIE
|
||||
#ifndef LD_PIE_SPEC
|
||||
-#define LD_PIE_SPEC "-pie"
|
||||
+#define LD_PIE_SPEC "-pie %{static|static-pie:--no-dynamic-linker -z text -Bsymbolic}"
|
||||
#endif
|
||||
#else
|
||||
#define LD_PIE_SPEC ""
|
||||
#endif
|
||||
-#define LINK_PIE_SPEC "%{static|shared|r:;" PIE_SPEC ":" LD_PIE_SPEC "} "
|
||||
+#define LINK_PIE_SPEC "%{shared|r:;" PIE_SPEC ":" LD_PIE_SPEC "} "
|
||||
#endif
|
||||
|
||||
#ifndef LINK_BUILDID_SPEC
|
||||
@ -1,20 +0,0 @@
|
||||
diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md
|
||||
index 59a456cd496..dbfddea41bd 100644
|
||||
--- a/gcc/config/m68k/m68k.md
|
||||
+++ b/gcc/config/m68k/m68k.md
|
||||
@@ -4174,13 +4174,13 @@
|
||||
(define_expand "sqrt<mode>2"
|
||||
[(set (match_operand:FP 0 "nonimmediate_operand" "")
|
||||
(sqrt:FP (match_operand:FP 1 "general_operand" "")))]
|
||||
- "TARGET_HARD_FLOAT"
|
||||
+ "(TARGET_68881 && TARGET_68040) || TARGET_COLDFIRE_FPU"
|
||||
"")
|
||||
|
||||
(define_insn "sqrt<mode>2_68881"
|
||||
[(set (match_operand:FP 0 "nonimmediate_operand" "=f")
|
||||
(sqrt:FP (match_operand:FP 1 "general_operand" "f<FP:dreg>m")))]
|
||||
- "TARGET_68881"
|
||||
+ "TARGET_68881 && TARGET_68040"
|
||||
{
|
||||
if (FP_REG_P (operands[1]))
|
||||
return "f<FP:round>sqrt%.x %1,%0";
|
||||
@ -1,8 +0,0 @@
|
||||
--- a/libstdc++-v3/ChangeLog 2024-03-13 18:04:21.050801063 -0400
|
||||
+++ b/libstdc++-v3/ChangeLog 2024-03-13 18:04:25.665836804 -0400
|
||||
@@ -4068,4 +4068,4 @@
|
||||
|
||||
Copying and distribution of this file, with or without modification,
|
||||
are permitted in any medium without royalty provided the copyright
|
||||
-notice and this notice are preserved.
|
||||
+notice and this notice are preserved.
|
||||
@ -1,11 +0,0 @@
|
||||
--- a/libgcc/unwind-pe.h 2024-03-14 05:59:53.754073149 +0900
|
||||
+++ b/libgcc/unwind-pe.h 2024-03-14 06:00:41.226074492 +0900
|
||||
@@ -262,7 +262,7 @@
|
||||
|
||||
if (result != 0)
|
||||
{
|
||||
-#if __FDPIC__
|
||||
+#if __FDPIC__ && __arm__
|
||||
/* FDPIC relative addresses imply taking the GOT address
|
||||
into account. */
|
||||
if ((encoding & DW_EH_PE_pcrel) && (encoding & DW_EH_PE_indirect))
|
||||
@ -1,38 +0,0 @@
|
||||
--- a/libgcc/crtstuff.c 2023-05-29 17:46:32.000000000 +0900
|
||||
+++ b/libgcc/crtstuff.c 2024-03-14 06:03:42.398079615 +0900
|
||||
@@ -441,17 +441,9 @@
|
||||
#ifdef FINI_SECTION_ASM_OP
|
||||
CRT_CALL_STATIC_FUNCTION (FINI_SECTION_ASM_OP, __do_global_dtors_aux)
|
||||
#elif defined (FINI_ARRAY_SECTION_ASM_OP)
|
||||
-#if defined(__FDPIC__)
|
||||
-__asm__("\t.equ\t__do_global_dtors_aux_alias, __do_global_dtors_aux\n");
|
||||
-extern char __do_global_dtors_aux_alias;
|
||||
-static void *__do_global_dtors_aux_fini_array_entry[]
|
||||
-__attribute__ ((__used__, section(".fini_array"), aligned(sizeof(void *))))
|
||||
- = { &__do_global_dtors_aux_alias };
|
||||
-#else /* defined(__FDPIC__) */
|
||||
static func_ptr __do_global_dtors_aux_fini_array_entry[]
|
||||
__attribute__ ((__used__, section(".fini_array"),
|
||||
aligned(__alignof__(func_ptr)))) = { __do_global_dtors_aux };
|
||||
-#endif /* defined(__FDPIC__) */
|
||||
#else /* !FINI_SECTION_ASM_OP && !FINI_ARRAY_SECTION_ASM_OP */
|
||||
static void __attribute__((used))
|
||||
__do_global_dtors_aux_1 (void)
|
||||
@@ -494,17 +486,9 @@
|
||||
#ifdef __LIBGCC_INIT_SECTION_ASM_OP__
|
||||
CRT_CALL_STATIC_FUNCTION (__LIBGCC_INIT_SECTION_ASM_OP__, frame_dummy)
|
||||
#else /* defined(__LIBGCC_INIT_SECTION_ASM_OP__) */
|
||||
-#if defined(__FDPIC__)
|
||||
-__asm__("\t.equ\t__frame_dummy_alias, frame_dummy\n");
|
||||
-extern char __frame_dummy_alias;
|
||||
-static void *__frame_dummy_init_array_entry[]
|
||||
-__attribute__ ((__used__, section(".init_array"), aligned(sizeof(void *))))
|
||||
- = { &__frame_dummy_alias };
|
||||
-#else /* defined(__FDPIC__) */
|
||||
static func_ptr __frame_dummy_init_array_entry[]
|
||||
__attribute__ ((__used__, section(".init_array"),
|
||||
aligned(__alignof__(func_ptr)))) = { frame_dummy };
|
||||
-#endif /* defined(__FDPIC__) */
|
||||
#endif /* !defined(__LIBGCC_INIT_SECTION_ASM_OP__) */
|
||||
#endif /* USE_EH_FRAME_REGISTRY || USE_TM_CLONE_REGISTRY */
|
||||
|
||||
@ -1,12 +0,0 @@
|
||||
--- gcc-11.4.0/gcc/config/sh/sh.c.orig 2024-04-04 05:52:42.125373614 +0900
|
||||
+++ gcc-11.4.0/gcc/config/sh/sh.c 2024-04-04 22:54:01.875106654 +0900
|
||||
@@ -9147,7 +9147,7 @@
|
||||
{
|
||||
/* Weak functions may be NULL which doesn't work with
|
||||
GOTOFFFUNCDESC because the runtime offset is not known. */
|
||||
- if (SYMBOL_REF_WEAK (orig))
|
||||
+ if (SYMBOL_REF_WEAK (orig) || (TREE_PUBLIC(SYMBOL_REF_DECL(orig)) && DECL_VISIBILITY (SYMBOL_REF_DECL(orig)) != VISIBILITY_HIDDEN))
|
||||
emit_insn (gen_symGOTFUNCDESC2reg (reg, orig));
|
||||
else
|
||||
emit_insn (gen_symGOTOFFFUNCDESC2reg (reg, orig));
|
||||
|
||||
@ -1,30 +0,0 @@
|
||||
diff --git a/gcc/config/i386/pmm_malloc.h b/gcc/config/i386/pmm_malloc.h
|
||||
index 1b0bfe37852..d7b2b19bb3c 100644
|
||||
--- a/gcc/config/i386/pmm_malloc.h
|
||||
+++ b/gcc/config/i386/pmm_malloc.h
|
||||
@@ -27,12 +27,13 @@
|
||||
#include <stdlib.h>
|
||||
|
||||
/* We can't depend on <stdlib.h> since the prototype of posix_memalign
|
||||
- may not be visible. */
|
||||
+ may not be visible and we can't pollute the namespace either. */
|
||||
#ifndef __cplusplus
|
||||
-extern int posix_memalign (void **, size_t, size_t);
|
||||
+extern int _mm_posix_memalign (void **, size_t, size_t)
|
||||
#else
|
||||
-extern "C" int posix_memalign (void **, size_t, size_t) throw ();
|
||||
+extern "C" int _mm_posix_memalign (void **, size_t, size_t) throw ()
|
||||
#endif
|
||||
+__asm__("posix_memalign");
|
||||
|
||||
static __inline void *
|
||||
_mm_malloc (size_t __size, size_t __alignment)
|
||||
@@ -42,7 +43,7 @@ _mm_malloc (size_t __size, size_t __alignment)
|
||||
return malloc (__size);
|
||||
if (__alignment == 2 || (sizeof (void *) == 8 && __alignment == 4))
|
||||
__alignment = sizeof (void *);
|
||||
- if (posix_memalign (&__ptr, __alignment, __size) == 0)
|
||||
+ if (_mm_posix_memalign (&__ptr, __alignment, __size) == 0)
|
||||
return __ptr;
|
||||
else
|
||||
return NULL;
|
||||
@ -1,346 +0,0 @@
|
||||
diff --git a/gcc/config.gcc b/gcc/config.gcc
|
||||
index 357b0bed067..528add999f2 100644
|
||||
--- a/gcc/config.gcc
|
||||
+++ b/gcc/config.gcc
|
||||
@@ -556,7 +556,7 @@ s390*-*-*)
|
||||
extra_headers="s390intrin.h htmintrin.h htmxlintrin.h vecintrin.h"
|
||||
;;
|
||||
# Note the 'l'; we need to be able to match e.g. "shle" or "shl".
|
||||
-sh[123456789lbe]*-*-* | sh-*-*)
|
||||
+sh[123456789lbej]*-*-* | sh-*-*)
|
||||
cpu_type=sh
|
||||
extra_options="${extra_options} fused-madd.opt"
|
||||
extra_objs="${extra_objs} sh_treg_combine.o sh-mem.o sh_optimize_sett_clrt.o"
|
||||
@@ -3202,18 +3202,18 @@ s390x-ibm-tpf*)
|
||||
extra_options="${extra_options} s390/tpf.opt"
|
||||
tmake_file="${tmake_file} s390/t-s390"
|
||||
;;
|
||||
-sh-*-elf* | sh[12346l]*-*-elf* | \
|
||||
- sh-*-linux* | sh[2346lbe]*-*-linux* | \
|
||||
+sh-*-elf* | sh[12346lj]*-*-elf* | \
|
||||
+ sh-*-linux* | sh[2346lbej]*-*-linux* | \
|
||||
sh-*-netbsdelf* | shl*-*-netbsdelf*)
|
||||
tmake_file="${tmake_file} sh/t-sh sh/t-elf"
|
||||
if test x${with_endian} = x; then
|
||||
case ${target} in
|
||||
- sh[1234]*be-*-* | sh[1234]*eb-*-*) with_endian=big ;;
|
||||
+ sh[j1234]*be-*-* | sh[j1234]*eb-*-*) with_endian=big ;;
|
||||
shbe-*-* | sheb-*-*) with_endian=big,little ;;
|
||||
sh[1234]l* | sh[34]*-*-linux*) with_endian=little ;;
|
||||
shl* | sh*-*-linux* | \
|
||||
sh-superh-elf) with_endian=little,big ;;
|
||||
- sh[1234]*-*-*) with_endian=big ;;
|
||||
+ sh[j1234]*-*-*) with_endian=big ;;
|
||||
*) with_endian=big,little ;;
|
||||
esac
|
||||
fi
|
||||
@@ -3280,6 +3280,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
|
||||
sh2a_nofpu*) sh_cpu_target=sh2a-nofpu ;;
|
||||
sh2a*) sh_cpu_target=sh2a ;;
|
||||
sh2e*) sh_cpu_target=sh2e ;;
|
||||
+ shj2*) sh_cpu_target=shj2;;
|
||||
sh2*) sh_cpu_target=sh2 ;;
|
||||
*) sh_cpu_target=sh1 ;;
|
||||
esac
|
||||
@@ -3301,7 +3302,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
|
||||
sh2a-single-only | sh2a-single | sh2a-nofpu | sh2a | \
|
||||
sh4a-single-only | sh4a-single | sh4a-nofpu | sh4a | sh4al | \
|
||||
sh4-single-only | sh4-single | sh4-nofpu | sh4 | sh4-300 | \
|
||||
- sh3e | sh3 | sh2e | sh2 | sh1) ;;
|
||||
+ sh3e | sh3 | sh2e | sh2 | sh1 | shj2) ;;
|
||||
"") sh_cpu_default=${sh_cpu_target} ;;
|
||||
*) echo "with_cpu=$with_cpu not supported"; exit 1 ;;
|
||||
esac
|
||||
@@ -3310,9 +3311,9 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
|
||||
case ${target} in
|
||||
sh[1234]*) sh_multilibs=${sh_cpu_target} ;;
|
||||
sh-superh-*) sh_multilibs=m4,m4-single,m4-single-only,m4-nofpu ;;
|
||||
- sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4 ;;
|
||||
+ sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4,mj2 ;;
|
||||
sh*-*-netbsd*) sh_multilibs=m3,m3e,m4 ;;
|
||||
- *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single ;;
|
||||
+ *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single,mj2 ;;
|
||||
esac
|
||||
if test x$with_fp = xno; then
|
||||
sh_multilibs="`echo $sh_multilibs|sed -e s/m4/sh4-nofpu/ -e s/,m4-[^,]*//g -e s/,m[23]e// -e s/m2a,m2a-single/m2a-nofpu/ -e s/m5-..m....,//g`"
|
||||
@@ -3327,7 +3328,8 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
|
||||
m1 | m2 | m2e | m3 | m3e | \
|
||||
m4 | m4-single | m4-single-only | m4-nofpu | m4-300 |\
|
||||
m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al | \
|
||||
- m2a | m2a-single | m2a-single-only | m2a-nofpu)
|
||||
+ m2a | m2a-single | m2a-single-only | m2a-nofpu | \
|
||||
+ mj2)
|
||||
# TM_MULTILIB_CONFIG is used by t-sh for the non-endian multilib definition
|
||||
# It is passed to MULTIILIB_OPTIONS verbatim.
|
||||
TM_MULTILIB_CONFIG="${TM_MULTILIB_CONFIG}/${sh_multilib}"
|
||||
@@ -3344,7 +3346,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
|
||||
done
|
||||
TM_MULTILIB_CONFIG=`echo $TM_MULTILIB_CONFIG | sed 's:^/::'`
|
||||
if test x${enable_incomplete_targets} = xyes ; then
|
||||
- tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1"
|
||||
+ tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1 SUPPORT_SHJ2=1"
|
||||
fi
|
||||
tm_file="$tm_file ./sysroot-suffix.h"
|
||||
tmake_file="$tmake_file t-sysroot-suffix"
|
||||
@@ -5175,6 +5177,8 @@ case "${target}" in
|
||||
;;
|
||||
m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al)
|
||||
;;
|
||||
+ mj2)
|
||||
+ ;;
|
||||
*)
|
||||
echo "Unknown CPU used in --with-cpu=$with_cpu, known values:" 1>&2
|
||||
echo "m1 m2 m2e m3 m3e m4 m4-single m4-single-only m4-nofpu" 1>&2
|
||||
@@ -5385,7 +5389,7 @@ case ${target} in
|
||||
tmake_file="${cpu_type}/t-${cpu_type} ${tmake_file}"
|
||||
;;
|
||||
|
||||
- sh[123456ble]*-*-* | sh-*-*)
|
||||
+ sh[123456blej]*-*-* | sh-*-*)
|
||||
c_target_objs="${c_target_objs} sh-c.o"
|
||||
cxx_target_objs="${cxx_target_objs} sh-c.o"
|
||||
;;
|
||||
diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c
|
||||
index 1564109c942..798c1c1c1a3 100644
|
||||
--- a/gcc/config/sh/sh.c
|
||||
+++ b/gcc/config/sh/sh.c
|
||||
@@ -686,6 +686,7 @@ parse_validate_atomic_model_option (const char* str)
|
||||
model_names[sh_atomic_model::hard_llcs] = "hard-llcs";
|
||||
model_names[sh_atomic_model::soft_tcb] = "soft-tcb";
|
||||
model_names[sh_atomic_model::soft_imask] = "soft-imask";
|
||||
+ model_names[sh_atomic_model::hard_cas] = "hard-cas";
|
||||
|
||||
const char* model_cdef_names[sh_atomic_model::num_models];
|
||||
model_cdef_names[sh_atomic_model::none] = "NONE";
|
||||
@@ -693,6 +694,7 @@ parse_validate_atomic_model_option (const char* str)
|
||||
model_cdef_names[sh_atomic_model::hard_llcs] = "HARD_LLCS";
|
||||
model_cdef_names[sh_atomic_model::soft_tcb] = "SOFT_TCB";
|
||||
model_cdef_names[sh_atomic_model::soft_imask] = "SOFT_IMASK";
|
||||
+ model_cdef_names[sh_atomic_model::hard_cas] = "HARD_CAS";
|
||||
|
||||
sh_atomic_model ret;
|
||||
ret.type = sh_atomic_model::none;
|
||||
@@ -771,6 +773,9 @@ got_mode_name:;
|
||||
if (ret.type == sh_atomic_model::soft_imask && TARGET_USERMODE)
|
||||
err_ret ("cannot use atomic model %s in user mode", ret.name);
|
||||
|
||||
+ if (ret.type == sh_atomic_model::hard_cas && !TARGET_SHJ2)
|
||||
+ err_ret ("atomic model %s is only available J2 targets", ret.name);
|
||||
+
|
||||
return ret;
|
||||
|
||||
#undef err_ret
|
||||
@@ -827,6 +832,8 @@ sh_option_override (void)
|
||||
sh_cpu = PROCESSOR_SH2E;
|
||||
if (TARGET_SH2A)
|
||||
sh_cpu = PROCESSOR_SH2A;
|
||||
+ if (TARGET_SHJ2)
|
||||
+ sh_cpu = PROCESSOR_SHJ2;
|
||||
if (TARGET_SH3)
|
||||
sh_cpu = PROCESSOR_SH3;
|
||||
if (TARGET_SH3E)
|
||||
diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h
|
||||
index d2280e2ffe6..3a54a896721 100644
|
||||
--- a/gcc/config/sh/sh.h
|
||||
+++ b/gcc/config/sh/sh.h
|
||||
@@ -85,6 +85,7 @@ extern int code_for_indirect_jump_scratch;
|
||||
#define SUPPORT_SH4_SINGLE 1
|
||||
#define SUPPORT_SH2A 1
|
||||
#define SUPPORT_SH2A_SINGLE 1
|
||||
+#define SUPPORT_SHJ2 1
|
||||
#endif
|
||||
|
||||
#define TARGET_DIVIDE_CALL_DIV1 (sh_div_strategy == SH_DIV_CALL_DIV1)
|
||||
@@ -117,6 +118,7 @@ extern int code_for_indirect_jump_scratch;
|
||||
#define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY)
|
||||
#define SELECT_SH4A (MASK_SH4A | SELECT_SH4)
|
||||
#define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE)
|
||||
+#define SELECT_SHJ2 (MASK_SHJ2 | SELECT_SH2)
|
||||
|
||||
#if SUPPORT_SH1
|
||||
#define SUPPORT_SH2 1
|
||||
@@ -124,6 +126,7 @@ extern int code_for_indirect_jump_scratch;
|
||||
#if SUPPORT_SH2
|
||||
#define SUPPORT_SH3 1
|
||||
#define SUPPORT_SH2A_NOFPU 1
|
||||
+#define SUPPORT_SHJ2 1
|
||||
#endif
|
||||
#if SUPPORT_SH3
|
||||
#define SUPPORT_SH4_NOFPU 1
|
||||
@@ -156,7 +159,7 @@ extern int code_for_indirect_jump_scratch;
|
||||
#define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \
|
||||
| MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \
|
||||
| MASK_HARD_SH4 | MASK_FPU_SINGLE \
|
||||
- | MASK_FPU_SINGLE_ONLY)
|
||||
+ | MASK_FPU_SINGLE_ONLY | MASK_SHJ2)
|
||||
|
||||
/* This defaults us to big-endian. */
|
||||
#ifndef TARGET_ENDIAN_DEFAULT
|
||||
@@ -231,7 +234,8 @@ extern int code_for_indirect_jump_scratch;
|
||||
%{m2a-single:--isa=sh2a} \
|
||||
%{m2a-single-only:--isa=sh2a} \
|
||||
%{m2a-nofpu:--isa=sh2a-nofpu} \
|
||||
-%{m4al:-dsp}"
|
||||
+%{m4al:-dsp} \
|
||||
+%{mj2:-isa=j2}"
|
||||
|
||||
#define ASM_SPEC SH_ASM_SPEC
|
||||
|
||||
@@ -347,6 +351,7 @@ struct sh_atomic_model
|
||||
hard_llcs,
|
||||
soft_tcb,
|
||||
soft_imask,
|
||||
+ hard_cas,
|
||||
|
||||
num_models
|
||||
};
|
||||
@@ -390,6 +395,9 @@ extern const sh_atomic_model& selected_atomic_model (void);
|
||||
#define TARGET_ATOMIC_SOFT_IMASK \
|
||||
(selected_atomic_model ().type == sh_atomic_model::soft_imask)
|
||||
|
||||
+#define TARGET_ATOMIC_HARD_CAS \
|
||||
+ (selected_atomic_model ().type == sh_atomic_model::hard_cas)
|
||||
+
|
||||
#endif // __cplusplus
|
||||
|
||||
#define SUBTARGET_OVERRIDE_OPTIONS (void) 0
|
||||
@@ -1484,7 +1492,7 @@ extern bool current_function_interrupt;
|
||||
|
||||
/* Nonzero if the target supports dynamic shift instructions
|
||||
like shad and shld. */
|
||||
-#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A)
|
||||
+#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A || TARGET_SHJ2)
|
||||
|
||||
/* The cost of using the dynamic shift insns (shad, shld) are the same
|
||||
if they are available. If they are not available a library function will
|
||||
@@ -1747,6 +1755,7 @@ enum processor_type {
|
||||
PROCESSOR_SH2,
|
||||
PROCESSOR_SH2E,
|
||||
PROCESSOR_SH2A,
|
||||
+ PROCESSOR_SHJ2,
|
||||
PROCESSOR_SH3,
|
||||
PROCESSOR_SH3E,
|
||||
PROCESSOR_SH4,
|
||||
diff --git a/gcc/config/sh/sh.opt b/gcc/config/sh/sh.opt
|
||||
index b4755a812f3..0989a1c18da 100644
|
||||
--- a/gcc/config/sh/sh.opt
|
||||
+++ b/gcc/config/sh/sh.opt
|
||||
@@ -65,6 +65,10 @@ m2e
|
||||
Target RejectNegative Condition(SUPPORT_SH2E)
|
||||
Generate SH2e code.
|
||||
|
||||
+mj2
|
||||
+Target RejectNegative Mask(SHJ2) Condition(SUPPORT_SHJ2)
|
||||
+Generate J2 code.
|
||||
+
|
||||
m3
|
||||
Target RejectNegative Mask(SH3) Condition(SUPPORT_SH3)
|
||||
Generate SH3 code.
|
||||
diff --git a/gcc/config/sh/sync.md b/gcc/config/sh/sync.md
|
||||
index 2b43f8edb86..118fc5d06db 100644
|
||||
--- a/gcc/config/sh/sync.md
|
||||
+++ b/gcc/config/sh/sync.md
|
||||
@@ -240,6 +240,9 @@
|
||||
|| (TARGET_SH4A && <MODE>mode == SImode && !TARGET_ATOMIC_STRICT))
|
||||
atomic_insn = gen_atomic_compare_and_swap<mode>_hard (old_val, mem,
|
||||
exp_val, new_val);
|
||||
+ else if (TARGET_ATOMIC_HARD_CAS && <MODE>mode == SImode)
|
||||
+ atomic_insn = gen_atomic_compare_and_swap<mode>_cas (old_val, mem,
|
||||
+ exp_val, new_val);
|
||||
else if (TARGET_ATOMIC_SOFT_GUSA)
|
||||
atomic_insn = gen_atomic_compare_and_swap<mode>_soft_gusa (old_val, mem,
|
||||
exp_val, new_val);
|
||||
@@ -306,6 +309,57 @@
|
||||
}
|
||||
[(set_attr "length" "14")])
|
||||
|
||||
+(define_expand "atomic_compare_and_swapsi_cas"
|
||||
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
||||
+ (unspec_volatile:SI
|
||||
+ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra")
|
||||
+ (match_operand:SI 2 "register_operand" "r")
|
||||
+ (match_operand:SI 3 "register_operand" "r")]
|
||||
+ UNSPECV_CMPXCHG_1))]
|
||||
+ "TARGET_ATOMIC_HARD_CAS"
|
||||
+{
|
||||
+ rtx mem = gen_rtx_REG (SImode, 0);
|
||||
+ emit_move_insn (mem, force_reg (SImode, XEXP (operands[1], 0)));
|
||||
+ emit_insn (gen_shj2_cas (operands[0], mem, operands[2], operands[3]));
|
||||
+ DONE;
|
||||
+})
|
||||
+
|
||||
+(define_insn "shj2_cas"
|
||||
+ [(set (match_operand:SI 0 "register_operand" "=&r")
|
||||
+ (unspec_volatile:SI
|
||||
+ [(match_operand:SI 1 "register_operand" "=r")
|
||||
+ (match_operand:SI 2 "register_operand" "r")
|
||||
+ (match_operand:SI 3 "register_operand" "0")]
|
||||
+ UNSPECV_CMPXCHG_1))
|
||||
+ (set (reg:SI T_REG)
|
||||
+ (unspec_volatile:SI [(const_int 0)] UNSPECV_CMPXCHG_3))]
|
||||
+ "TARGET_ATOMIC_HARD_CAS"
|
||||
+ "cas.l %2,%0,@%1"
|
||||
+ [(set_attr "length" "2")]
|
||||
+)
|
||||
+
|
||||
+(define_expand "atomic_compare_and_swapqi_cas"
|
||||
+ [(set (match_operand:SI 0 "arith_reg_dest" "=&r")
|
||||
+ (unspec_volatile:SI
|
||||
+ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra")
|
||||
+ (match_operand:SI 2 "arith_operand" "rI08")
|
||||
+ (match_operand:SI 3 "arith_operand" "rI08")]
|
||||
+ UNSPECV_CMPXCHG_1))]
|
||||
+ "TARGET_ATOMIC_HARD_CAS"
|
||||
+{FAIL;}
|
||||
+)
|
||||
+
|
||||
+(define_expand "atomic_compare_and_swaphi_cas"
|
||||
+ [(set (match_operand:SI 0 "arith_reg_dest" "=&r")
|
||||
+ (unspec_volatile:SI
|
||||
+ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra")
|
||||
+ (match_operand:SI 2 "arith_operand" "rI08")
|
||||
+ (match_operand:SI 3 "arith_operand" "rI08")]
|
||||
+ UNSPECV_CMPXCHG_1))]
|
||||
+ "TARGET_ATOMIC_HARD_CAS"
|
||||
+{FAIL;}
|
||||
+)
|
||||
+
|
||||
;; The QIHImode llcs patterns modify the address register of the memory
|
||||
;; operand. In order to express that, we have to open code the memory
|
||||
;; operand. Initially the insn is expanded like every other atomic insn
|
||||
diff --git a/gcc/config/sh/t-sh b/gcc/config/sh/t-sh
|
||||
index 888f8ff7f25..29fd6ae45fd 100644
|
||||
--- a/gcc/config/sh/t-sh
|
||||
+++ b/gcc/config/sh/t-sh
|
||||
@@ -50,7 +50,8 @@ MULTILIB_MATCHES = $(shell \
|
||||
m2e,m3e,m4-single-only,m4-100-single-only,m4-200-single-only,m4-300-single-only,m4a-single-only \
|
||||
m2a-single,m2a-single-only \
|
||||
m4-single,m4-100-single,m4-200-single,m4-300-single,m4a-single \
|
||||
- m4,m4-100,m4-200,m4-300,m4a; do \
|
||||
+ m4,m4-100,m4-200,m4-300,m4a \
|
||||
+ mj2; do \
|
||||
subst= ; \
|
||||
for lib in `echo $$abi|tr , ' '` ; do \
|
||||
if test "`echo $$multilibs|sed s/$$lib//`" != "$$multilibs"; then \
|
||||
@@ -63,9 +64,9 @@ MULTILIB_MATCHES = $(shell \
|
||||
|
||||
# SH1 and SH2A support big endian only.
|
||||
ifeq ($(DEFAULT_ENDIAN),ml)
|
||||
-MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG)
|
||||
+MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG)
|
||||
else
|
||||
-MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG)
|
||||
+MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG)
|
||||
endif
|
||||
|
||||
MULTILIB_OSDIRNAMES = \
|
||||
@@ -87,7 +88,8 @@ MULTILIB_OSDIRNAMES = \
|
||||
m4a-single-only=!m4a-single-only $(OTHER_ENDIAN)/m4a-single-only=!$(OTHER_ENDIAN)/m4a-single-only \
|
||||
m4a-single=!m4a-single $(OTHER_ENDIAN)/m4a-single=!$(OTHER_ENDIAN)/m4a-single \
|
||||
m4a=!m4a $(OTHER_ENDIAN)/m4a=!$(OTHER_ENDIAN)/m4a \
|
||||
- m4al=!m4al $(OTHER_ENDIAN)/m4al=!$(OTHER_ENDIAN)/m4al
|
||||
+ m4al=!m4al $(OTHER_ENDIAN)/m4al=!$(OTHER_ENDIAN)/m4al \
|
||||
+ mj2=!j2
|
||||
|
||||
$(out_object_file): gt-sh.h
|
||||
gt-sh.h : s-gtype ; @true
|
||||
@ -1,92 +0,0 @@
|
||||
diff --git a/gcc/common.opt b/gcc/common.opt
|
||||
index a75b44ee47e..7c564818b49 100644
|
||||
--- a/gcc/common.opt
|
||||
+++ b/gcc/common.opt
|
||||
@@ -3473,11 +3473,11 @@ Driver
|
||||
|
||||
no-pie
|
||||
Driver RejectNegative Negative(shared)
|
||||
-Don't create a dynamically linked position independent executable.
|
||||
+Don't create a position independent executable.
|
||||
|
||||
pie
|
||||
Driver RejectNegative Negative(no-pie)
|
||||
-Create a dynamically linked position independent executable.
|
||||
+Create a position independent executable.
|
||||
|
||||
static-pie
|
||||
Driver RejectNegative Negative(pie)
|
||||
diff --git a/gcc/config/gnu-user.h b/gcc/config/gnu-user.h
|
||||
index 5ebbf42a13d..bb907d8e89a 100644
|
||||
--- a/gcc/config/gnu-user.h
|
||||
+++ b/gcc/config/gnu-user.h
|
||||
@@ -51,13 +51,12 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
|
||||
#define GNU_USER_TARGET_STARTFILE_SPEC \
|
||||
"%{shared:; \
|
||||
pg|p|profile:%{static-pie:grcrt1.o%s;:gcrt1.o%s}; \
|
||||
- static:crt1.o%s; \
|
||||
- static-pie:rcrt1.o%s; \
|
||||
+ static|static-pie:%{" PIE_SPEC ":rcrt1.o%s;:crt1.o%s}; \
|
||||
" PIE_SPEC ":Scrt1.o%s; \
|
||||
:crt1.o%s} " \
|
||||
GNU_USER_TARGET_CRTI " \
|
||||
- %{static:crtbeginT.o%s; \
|
||||
- shared|static-pie|" PIE_SPEC ":crtbeginS.o%s; \
|
||||
+ %{shared|" PIE_SPEC ":crtbeginS.o%s; \
|
||||
+ static:crtbeginT.o%s; \
|
||||
:crtbegin.o%s} \
|
||||
%{fvtable-verify=none:%s; \
|
||||
fvtable-verify=preinit:vtv_start_preinit.o%s; \
|
||||
@@ -73,11 +72,11 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
|
||||
GNU userspace "finalizer" file, `crtn.o'. */
|
||||
|
||||
#define GNU_USER_TARGET_ENDFILE_SPEC \
|
||||
- "%{!static:%{fvtable-verify=none:%s; \
|
||||
+ "%{static|static-pie:; \
|
||||
+ fvtable-verify=none:%s; \
|
||||
fvtable-verify=preinit:vtv_end_preinit.o%s; \
|
||||
- fvtable-verify=std:vtv_end.o%s}} \
|
||||
- %{static:crtend.o%s; \
|
||||
- shared|static-pie|" PIE_SPEC ":crtendS.o%s; \
|
||||
+ fvtable-verify=std:vtv_end.o%s} \
|
||||
+ %{shared|" PIE_SPEC ":crtendS.o%s; \
|
||||
:crtend.o%s} " \
|
||||
GNU_USER_TARGET_CRTN " " \
|
||||
CRTOFFLOADEND
|
||||
@@ -106,7 +105,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
|
||||
#define LIB_SPEC GNU_USER_TARGET_LIB_SPEC
|
||||
|
||||
#if defined(HAVE_LD_EH_FRAME_HDR)
|
||||
-#define LINK_EH_SPEC "%{!static|static-pie:--eh-frame-hdr} "
|
||||
+#define LINK_EH_SPEC "%{!static|" PIE_SPEC ":--eh-frame-hdr} "
|
||||
#endif
|
||||
|
||||
#define GNU_USER_TARGET_LINK_GCC_C_SEQUENCE_SPEC \
|
||||
diff --git a/gcc/gcc.c b/gcc/gcc.c
|
||||
index 3c81c5798d8..cd96eac5d12 100644
|
||||
--- a/gcc/gcc.c
|
||||
+++ b/gcc/gcc.c
|
||||
@@ -1010,7 +1010,7 @@ proper position among the other output files. */
|
||||
#define NO_FPIE_AND_FPIC_SPEC NO_FPIE_SPEC "|" NO_FPIC_SPEC
|
||||
#define FPIE_OR_FPIC_SPEC NO_FPIE_AND_FPIC_SPEC ":;"
|
||||
#else
|
||||
-#define PIE_SPEC "pie"
|
||||
+#define PIE_SPEC "pie|static-pie"
|
||||
#define FPIE1_SPEC "fpie"
|
||||
#define NO_FPIE1_SPEC FPIE1_SPEC ":;"
|
||||
#define FPIE2_SPEC "fPIE"
|
||||
@@ -1034,12 +1034,12 @@ proper position among the other output files. */
|
||||
#ifndef LINK_PIE_SPEC
|
||||
#ifdef HAVE_LD_PIE
|
||||
#ifndef LD_PIE_SPEC
|
||||
-#define LD_PIE_SPEC "-pie"
|
||||
+#define LD_PIE_SPEC "-pie %{static|static-pie:--no-dynamic-linker -z text -Bsymbolic}"
|
||||
#endif
|
||||
#else
|
||||
#define LD_PIE_SPEC ""
|
||||
#endif
|
||||
-#define LINK_PIE_SPEC "%{static|shared|r:;" PIE_SPEC ":" LD_PIE_SPEC "} "
|
||||
+#define LINK_PIE_SPEC "%{shared|r:;" PIE_SPEC ":" LD_PIE_SPEC "} "
|
||||
#endif
|
||||
|
||||
#ifndef LINK_BUILDID_SPEC
|
||||
@ -1,20 +0,0 @@
|
||||
diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md
|
||||
index 59a456cd496..dbfddea41bd 100644
|
||||
--- a/gcc/config/m68k/m68k.md
|
||||
+++ b/gcc/config/m68k/m68k.md
|
||||
@@ -4174,13 +4174,13 @@
|
||||
(define_expand "sqrt<mode>2"
|
||||
[(set (match_operand:FP 0 "nonimmediate_operand" "")
|
||||
(sqrt:FP (match_operand:FP 1 "general_operand" "")))]
|
||||
- "TARGET_HARD_FLOAT"
|
||||
+ "(TARGET_68881 && TARGET_68040) || TARGET_COLDFIRE_FPU"
|
||||
"")
|
||||
|
||||
(define_insn "sqrt<mode>2_68881"
|
||||
[(set (match_operand:FP 0 "nonimmediate_operand" "=f")
|
||||
(sqrt:FP (match_operand:FP 1 "general_operand" "f<FP:dreg>m")))]
|
||||
- "TARGET_68881"
|
||||
+ "TARGET_68881 && TARGET_68040"
|
||||
{
|
||||
if (FP_REG_P (operands[1]))
|
||||
return "f<FP:round>sqrt%.x %1,%0";
|
||||
@ -1,8 +0,0 @@
|
||||
--- a/libstdc++-v3/ChangeLog 2024-03-13 18:04:21.050801063 -0400
|
||||
+++ b/libstdc++-v3/ChangeLog 2024-03-13 18:04:25.665836804 -0400
|
||||
@@ -4068,4 +4068,4 @@
|
||||
|
||||
Copying and distribution of this file, with or without modification,
|
||||
are permitted in any medium without royalty provided the copyright
|
||||
-notice and this notice are preserved.
|
||||
+notice and this notice are preserved.
|
||||
@ -1,11 +0,0 @@
|
||||
--- a/libgcc/unwind-pe.h 2024-03-14 05:59:53.754073149 +0900
|
||||
+++ b/libgcc/unwind-pe.h 2024-03-14 06:00:41.226074492 +0900
|
||||
@@ -262,7 +262,7 @@
|
||||
|
||||
if (result != 0)
|
||||
{
|
||||
-#if __FDPIC__
|
||||
+#if __FDPIC__ && __arm__
|
||||
/* FDPIC relative addresses imply taking the GOT address
|
||||
into account. */
|
||||
if ((encoding & DW_EH_PE_pcrel) && (encoding & DW_EH_PE_indirect))
|
||||
@ -1,38 +0,0 @@
|
||||
--- a/libgcc/crtstuff.c 2023-05-29 17:46:32.000000000 +0900
|
||||
+++ b/libgcc/crtstuff.c 2024-03-14 06:03:42.398079615 +0900
|
||||
@@ -441,17 +441,9 @@
|
||||
#ifdef FINI_SECTION_ASM_OP
|
||||
CRT_CALL_STATIC_FUNCTION (FINI_SECTION_ASM_OP, __do_global_dtors_aux)
|
||||
#elif defined (FINI_ARRAY_SECTION_ASM_OP)
|
||||
-#if defined(__FDPIC__)
|
||||
-__asm__("\t.equ\t__do_global_dtors_aux_alias, __do_global_dtors_aux\n");
|
||||
-extern char __do_global_dtors_aux_alias;
|
||||
-static void *__do_global_dtors_aux_fini_array_entry[]
|
||||
-__attribute__ ((__used__, section(".fini_array"), aligned(sizeof(void *))))
|
||||
- = { &__do_global_dtors_aux_alias };
|
||||
-#else /* defined(__FDPIC__) */
|
||||
static func_ptr __do_global_dtors_aux_fini_array_entry[]
|
||||
__attribute__ ((__used__, section(".fini_array"),
|
||||
aligned(__alignof__(func_ptr)))) = { __do_global_dtors_aux };
|
||||
-#endif /* defined(__FDPIC__) */
|
||||
#else /* !FINI_SECTION_ASM_OP && !FINI_ARRAY_SECTION_ASM_OP */
|
||||
static void __attribute__((used))
|
||||
__do_global_dtors_aux_1 (void)
|
||||
@@ -494,17 +486,9 @@
|
||||
#ifdef __LIBGCC_INIT_SECTION_ASM_OP__
|
||||
CRT_CALL_STATIC_FUNCTION (__LIBGCC_INIT_SECTION_ASM_OP__, frame_dummy)
|
||||
#else /* defined(__LIBGCC_INIT_SECTION_ASM_OP__) */
|
||||
-#if defined(__FDPIC__)
|
||||
-__asm__("\t.equ\t__frame_dummy_alias, frame_dummy\n");
|
||||
-extern char __frame_dummy_alias;
|
||||
-static void *__frame_dummy_init_array_entry[]
|
||||
-__attribute__ ((__used__, section(".init_array"), aligned(sizeof(void *))))
|
||||
- = { &__frame_dummy_alias };
|
||||
-#else /* defined(__FDPIC__) */
|
||||
static func_ptr __frame_dummy_init_array_entry[]
|
||||
__attribute__ ((__used__, section(".init_array"),
|
||||
aligned(__alignof__(func_ptr)))) = { frame_dummy };
|
||||
-#endif /* defined(__FDPIC__) */
|
||||
#endif /* !defined(__LIBGCC_INIT_SECTION_ASM_OP__) */
|
||||
#endif /* USE_EH_FRAME_REGISTRY || USE_TM_CLONE_REGISTRY */
|
||||
|
||||
@ -1,12 +0,0 @@
|
||||
--- gcc-11.4.0/gcc/config/sh/sh.c.orig 2024-04-04 05:52:42.125373614 +0900
|
||||
+++ gcc-11.4.0/gcc/config/sh/sh.c 2024-04-04 22:54:01.875106654 +0900
|
||||
@@ -9147,7 +9147,7 @@
|
||||
{
|
||||
/* Weak functions may be NULL which doesn't work with
|
||||
GOTOFFFUNCDESC because the runtime offset is not known. */
|
||||
- if (SYMBOL_REF_WEAK (orig))
|
||||
+ if (SYMBOL_REF_WEAK (orig) || (TREE_PUBLIC(SYMBOL_REF_DECL(orig)) && DECL_VISIBILITY (SYMBOL_REF_DECL(orig)) != VISIBILITY_HIDDEN))
|
||||
emit_insn (gen_symGOTFUNCDESC2reg (reg, orig));
|
||||
else
|
||||
emit_insn (gen_symGOTOFFFUNCDESC2reg (reg, orig));
|
||||
|
||||
@ -1,14 +0,0 @@
|
||||
diff --git a/gcc/gcc.cc b/gcc/gcc.cc
|
||||
index 7837553958b..3c81c5798d8 100644
|
||||
--- a/gcc/gcc.cc
|
||||
+++ b/gcc/gcc.cc
|
||||
@@ -980,7 +980,8 @@ proper position among the other output files. */
|
||||
#ifndef LINK_SSP_SPEC
|
||||
#ifdef TARGET_LIBC_PROVIDES_SSP
|
||||
#define LINK_SSP_SPEC "%{fstack-protector|fstack-protector-all" \
|
||||
- "|fstack-protector-strong|fstack-protector-explicit:}"
|
||||
+ "|fstack-protector-strong|fstack-protector-explicit" \
|
||||
+ ":-lssp_nonshared}"
|
||||
#else
|
||||
#define LINK_SSP_SPEC "%{fstack-protector|fstack-protector-all" \
|
||||
"|fstack-protector-strong|fstack-protector-explicit" \
|
||||
@ -1,346 +0,0 @@
|
||||
diff --git a/gcc/config.gcc b/gcc/config.gcc
|
||||
index 357b0bed067..528add999f2 100644
|
||||
--- a/gcc/config.gcc
|
||||
+++ b/gcc/config.gcc
|
||||
@@ -556,7 +556,7 @@ s390*-*-*)
|
||||
extra_headers="s390intrin.h htmintrin.h htmxlintrin.h vecintrin.h"
|
||||
;;
|
||||
# Note the 'l'; we need to be able to match e.g. "shle" or "shl".
|
||||
-sh[123456789lbe]*-*-* | sh-*-*)
|
||||
+sh[123456789lbej]*-*-* | sh-*-*)
|
||||
cpu_type=sh
|
||||
extra_options="${extra_options} fused-madd.opt"
|
||||
extra_objs="${extra_objs} sh_treg_combine.o sh-mem.o sh_optimize_sett_clrt.o"
|
||||
@@ -3202,18 +3202,18 @@ s390x-ibm-tpf*)
|
||||
extra_options="${extra_options} s390/tpf.opt"
|
||||
tmake_file="${tmake_file} s390/t-s390"
|
||||
;;
|
||||
-sh-*-elf* | sh[12346l]*-*-elf* | \
|
||||
- sh-*-linux* | sh[2346lbe]*-*-linux* | \
|
||||
+sh-*-elf* | sh[12346lj]*-*-elf* | \
|
||||
+ sh-*-linux* | sh[2346lbej]*-*-linux* | \
|
||||
sh-*-netbsdelf* | shl*-*-netbsdelf*)
|
||||
tmake_file="${tmake_file} sh/t-sh sh/t-elf"
|
||||
if test x${with_endian} = x; then
|
||||
case ${target} in
|
||||
- sh[1234]*be-*-* | sh[1234]*eb-*-*) with_endian=big ;;
|
||||
+ sh[j1234]*be-*-* | sh[j1234]*eb-*-*) with_endian=big ;;
|
||||
shbe-*-* | sheb-*-*) with_endian=big,little ;;
|
||||
sh[1234]l* | sh[34]*-*-linux*) with_endian=little ;;
|
||||
shl* | sh*-*-linux* | \
|
||||
sh-superh-elf) with_endian=little,big ;;
|
||||
- sh[1234]*-*-*) with_endian=big ;;
|
||||
+ sh[j1234]*-*-*) with_endian=big ;;
|
||||
*) with_endian=big,little ;;
|
||||
esac
|
||||
fi
|
||||
@@ -3280,6 +3280,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
|
||||
sh2a_nofpu*) sh_cpu_target=sh2a-nofpu ;;
|
||||
sh2a*) sh_cpu_target=sh2a ;;
|
||||
sh2e*) sh_cpu_target=sh2e ;;
|
||||
+ shj2*) sh_cpu_target=shj2;;
|
||||
sh2*) sh_cpu_target=sh2 ;;
|
||||
*) sh_cpu_target=sh1 ;;
|
||||
esac
|
||||
@@ -3301,7 +3302,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
|
||||
sh2a-single-only | sh2a-single | sh2a-nofpu | sh2a | \
|
||||
sh4a-single-only | sh4a-single | sh4a-nofpu | sh4a | sh4al | \
|
||||
sh4-single-only | sh4-single | sh4-nofpu | sh4 | sh4-300 | \
|
||||
- sh3e | sh3 | sh2e | sh2 | sh1) ;;
|
||||
+ sh3e | sh3 | sh2e | sh2 | sh1 | shj2) ;;
|
||||
"") sh_cpu_default=${sh_cpu_target} ;;
|
||||
*) echo "with_cpu=$with_cpu not supported"; exit 1 ;;
|
||||
esac
|
||||
@@ -3310,9 +3311,9 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
|
||||
case ${target} in
|
||||
sh[1234]*) sh_multilibs=${sh_cpu_target} ;;
|
||||
sh-superh-*) sh_multilibs=m4,m4-single,m4-single-only,m4-nofpu ;;
|
||||
- sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4 ;;
|
||||
+ sh*-*-linux*) sh_multilibs=m1,m2,m2a,m3e,m4,mj2 ;;
|
||||
sh*-*-netbsd*) sh_multilibs=m3,m3e,m4 ;;
|
||||
- *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single ;;
|
||||
+ *) sh_multilibs=m1,m2,m2e,m4,m4-single,m4-single-only,m2a,m2a-single,mj2 ;;
|
||||
esac
|
||||
if test x$with_fp = xno; then
|
||||
sh_multilibs="`echo $sh_multilibs|sed -e s/m4/sh4-nofpu/ -e s/,m4-[^,]*//g -e s/,m[23]e// -e s/m2a,m2a-single/m2a-nofpu/ -e s/m5-..m....,//g`"
|
||||
@@ -3327,7 +3328,8 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
|
||||
m1 | m2 | m2e | m3 | m3e | \
|
||||
m4 | m4-single | m4-single-only | m4-nofpu | m4-300 |\
|
||||
m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al | \
|
||||
- m2a | m2a-single | m2a-single-only | m2a-nofpu)
|
||||
+ m2a | m2a-single | m2a-single-only | m2a-nofpu | \
|
||||
+ mj2)
|
||||
# TM_MULTILIB_CONFIG is used by t-sh for the non-endian multilib definition
|
||||
# It is passed to MULTIILIB_OPTIONS verbatim.
|
||||
TM_MULTILIB_CONFIG="${TM_MULTILIB_CONFIG}/${sh_multilib}"
|
||||
@@ -3344,7 +3346,7 @@ sh-*-elf* | sh[12346l]*-*-elf* | \
|
||||
done
|
||||
TM_MULTILIB_CONFIG=`echo $TM_MULTILIB_CONFIG | sed 's:^/::'`
|
||||
if test x${enable_incomplete_targets} = xyes ; then
|
||||
- tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1"
|
||||
+ tm_defines="$tm_defines SUPPORT_SH1=1 SUPPORT_SH2E=1 SUPPORT_SH4=1 SUPPORT_SH4_SINGLE=1 SUPPORT_SH2A=1 SUPPORT_SH2A_SINGLE=1 SUPPORT_SHJ2=1"
|
||||
fi
|
||||
tm_file="$tm_file ./sysroot-suffix.h"
|
||||
tmake_file="$tmake_file t-sysroot-suffix"
|
||||
@@ -5175,6 +5177,8 @@ case "${target}" in
|
||||
;;
|
||||
m4a | m4a-single | m4a-single-only | m4a-nofpu | m4al)
|
||||
;;
|
||||
+ mj2)
|
||||
+ ;;
|
||||
*)
|
||||
echo "Unknown CPU used in --with-cpu=$with_cpu, known values:" 1>&2
|
||||
echo "m1 m2 m2e m3 m3e m4 m4-single m4-single-only m4-nofpu" 1>&2
|
||||
@@ -5385,7 +5389,7 @@ case ${target} in
|
||||
tmake_file="${cpu_type}/t-${cpu_type} ${tmake_file}"
|
||||
;;
|
||||
|
||||
- sh[123456ble]*-*-* | sh-*-*)
|
||||
+ sh[123456blej]*-*-* | sh-*-*)
|
||||
c_target_objs="${c_target_objs} sh-c.o"
|
||||
cxx_target_objs="${cxx_target_objs} sh-c.o"
|
||||
;;
|
||||
diff --git a/gcc/config/sh/sh.cc b/gcc/config/sh/sh.cc
|
||||
index 1564109c942..798c1c1c1a3 100644
|
||||
--- a/gcc/config/sh/sh.cc
|
||||
+++ b/gcc/config/sh/sh.cc
|
||||
@@ -686,6 +686,7 @@ parse_validate_atomic_model_option (const char* str)
|
||||
model_names[sh_atomic_model::hard_llcs] = "hard-llcs";
|
||||
model_names[sh_atomic_model::soft_tcb] = "soft-tcb";
|
||||
model_names[sh_atomic_model::soft_imask] = "soft-imask";
|
||||
+ model_names[sh_atomic_model::hard_cas] = "hard-cas";
|
||||
|
||||
const char* model_cdef_names[sh_atomic_model::num_models];
|
||||
model_cdef_names[sh_atomic_model::none] = "NONE";
|
||||
@@ -693,6 +694,7 @@ parse_validate_atomic_model_option (const char* str)
|
||||
model_cdef_names[sh_atomic_model::hard_llcs] = "HARD_LLCS";
|
||||
model_cdef_names[sh_atomic_model::soft_tcb] = "SOFT_TCB";
|
||||
model_cdef_names[sh_atomic_model::soft_imask] = "SOFT_IMASK";
|
||||
+ model_cdef_names[sh_atomic_model::hard_cas] = "HARD_CAS";
|
||||
|
||||
sh_atomic_model ret;
|
||||
ret.type = sh_atomic_model::none;
|
||||
@@ -771,6 +773,9 @@ got_mode_name:;
|
||||
if (ret.type == sh_atomic_model::soft_imask && TARGET_USERMODE)
|
||||
err_ret ("cannot use atomic model %s in user mode", ret.name);
|
||||
|
||||
+ if (ret.type == sh_atomic_model::hard_cas && !TARGET_SHJ2)
|
||||
+ err_ret ("atomic model %s is only available J2 targets", ret.name);
|
||||
+
|
||||
return ret;
|
||||
|
||||
#undef err_ret
|
||||
@@ -827,6 +832,8 @@ sh_option_override (void)
|
||||
sh_cpu = PROCESSOR_SH2E;
|
||||
if (TARGET_SH2A)
|
||||
sh_cpu = PROCESSOR_SH2A;
|
||||
+ if (TARGET_SHJ2)
|
||||
+ sh_cpu = PROCESSOR_SHJ2;
|
||||
if (TARGET_SH3)
|
||||
sh_cpu = PROCESSOR_SH3;
|
||||
if (TARGET_SH3E)
|
||||
diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h
|
||||
index d2280e2ffe6..3a54a896721 100644
|
||||
--- a/gcc/config/sh/sh.h
|
||||
+++ b/gcc/config/sh/sh.h
|
||||
@@ -85,6 +85,7 @@ extern int code_for_indirect_jump_scratch;
|
||||
#define SUPPORT_SH4_SINGLE 1
|
||||
#define SUPPORT_SH2A 1
|
||||
#define SUPPORT_SH2A_SINGLE 1
|
||||
+#define SUPPORT_SHJ2 1
|
||||
#endif
|
||||
|
||||
#define TARGET_DIVIDE_CALL_DIV1 (sh_div_strategy == SH_DIV_CALL_DIV1)
|
||||
@@ -117,6 +118,7 @@ extern int code_for_indirect_jump_scratch;
|
||||
#define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY)
|
||||
#define SELECT_SH4A (MASK_SH4A | SELECT_SH4)
|
||||
#define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE)
|
||||
+#define SELECT_SHJ2 (MASK_SHJ2 | SELECT_SH2)
|
||||
|
||||
#if SUPPORT_SH1
|
||||
#define SUPPORT_SH2 1
|
||||
@@ -124,6 +126,7 @@ extern int code_for_indirect_jump_scratch;
|
||||
#if SUPPORT_SH2
|
||||
#define SUPPORT_SH3 1
|
||||
#define SUPPORT_SH2A_NOFPU 1
|
||||
+#define SUPPORT_SHJ2 1
|
||||
#endif
|
||||
#if SUPPORT_SH3
|
||||
#define SUPPORT_SH4_NOFPU 1
|
||||
@@ -156,7 +159,7 @@ extern int code_for_indirect_jump_scratch;
|
||||
#define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \
|
||||
| MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \
|
||||
| MASK_HARD_SH4 | MASK_FPU_SINGLE \
|
||||
- | MASK_FPU_SINGLE_ONLY)
|
||||
+ | MASK_FPU_SINGLE_ONLY | MASK_SHJ2)
|
||||
|
||||
/* This defaults us to big-endian. */
|
||||
#ifndef TARGET_ENDIAN_DEFAULT
|
||||
@@ -231,7 +234,8 @@ extern int code_for_indirect_jump_scratch;
|
||||
%{m2a-single:--isa=sh2a} \
|
||||
%{m2a-single-only:--isa=sh2a} \
|
||||
%{m2a-nofpu:--isa=sh2a-nofpu} \
|
||||
-%{m4al:-dsp}"
|
||||
+%{m4al:-dsp} \
|
||||
+%{mj2:-isa=j2}"
|
||||
|
||||
#define ASM_SPEC SH_ASM_SPEC
|
||||
|
||||
@@ -347,6 +351,7 @@ struct sh_atomic_model
|
||||
hard_llcs,
|
||||
soft_tcb,
|
||||
soft_imask,
|
||||
+ hard_cas,
|
||||
|
||||
num_models
|
||||
};
|
||||
@@ -390,6 +395,9 @@ extern const sh_atomic_model& selected_atomic_model (void);
|
||||
#define TARGET_ATOMIC_SOFT_IMASK \
|
||||
(selected_atomic_model ().type == sh_atomic_model::soft_imask)
|
||||
|
||||
+#define TARGET_ATOMIC_HARD_CAS \
|
||||
+ (selected_atomic_model ().type == sh_atomic_model::hard_cas)
|
||||
+
|
||||
#endif // __cplusplus
|
||||
|
||||
#define SUBTARGET_OVERRIDE_OPTIONS (void) 0
|
||||
@@ -1484,7 +1492,7 @@ extern bool current_function_interrupt;
|
||||
|
||||
/* Nonzero if the target supports dynamic shift instructions
|
||||
like shad and shld. */
|
||||
-#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A)
|
||||
+#define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A || TARGET_SHJ2)
|
||||
|
||||
/* The cost of using the dynamic shift insns (shad, shld) are the same
|
||||
if they are available. If they are not available a library function will
|
||||
@@ -1747,6 +1755,7 @@ enum processor_type {
|
||||
PROCESSOR_SH2,
|
||||
PROCESSOR_SH2E,
|
||||
PROCESSOR_SH2A,
|
||||
+ PROCESSOR_SHJ2,
|
||||
PROCESSOR_SH3,
|
||||
PROCESSOR_SH3E,
|
||||
PROCESSOR_SH4,
|
||||
diff --git a/gcc/config/sh/sh.opt b/gcc/config/sh/sh.opt
|
||||
index b4755a812f3..0989a1c18da 100644
|
||||
--- a/gcc/config/sh/sh.opt
|
||||
+++ b/gcc/config/sh/sh.opt
|
||||
@@ -65,6 +65,10 @@ m2e
|
||||
Target RejectNegative Condition(SUPPORT_SH2E)
|
||||
Generate SH2e code.
|
||||
|
||||
+mj2
|
||||
+Target RejectNegative Mask(SHJ2) Condition(SUPPORT_SHJ2)
|
||||
+Generate J2 code.
|
||||
+
|
||||
m3
|
||||
Target RejectNegative Mask(SH3) Condition(SUPPORT_SH3)
|
||||
Generate SH3 code.
|
||||
diff --git a/gcc/config/sh/sync.md b/gcc/config/sh/sync.md
|
||||
index 2b43f8edb86..118fc5d06db 100644
|
||||
--- a/gcc/config/sh/sync.md
|
||||
+++ b/gcc/config/sh/sync.md
|
||||
@@ -240,6 +240,9 @@
|
||||
|| (TARGET_SH4A && <MODE>mode == SImode && !TARGET_ATOMIC_STRICT))
|
||||
atomic_insn = gen_atomic_compare_and_swap<mode>_hard (old_val, mem,
|
||||
exp_val, new_val);
|
||||
+ else if (TARGET_ATOMIC_HARD_CAS && <MODE>mode == SImode)
|
||||
+ atomic_insn = gen_atomic_compare_and_swap<mode>_cas (old_val, mem,
|
||||
+ exp_val, new_val);
|
||||
else if (TARGET_ATOMIC_SOFT_GUSA)
|
||||
atomic_insn = gen_atomic_compare_and_swap<mode>_soft_gusa (old_val, mem,
|
||||
exp_val, new_val);
|
||||
@@ -306,6 +309,57 @@
|
||||
}
|
||||
[(set_attr "length" "14")])
|
||||
|
||||
+(define_expand "atomic_compare_and_swapsi_cas"
|
||||
+ [(set (match_operand:SI 0 "register_operand" "=r")
|
||||
+ (unspec_volatile:SI
|
||||
+ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra")
|
||||
+ (match_operand:SI 2 "register_operand" "r")
|
||||
+ (match_operand:SI 3 "register_operand" "r")]
|
||||
+ UNSPECV_CMPXCHG_1))]
|
||||
+ "TARGET_ATOMIC_HARD_CAS"
|
||||
+{
|
||||
+ rtx mem = gen_rtx_REG (SImode, 0);
|
||||
+ emit_move_insn (mem, force_reg (SImode, XEXP (operands[1], 0)));
|
||||
+ emit_insn (gen_shj2_cas (operands[0], mem, operands[2], operands[3]));
|
||||
+ DONE;
|
||||
+})
|
||||
+
|
||||
+(define_insn "shj2_cas"
|
||||
+ [(set (match_operand:SI 0 "register_operand" "=&r")
|
||||
+ (unspec_volatile:SI
|
||||
+ [(match_operand:SI 1 "register_operand" "=r")
|
||||
+ (match_operand:SI 2 "register_operand" "r")
|
||||
+ (match_operand:SI 3 "register_operand" "0")]
|
||||
+ UNSPECV_CMPXCHG_1))
|
||||
+ (set (reg:SI T_REG)
|
||||
+ (unspec_volatile:SI [(const_int 0)] UNSPECV_CMPXCHG_3))]
|
||||
+ "TARGET_ATOMIC_HARD_CAS"
|
||||
+ "cas.l %2,%0,@%1"
|
||||
+ [(set_attr "length" "2")]
|
||||
+)
|
||||
+
|
||||
+(define_expand "atomic_compare_and_swapqi_cas"
|
||||
+ [(set (match_operand:SI 0 "arith_reg_dest" "=&r")
|
||||
+ (unspec_volatile:SI
|
||||
+ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra")
|
||||
+ (match_operand:SI 2 "arith_operand" "rI08")
|
||||
+ (match_operand:SI 3 "arith_operand" "rI08")]
|
||||
+ UNSPECV_CMPXCHG_1))]
|
||||
+ "TARGET_ATOMIC_HARD_CAS"
|
||||
+{FAIL;}
|
||||
+)
|
||||
+
|
||||
+(define_expand "atomic_compare_and_swaphi_cas"
|
||||
+ [(set (match_operand:SI 0 "arith_reg_dest" "=&r")
|
||||
+ (unspec_volatile:SI
|
||||
+ [(match_operand:SI 1 "atomic_mem_operand_0" "=Sra")
|
||||
+ (match_operand:SI 2 "arith_operand" "rI08")
|
||||
+ (match_operand:SI 3 "arith_operand" "rI08")]
|
||||
+ UNSPECV_CMPXCHG_1))]
|
||||
+ "TARGET_ATOMIC_HARD_CAS"
|
||||
+{FAIL;}
|
||||
+)
|
||||
+
|
||||
;; The QIHImode llcs patterns modify the address register of the memory
|
||||
;; operand. In order to express that, we have to open code the memory
|
||||
;; operand. Initially the insn is expanded like every other atomic insn
|
||||
diff --git a/gcc/config/sh/t-sh b/gcc/config/sh/t-sh
|
||||
index 888f8ff7f25..29fd6ae45fd 100644
|
||||
--- a/gcc/config/sh/t-sh
|
||||
+++ b/gcc/config/sh/t-sh
|
||||
@@ -50,7 +50,8 @@ MULTILIB_MATCHES = $(shell \
|
||||
m2e,m3e,m4-single-only,m4-100-single-only,m4-200-single-only,m4-300-single-only,m4a-single-only \
|
||||
m2a-single,m2a-single-only \
|
||||
m4-single,m4-100-single,m4-200-single,m4-300-single,m4a-single \
|
||||
- m4,m4-100,m4-200,m4-300,m4a; do \
|
||||
+ m4,m4-100,m4-200,m4-300,m4a \
|
||||
+ mj2; do \
|
||||
subst= ; \
|
||||
for lib in `echo $$abi|tr , ' '` ; do \
|
||||
if test "`echo $$multilibs|sed s/$$lib//`" != "$$multilibs"; then \
|
||||
@@ -63,9 +64,9 @@ MULTILIB_MATCHES = $(shell \
|
||||
|
||||
# SH1 and SH2A support big endian only.
|
||||
ifeq ($(DEFAULT_ENDIAN),ml)
|
||||
-MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG)
|
||||
+MULTILIB_EXCEPTIONS = m1 ml/m1 m2a* ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG)
|
||||
else
|
||||
-MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* $(TM_MULTILIB_EXCEPTIONS_CONFIG)
|
||||
+MULTILIB_EXCEPTIONS = ml/m1 ml/m2a* ml/mj2 $(TM_MULTILIB_EXCEPTIONS_CONFIG)
|
||||
endif
|
||||
|
||||
MULTILIB_OSDIRNAMES = \
|
||||
@@ -87,7 +88,8 @@ MULTILIB_OSDIRNAMES = \
|
||||
m4a-single-only=!m4a-single-only $(OTHER_ENDIAN)/m4a-single-only=!$(OTHER_ENDIAN)/m4a-single-only \
|
||||
m4a-single=!m4a-single $(OTHER_ENDIAN)/m4a-single=!$(OTHER_ENDIAN)/m4a-single \
|
||||
m4a=!m4a $(OTHER_ENDIAN)/m4a=!$(OTHER_ENDIAN)/m4a \
|
||||
- m4al=!m4al $(OTHER_ENDIAN)/m4al=!$(OTHER_ENDIAN)/m4al
|
||||
+ m4al=!m4al $(OTHER_ENDIAN)/m4al=!$(OTHER_ENDIAN)/m4al \
|
||||
+ mj2=!j2
|
||||
|
||||
$(out_object_file): gt-sh.h
|
||||
gt-sh.h : s-gtype ; @true
|
||||
@ -1,92 +0,0 @@
|
||||
diff --git a/gcc/common.opt b/gcc/common.opt
|
||||
index a75b44ee47e..7c564818b49 100644
|
||||
--- a/gcc/common.opt
|
||||
+++ b/gcc/common.opt
|
||||
@@ -3473,11 +3473,11 @@ Driver
|
||||
|
||||
no-pie
|
||||
Driver RejectNegative Negative(shared)
|
||||
-Don't create a dynamically linked position independent executable.
|
||||
+Don't create a position independent executable.
|
||||
|
||||
pie
|
||||
Driver RejectNegative Negative(no-pie)
|
||||
-Create a dynamically linked position independent executable.
|
||||
+Create a position independent executable.
|
||||
|
||||
static-pie
|
||||
Driver RejectNegative Negative(pie)
|
||||
diff --git a/gcc/config/gnu-user.h b/gcc/config/gnu-user.h
|
||||
index 5ebbf42a13d..bb907d8e89a 100644
|
||||
--- a/gcc/config/gnu-user.h
|
||||
+++ b/gcc/config/gnu-user.h
|
||||
@@ -51,13 +51,12 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
|
||||
#define GNU_USER_TARGET_STARTFILE_SPEC \
|
||||
"%{shared:; \
|
||||
pg|p|profile:%{static-pie:grcrt1.o%s;:gcrt1.o%s}; \
|
||||
- static:crt1.o%s; \
|
||||
- static-pie:rcrt1.o%s; \
|
||||
+ static|static-pie:%{" PIE_SPEC ":rcrt1.o%s;:crt1.o%s}; \
|
||||
" PIE_SPEC ":Scrt1.o%s; \
|
||||
:crt1.o%s} " \
|
||||
GNU_USER_TARGET_CRTI " \
|
||||
- %{static:crtbeginT.o%s; \
|
||||
- shared|static-pie|" PIE_SPEC ":crtbeginS.o%s; \
|
||||
+ %{shared|" PIE_SPEC ":crtbeginS.o%s; \
|
||||
+ static:crtbeginT.o%s; \
|
||||
:crtbegin.o%s} \
|
||||
%{fvtable-verify=none:%s; \
|
||||
fvtable-verify=preinit:vtv_start_preinit.o%s; \
|
||||
@@ -73,11 +72,11 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
|
||||
GNU userspace "finalizer" file, `crtn.o'. */
|
||||
|
||||
#define GNU_USER_TARGET_ENDFILE_SPEC \
|
||||
- "%{!static:%{fvtable-verify=none:%s; \
|
||||
+ "%{static|static-pie:; \
|
||||
+ fvtable-verify=none:%s; \
|
||||
fvtable-verify=preinit:vtv_end_preinit.o%s; \
|
||||
- fvtable-verify=std:vtv_end.o%s}} \
|
||||
- %{static:crtend.o%s; \
|
||||
- shared|static-pie|" PIE_SPEC ":crtendS.o%s; \
|
||||
+ fvtable-verify=std:vtv_end.o%s} \
|
||||
+ %{shared|" PIE_SPEC ":crtendS.o%s; \
|
||||
:crtend.o%s} " \
|
||||
GNU_USER_TARGET_CRTN " " \
|
||||
CRTOFFLOADEND
|
||||
@@ -106,7 +105,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
|
||||
#define LIB_SPEC GNU_USER_TARGET_LIB_SPEC
|
||||
|
||||
#if defined(HAVE_LD_EH_FRAME_HDR)
|
||||
-#define LINK_EH_SPEC "%{!static|static-pie:--eh-frame-hdr} "
|
||||
+#define LINK_EH_SPEC "%{!static|" PIE_SPEC ":--eh-frame-hdr} "
|
||||
#endif
|
||||
|
||||
#define GNU_USER_TARGET_LINK_GCC_C_SEQUENCE_SPEC \
|
||||
diff --git a/gcc/gcc.cc b/gcc/gcc.cc
|
||||
index 3c81c5798d8..cd96eac5d12 100644
|
||||
--- a/gcc/gcc.cc
|
||||
+++ b/gcc/gcc.cc
|
||||
@@ -1010,7 +1010,7 @@ proper position among the other output files. */
|
||||
#define NO_FPIE_AND_FPIC_SPEC NO_FPIE_SPEC "|" NO_FPIC_SPEC
|
||||
#define FPIE_OR_FPIC_SPEC NO_FPIE_AND_FPIC_SPEC ":;"
|
||||
#else
|
||||
-#define PIE_SPEC "pie"
|
||||
+#define PIE_SPEC "pie|static-pie"
|
||||
#define FPIE1_SPEC "fpie"
|
||||
#define NO_FPIE1_SPEC FPIE1_SPEC ":;"
|
||||
#define FPIE2_SPEC "fPIE"
|
||||
@@ -1034,12 +1034,12 @@ proper position among the other output files. */
|
||||
#ifndef LINK_PIE_SPEC
|
||||
#ifdef HAVE_LD_PIE
|
||||
#ifndef LD_PIE_SPEC
|
||||
-#define LD_PIE_SPEC "-pie"
|
||||
+#define LD_PIE_SPEC "-pie %{static|static-pie:--no-dynamic-linker -z text -Bsymbolic}"
|
||||
#endif
|
||||
#else
|
||||
#define LD_PIE_SPEC ""
|
||||
#endif
|
||||
-#define LINK_PIE_SPEC "%{static|shared|r:;" PIE_SPEC ":" LD_PIE_SPEC "} "
|
||||
+#define LINK_PIE_SPEC "%{shared|r:;" PIE_SPEC ":" LD_PIE_SPEC "} "
|
||||
#endif
|
||||
|
||||
#ifndef LINK_BUILDID_SPEC
|
||||
@ -1,20 +0,0 @@
|
||||
diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md
|
||||
index 59a456cd496..dbfddea41bd 100644
|
||||
--- a/gcc/config/m68k/m68k.md
|
||||
+++ b/gcc/config/m68k/m68k.md
|
||||
@@ -4174,13 +4174,13 @@
|
||||
(define_expand "sqrt<mode>2"
|
||||
[(set (match_operand:FP 0 "nonimmediate_operand" "")
|
||||
(sqrt:FP (match_operand:FP 1 "general_operand" "")))]
|
||||
- "TARGET_HARD_FLOAT"
|
||||
+ "(TARGET_68881 && TARGET_68040) || TARGET_COLDFIRE_FPU"
|
||||
"")
|
||||
|
||||
(define_insn "sqrt<mode>2_68881"
|
||||
[(set (match_operand:FP 0 "nonimmediate_operand" "=f")
|
||||
(sqrt:FP (match_operand:FP 1 "general_operand" "f<FP:dreg>m")))]
|
||||
- "TARGET_68881"
|
||||
+ "TARGET_68881 && TARGET_68040"
|
||||
{
|
||||
if (FP_REG_P (operands[1]))
|
||||
return "f<FP:round>sqrt%.x %1,%0";
|
||||
@ -1,8 +0,0 @@
|
||||
--- a/libstdc++-v3/ChangeLog 2024-03-13 18:04:21.050801063 -0400
|
||||
+++ b/libstdc++-v3/ChangeLog 2024-03-13 18:04:25.665836804 -0400
|
||||
@@ -4068,4 +4068,4 @@
|
||||
|
||||
Copying and distribution of this file, with or without modification,
|
||||
are permitted in any medium without royalty provided the copyright
|
||||
-notice and this notice are preserved.
|
||||
+notice and this notice are preserved.
|
||||
@ -1,11 +0,0 @@
|
||||
--- a/libgcc/unwind-pe.h 2024-03-14 05:59:53.754073149 +0900
|
||||
+++ b/libgcc/unwind-pe.h 2024-03-14 06:00:41.226074492 +0900
|
||||
@@ -262,7 +262,7 @@
|
||||
|
||||
if (result != 0)
|
||||
{
|
||||
-#if __FDPIC__
|
||||
+#if __FDPIC__ && __arm__
|
||||
/* FDPIC relative addresses imply taking the GOT address
|
||||
into account. */
|
||||
if ((encoding & DW_EH_PE_pcrel) && (encoding & DW_EH_PE_indirect))
|
||||
@ -1,38 +0,0 @@
|
||||
--- a/libgcc/crtstuff.c 2023-05-29 17:46:32.000000000 +0900
|
||||
+++ b/libgcc/crtstuff.c 2024-03-14 06:03:42.398079615 +0900
|
||||
@@ -441,17 +441,9 @@
|
||||
#ifdef FINI_SECTION_ASM_OP
|
||||
CRT_CALL_STATIC_FUNCTION (FINI_SECTION_ASM_OP, __do_global_dtors_aux)
|
||||
#elif defined (FINI_ARRAY_SECTION_ASM_OP)
|
||||
-#if defined(__FDPIC__)
|
||||
-__asm__("\t.equ\t__do_global_dtors_aux_alias, __do_global_dtors_aux\n");
|
||||
-extern char __do_global_dtors_aux_alias;
|
||||
-static void *__do_global_dtors_aux_fini_array_entry[]
|
||||
-__attribute__ ((__used__, section(".fini_array"), aligned(sizeof(void *))))
|
||||
- = { &__do_global_dtors_aux_alias };
|
||||
-#else /* defined(__FDPIC__) */
|
||||
static func_ptr __do_global_dtors_aux_fini_array_entry[]
|
||||
__attribute__ ((__used__, section(".fini_array"),
|
||||
aligned(__alignof__(func_ptr)))) = { __do_global_dtors_aux };
|
||||
-#endif /* defined(__FDPIC__) */
|
||||
#else /* !FINI_SECTION_ASM_OP && !FINI_ARRAY_SECTION_ASM_OP */
|
||||
static void __attribute__((used))
|
||||
__do_global_dtors_aux_1 (void)
|
||||
@@ -494,17 +486,9 @@
|
||||
#ifdef __LIBGCC_INIT_SECTION_ASM_OP__
|
||||
CRT_CALL_STATIC_FUNCTION (__LIBGCC_INIT_SECTION_ASM_OP__, frame_dummy)
|
||||
#else /* defined(__LIBGCC_INIT_SECTION_ASM_OP__) */
|
||||
-#if defined(__FDPIC__)
|
||||
-__asm__("\t.equ\t__frame_dummy_alias, frame_dummy\n");
|
||||
-extern char __frame_dummy_alias;
|
||||
-static void *__frame_dummy_init_array_entry[]
|
||||
-__attribute__ ((__used__, section(".init_array"), aligned(sizeof(void *))))
|
||||
- = { &__frame_dummy_alias };
|
||||
-#else /* defined(__FDPIC__) */
|
||||
static func_ptr __frame_dummy_init_array_entry[]
|
||||
__attribute__ ((__used__, section(".init_array"),
|
||||
aligned(__alignof__(func_ptr)))) = { frame_dummy };
|
||||
-#endif /* defined(__FDPIC__) */
|
||||
#endif /* !defined(__LIBGCC_INIT_SECTION_ASM_OP__) */
|
||||
#endif /* USE_EH_FRAME_REGISTRY || USE_TM_CLONE_REGISTRY */
|
||||
|
||||
@ -1,12 +0,0 @@
|
||||
--- gcc-11.4.0/gcc/config/sh/sh.cc.orig 2024-04-04 05:52:42.125373614 +0900
|
||||
+++ gcc-11.4.0/gcc/config/sh/sh.cc 2024-04-04 22:54:01.875106654 +0900
|
||||
@@ -9147,7 +9147,7 @@
|
||||
{
|
||||
/* Weak functions may be NULL which doesn't work with
|
||||
GOTOFFFUNCDESC because the runtime offset is not known. */
|
||||
- if (SYMBOL_REF_WEAK (orig))
|
||||
+ if (SYMBOL_REF_WEAK (orig) || (TREE_PUBLIC(SYMBOL_REF_DECL(orig)) && DECL_VISIBILITY (SYMBOL_REF_DECL(orig)) != VISIBILITY_HIDDEN))
|
||||
emit_insn (gen_symGOTFUNCDESC2reg (reg, orig));
|
||||
else
|
||||
emit_insn (gen_symGOTOFFFUNCDESC2reg (reg, orig));
|
||||
|
||||
@ -1,14 +0,0 @@
|
||||
diff --git a/gcc/gcc.cc b/gcc/gcc.cc
|
||||
index 7837553958b..3c81c5798d8 100644
|
||||
--- a/gcc/gcc.cc
|
||||
+++ b/gcc/gcc.cc
|
||||
@@ -980,7 +980,8 @@ proper position among the other output files. */
|
||||
#ifndef LINK_SSP_SPEC
|
||||
#ifdef TARGET_LIBC_PROVIDES_SSP
|
||||
#define LINK_SSP_SPEC "%{fstack-protector|fstack-protector-all" \
|
||||
- "|fstack-protector-strong|fstack-protector-explicit:}"
|
||||
+ "|fstack-protector-strong|fstack-protector-explicit" \
|
||||
+ ":-lssp_nonshared}"
|
||||
#else
|
||||
#define LINK_SSP_SPEC "%{fstack-protector|fstack-protector-all" \
|
||||
"|fstack-protector-strong|fstack-protector-explicit" \
|
||||
@ -1,30 +0,0 @@
|
||||
diff --git a/gcc/config/i386/pmm_malloc.h b/gcc/config/i386/pmm_malloc.h
|
||||
index 1b0bfe37852..d7b2b19bb3c 100644
|
||||
--- a/gcc/config/i386/pmm_malloc.h
|
||||
+++ b/gcc/config/i386/pmm_malloc.h
|
||||
@@ -27,12 +27,13 @@
|
||||
#include <stdlib.h>
|
||||
|
||||
/* We can't depend on <stdlib.h> since the prototype of posix_memalign
|
||||
- may not be visible. */
|
||||
+ may not be visible and we can't pollute the namespace either. */
|
||||
#ifndef __cplusplus
|
||||
-extern int posix_memalign (void **, size_t, size_t);
|
||||
+extern int _mm_posix_memalign (void **, size_t, size_t)
|
||||
#else
|
||||
-extern "C" int posix_memalign (void **, size_t, size_t) throw ();
|
||||
+extern "C" int _mm_posix_memalign (void **, size_t, size_t) throw ()
|
||||
#endif
|
||||
+__asm__("posix_memalign");
|
||||
|
||||
static __inline void *
|
||||
_mm_malloc (size_t __size, size_t __alignment)
|
||||
@@ -42,7 +43,7 @@ _mm_malloc (size_t __size, size_t __alignment)
|
||||
return malloc (__size);
|
||||
if (__alignment == 2 || (sizeof (void *) == 8 && __alignment == 4))
|
||||
__alignment = sizeof (void *);
|
||||
- if (posix_memalign (&__ptr, __alignment, __size) == 0)
|
||||
+ if (_mm_posix_memalign (&__ptr, __alignment, __size) == 0)
|
||||
return __ptr;
|
||||
else
|
||||
return NULL;
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user