a3fe76d73f
[ Upstream commit a9b7c84d22fb1687d63ca2a386773015cf59436b ]
The CLKOUTn may be fed from PLL1/2/3, but the PLL1/2/3 has to be enabled
first by setting PLL_CLKE bit 11 in CCM_ANALOG_SYS_PLLn_GEN_CTRL register.
The CCM_ANALOG_SYS_PLLn_GEN_CTRL bit 11 is modeled by plln_out clock. Fix
the clock tree and place the clkout1/2 under plln_sel instead of plain plln
to let the clock subsystem correctly control the bit 11 and enable the PLL
in case the CLKOUTn is supplied by PLL1/2/3.
Fixes:
|
||
|---|---|---|
| .. | ||
| clk-busy.c | ||
| clk-composite-7ulp.c | ||
| clk-composite-8m.c | ||
| clk-composite-93.c | ||
| clk-cpu.c | ||
| clk-divider-gate.c | ||
| clk-fixup-div.c | ||
| clk-fixup-mux.c | ||
| clk-frac-pll.c | ||
| clk-fracn-gppll.c | ||
| clk-gate2.c | ||
| clk-gate-93.c | ||
| clk-gate-exclusive.c | ||
| clk-imx1.c | ||
| clk-imx5.c | ||
| clk-imx6q.c | ||
| clk-imx6sl.c | ||
| clk-imx6sll.c | ||
| clk-imx6sx.c | ||
| clk-imx6ul.c | ||
| clk-imx7d.c | ||
| clk-imx7ulp.c | ||
| clk-imx8dxl-rsrc.c | ||
| clk-imx8mm.c | ||
| clk-imx8mn.c | ||
| clk-imx8mp.c | ||
| clk-imx8mq.c | ||
| clk-imx8qm-rsrc.c | ||
| clk-imx8qxp-lpcg.c | ||
| clk-imx8qxp-lpcg.h | ||
| clk-imx8qxp-rsrc.c | ||
| clk-imx8qxp.c | ||
| clk-imx8ulp.c | ||
| clk-imx25.c | ||
| clk-imx27.c | ||
| clk-imx31.c | ||
| clk-imx35.c | ||
| clk-imx93.c | ||
| clk-imxrt1050.c | ||
| clk-lpcg-scu.c | ||
| clk-pfd.c | ||
| clk-pfdv2.c | ||
| clk-pll14xx.c | ||
| clk-pllv1.c | ||
| clk-pllv2.c | ||
| clk-pllv3.c | ||
| clk-pllv4.c | ||
| clk-scu.c | ||
| clk-scu.h | ||
| clk-sscg-pll.c | ||
| clk-vf610.c | ||
| clk.c | ||
| clk.h | ||
| Kconfig | ||
| Makefile | ||