hamza.kesraoui/sst-linux
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

clk: samsung: exynos7885: do not define number of clocks in bindings

Browse Source 
[ Upstream commit ef4923c8e0523d83b7cd4918760e03b03b2b08ad ]

Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously.  Therefore these numbers of
clocks should not be in the bindings, as that prevents changing them.

Define number of clocks per each clock controller inside the driver
directly.

Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20230808082738.122804-9-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Stable-dep-of: 217a5f23c290 ("clk: samsung: exynos7885: Update CLKS_NR_FSYS after bindings fix")
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Krzysztof Kozlowski 2023-08-08 10:27:35 +02:00 committed by Greg Kroah-Hartman
parent 4fab87aa79
commit cfecad07c1
1 changed files with 10 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
drivers/clk/samsung/clk-exynos7885.c
View File

@ -17,6 +17,12 @@
#include "clk.h"
#include "clk-exynos-arm64.h"
/* NOTE: Must be equal to the last clock ID increased by one */
#define CLKS_NR_TOP (CLK_GOUT_FSYS_USB30DRD + 1)
#define CLKS_NR_CORE (CLK_GOUT_TREX_P_CORE_PCLK_P_CORE + 1)
#define CLKS_NR_PERI (CLK_GOUT_WDT1_PCLK + 1)
#define CLKS_NR_FSYS (CLK_GOUT_MMC_SDIO_SDCLKIN + 1)
/* ---- CMU_TOP ------------------------------------------------------------- */
/* Register Offset definitions for CMU_TOP (0x12060000) */
@ -334,7 +340,7 @@ static const struct samsung_cmu_info top_cmu_info __initconst = {
.nr_div_clks = ARRAY_SIZE(top_div_clks),
.gate_clks = top_gate_clks,
.nr_gate_clks = ARRAY_SIZE(top_gate_clks),
.nr_clk_ids = TOP_NR_CLK,
.nr_clk_ids = CLKS_NR_TOP,
.clk_regs = top_clk_regs,
.nr_clk_regs = ARRAY_SIZE(top_clk_regs),
};
@ -553,7 +559,7 @@ static const struct samsung_cmu_info peri_cmu_info __initconst = {
.nr_mux_clks = ARRAY_SIZE(peri_mux_clks),
.gate_clks = peri_gate_clks,
.nr_gate_clks = ARRAY_SIZE(peri_gate_clks),
.nr_clk_ids = PERI_NR_CLK,
.nr_clk_ids = CLKS_NR_PERI,
.clk_regs = peri_clk_regs,
.nr_clk_regs = ARRAY_SIZE(peri_clk_regs),
.clk_name = "dout_peri_bus",
@ -662,7 +668,7 @@ static const struct samsung_cmu_info core_cmu_info __initconst = {
.nr_div_clks = ARRAY_SIZE(core_div_clks),
.gate_clks = core_gate_clks,
.nr_gate_clks = ARRAY_SIZE(core_gate_clks),
.nr_clk_ids = CORE_NR_CLK,
.nr_clk_ids = CLKS_NR_CORE,
.clk_regs = core_clk_regs,
.nr_clk_regs = ARRAY_SIZE(core_clk_regs),
.clk_name = "dout_core_bus",
@ -744,7 +750,7 @@ static const struct samsung_cmu_info fsys_cmu_info __initconst = {
.nr_mux_clks = ARRAY_SIZE(fsys_mux_clks),
.gate_clks = fsys_gate_clks,
.nr_gate_clks = ARRAY_SIZE(fsys_gate_clks),
.nr_clk_ids = FSYS_NR_CLK,
.nr_clk_ids = CLKS_NR_FSYS,
.clk_regs = fsys_clk_regs,
.nr_clk_regs = ARRAY_SIZE(fsys_clk_regs),
.clk_name = "dout_fsys_bus",