ths 00a709c7b9 Fix mips FPU emulation, 32 bit data types are allowed to use odd registers. ...

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2454 c046a42c-6fe2-441c-8c8c-71466251a162

2007-02-27 19:27:51 +00:00

..

cpu.h

Replace TLSZ with TARGET_FMT_lx.

2007-02-20 23:37:21 +00:00

exec.h

Sparc arm/mips/sparc register patch, by Martin Bochnig.

2007-02-02 01:03:34 +00:00

fop_template.c

Preliminiary MIPS64 support, disabled by default due to performance impact.

2006-12-21 01:19:56 +00:00

helper.c

Replace TLSZ with TARGET_FMT_lx.

2007-02-20 23:37:21 +00:00

mips-defs.h

Preliminiary MIPS64 support, disabled by default due to performance impact.

2006-12-21 01:19:56 +00:00

op_helper_mem.c

Replace TLSZ with TARGET_FMT_lx.

2007-02-20 23:37:21 +00:00

op_helper.c

Replace TLSZ with TARGET_FMT_lx.

2007-02-20 23:37:21 +00:00

op_mem.c

Preliminiary MIPS64 support, disabled by default due to performance impact.

2006-12-21 01:19:56 +00:00

op_template.c

Preliminiary MIPS64 support, disabled by default due to performance impact.

2006-12-21 01:19:56 +00:00

op.c

Fix mips FPU emulation, 32 bit data types are allowed to use odd registers.

2007-02-27 19:27:51 +00:00

TODO

Update MIPS TODO.

2007-02-02 02:56:33 +00:00

translate.c

Fix mips FPU emulation, 32 bit data types are allowed to use odd registers.

2007-02-27 19:27:51 +00:00