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x86: Work around SMI migration breakages

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Migration from a 2.3.0 qemu results in a reboot on the receiving QEMU
due to a disagreement about SM (System management) interrupts.

2.3.0 didn't have much SMI support, but it did set CPU_INTERRUPT_SMI
and this gets into the migration stream, but on 2.3.0 it
never got delivered.

~2.4.0 SMI interrupt support was added but was broken - so
that when a 2.3.0 stream was received it cleared the CPU_INTERRUPT_SMI
but never actually caused an interrupt.

The SMI delivery was recently fixed by 68c6efe07a, but the
effect now is that an incoming 2.3.0 stream takes the interrupt it
had flagged but it's bios can't actually handle it(I think
partly due to the original interrupt not being taken during boot?).
The consequence is a triple(?) fault and a reboot.

Tested from:
  2.3.1 -M 2.3.0
  2.7.0 -M 2.3.0
  2.8.0 -M 2.3.0
  2.8.0 -M 2.8.0

This corresponds to RH bugzilla entry 1420679.

Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Message-Id: <20170223133441.16010-1-dgilbert@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Dr. David Alan Gilbert 2017-02-23 13:34:41 +00:00 committed by Paolo Bonzini
parent f20e6f8cd4
commit fc3a1fd74f
4 changed files with 15 additions and 1 deletions
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4
include/hw/i386/pc.h
View File

@ -623,6 +623,10 @@ bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
.driver = "Broadwell-noTSX" "-" TYPE_X86_CPU,\ .driver = "Broadwell-noTSX" "-" TYPE_X86_CPU,\
.property = "xlevel",\ .property = "xlevel",\
.value = stringify(0x8000000a),\ .value = stringify(0x8000000a),\
},{\
.driver = TYPE_X86_CPU,\
.property = "kvm-no-smi-migration",\
.value = "on",\
}, },
#define PC_COMPAT_2_2 \ #define PC_COMPAT_2_2 \

2
target/i386/cpu.c
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@ -3983,6 +3983,8 @@ static Property x86_cpu_properties[] = {
DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false), DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true), DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
DEFINE_PROP_BOOL("kvm-no-smi-migration", X86CPU, kvm_no_smi_migration,
false),
DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true), DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
DEFINE_PROP_END_OF_LIST() DEFINE_PROP_END_OF_LIST()
}; };

3
target/i386/cpu.h
View File

@ -1255,6 +1255,9 @@ struct X86CPU {
/* if true override the phys_bits value with a value read from the host */ /* if true override the phys_bits value with a value read from the host */
bool host_phys_bits; bool host_phys_bits;
/* Stop SMI delivery for migration compatibility with old machines */
bool kvm_no_smi_migration;
/* Number of physical address bits supported */ /* Number of physical address bits supported */
uint32_t phys_bits; uint32_t phys_bits;

5
target/i386/kvm.c
View File

@ -2492,8 +2492,13 @@ static int kvm_put_vcpu_events(X86CPU *cpu, int level)
events.smi.pending = 0; events.smi.pending = 0;
events.smi.latched_init = 0; events.smi.latched_init = 0;
} }
/* Stop SMI delivery on old machine types to avoid a reboot
* on an inward migration of an old VM.
*/
if (!cpu->kvm_no_smi_migration) {
events.flags |= KVM_VCPUEVENT_VALID_SMM; events.flags |= KVM_VCPUEVENT_VALID_SMM;
} }
}
if (level >= KVM_PUT_RESET_STATE) { if (level >= KVM_PUT_RESET_STATE) {
events.flags |= events.flags |=