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pl041: Rename pl041_state to PL041State

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Reviewed-by: Hu Tao <hutao@cn.fujitsu.com>
[AF: Split off renaming from QOM cast changes]
Signed-off-by: Andreas Färber <afaerber@suse.de>
This commit is contained in:
Andreas Färber 2013-07-27 19:45:52 +02:00
parent 922cc6010e
commit baae672597
1 changed files with 19 additions and 18 deletions
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37
hw/audio/pl041.c
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@ -70,7 +70,7 @@ typedef struct {
uint8_t rx_sample_size; uint8_t rx_sample_size;
} pl041_channel; } pl041_channel;
typedef struct { typedef struct PL041State {
SysBusDevice busdev; SysBusDevice busdev;
MemoryRegion iomem; MemoryRegion iomem;
qemu_irq irq; qemu_irq irq;
@ -80,7 +80,7 @@ typedef struct {
pl041_regfile regs; pl041_regfile regs;
pl041_channel fifo1; pl041_channel fifo1;
lm4549_state codec; lm4549_state codec;
} pl041_state; } PL041State;
static const unsigned char pl041_default_id[8] = { static const unsigned char pl041_default_id[8] = {
@ -107,7 +107,7 @@ static const char *get_reg_name(hwaddr offset)
} }
#endif #endif
static uint8_t pl041_compute_periphid3(pl041_state *s) static uint8_t pl041_compute_periphid3(PL041State *s)
{ {
uint8_t id3 = 1; /* One channel */ uint8_t id3 = 1; /* One channel */
@ -142,7 +142,7 @@ static uint8_t pl041_compute_periphid3(pl041_state *s)
return id3; return id3;
} }
static void pl041_reset(pl041_state *s) static void pl041_reset(PL041State *s)
{ {
DBG_L1("pl041_reset\n"); DBG_L1("pl041_reset\n");
@ -156,7 +156,7 @@ static void pl041_reset(pl041_state *s)
} }
static void pl041_fifo1_write(pl041_state *s, uint32_t value) static void pl041_fifo1_write(PL041State *s, uint32_t value)
{ {
pl041_channel *channel = &s->fifo1; pl041_channel *channel = &s->fifo1;
pl041_fifo *fifo = &s->fifo1.tx_fifo; pl041_fifo *fifo = &s->fifo1.tx_fifo;
@ -239,7 +239,7 @@ static void pl041_fifo1_write(pl041_state *s, uint32_t value)
DBG_L2("fifo1_push sr1 = 0x%08x\n", s->regs.sr1); DBG_L2("fifo1_push sr1 = 0x%08x\n", s->regs.sr1);
} }
static void pl041_fifo1_transmit(pl041_state *s) static void pl041_fifo1_transmit(PL041State *s)
{ {
pl041_channel *channel = &s->fifo1; pl041_channel *channel = &s->fifo1;
pl041_fifo *fifo = &s->fifo1.tx_fifo; pl041_fifo *fifo = &s->fifo1.tx_fifo;
@ -291,7 +291,7 @@ static void pl041_fifo1_transmit(pl041_state *s)
} }
} }
static void pl041_isr1_update(pl041_state *s) static void pl041_isr1_update(PL041State *s)
{ {
/* Update ISR1 */ /* Update ISR1 */
if (s->regs.sr1 & TXUNDERRUN) { if (s->regs.sr1 & TXUNDERRUN) {
@ -320,7 +320,7 @@ static void pl041_isr1_update(pl041_state *s)
static void pl041_request_data(void *opaque) static void pl041_request_data(void *opaque)
{ {
pl041_state *s = (pl041_state *)opaque; PL041State *s = (PL041State *)opaque;
/* Trigger pending transfers */ /* Trigger pending transfers */
pl041_fifo1_transmit(s); pl041_fifo1_transmit(s);
@ -330,7 +330,7 @@ static void pl041_request_data(void *opaque)
static uint64_t pl041_read(void *opaque, hwaddr offset, static uint64_t pl041_read(void *opaque, hwaddr offset,
unsigned size) unsigned size)
{ {
pl041_state *s = (pl041_state *)opaque; PL041State *s = (PL041State *)opaque;
int value; int value;
if ((offset >= PL041_periphid0) && (offset <= PL041_pcellid3)) { if ((offset >= PL041_periphid0) && (offset <= PL041_pcellid3)) {
@ -364,7 +364,7 @@ static uint64_t pl041_read(void *opaque, hwaddr offset,
static void pl041_write(void *opaque, hwaddr offset, static void pl041_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size) uint64_t value, unsigned size)
{ {
pl041_state *s = (pl041_state *)opaque; PL041State *s = (PL041State *)opaque;
uint16_t control, data; uint16_t control, data;
uint32_t result; uint32_t result;
@ -504,7 +504,7 @@ static void pl041_write(void *opaque, hwaddr offset,
static void pl041_device_reset(DeviceState *d) static void pl041_device_reset(DeviceState *d)
{ {
pl041_state *s = DO_UPCAST(pl041_state, busdev.qdev, d); PL041State *s = DO_UPCAST(PL041State, busdev.qdev, d);
pl041_reset(s); pl041_reset(s);
} }
@ -517,7 +517,7 @@ static const MemoryRegionOps pl041_ops = {
static int pl041_init(SysBusDevice *dev) static int pl041_init(SysBusDevice *dev)
{ {
pl041_state *s = FROM_SYSBUS(pl041_state, dev); PL041State *s = FROM_SYSBUS(PL041State, dev);
DBG_L1("pl041_init 0x%08x\n", (uint32_t)s); DBG_L1("pl041_init 0x%08x\n", (uint32_t)s);
@ -603,12 +603,12 @@ static const VMStateDescription vmstate_pl041 = {
.version_id = 1, .version_id = 1,
.minimum_version_id = 1, .minimum_version_id = 1,
.fields = (VMStateField[]) { .fields = (VMStateField[]) {
VMSTATE_UINT32(fifo_depth, pl041_state), VMSTATE_UINT32(fifo_depth, PL041State),
VMSTATE_STRUCT(regs, pl041_state, 0, VMSTATE_STRUCT(regs, PL041State, 0,
vmstate_pl041_regfile, pl041_regfile), vmstate_pl041_regfile, pl041_regfile),
VMSTATE_STRUCT(fifo1, pl041_state, 0, VMSTATE_STRUCT(fifo1, PL041State, 0,
vmstate_pl041_channel, pl041_channel), vmstate_pl041_channel, pl041_channel),
VMSTATE_STRUCT(codec, pl041_state, 0, VMSTATE_STRUCT(codec, PL041State, 0,
vmstate_lm4549_state, lm4549_state), vmstate_lm4549_state, lm4549_state),
VMSTATE_END_OF_LIST() VMSTATE_END_OF_LIST()
} }
@ -616,7 +616,8 @@ static const VMStateDescription vmstate_pl041 = {
static Property pl041_device_properties[] = { static Property pl041_device_properties[] = {
/* Non-compact FIFO depth property */ /* Non-compact FIFO depth property */
DEFINE_PROP_UINT32("nc_fifo_depth", pl041_state, fifo_depth, DEFAULT_FIFO_DEPTH), DEFINE_PROP_UINT32("nc_fifo_depth", PL041State, fifo_depth,
DEFAULT_FIFO_DEPTH),
DEFINE_PROP_END_OF_LIST(), DEFINE_PROP_END_OF_LIST(),
}; };
@ -636,7 +637,7 @@ static void pl041_device_class_init(ObjectClass *klass, void *data)
static const TypeInfo pl041_device_info = { static const TypeInfo pl041_device_info = {
.name = "pl041", .name = "pl041",
.parent = TYPE_SYS_BUS_DEVICE, .parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(pl041_state), .instance_size = sizeof(PL041State),
.class_init = pl041_device_class_init, .class_init = pl041_device_class_init,
}; };