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ETRAX-PIC: Untabify.

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Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
This commit is contained in:
Edgar E. Iglesias 2009-05-16 12:28:33 +02:00
parent 3b1fd90ed1
commit 979d98ca90
1 changed files with 84 additions and 84 deletions
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168
hw/etraxfs_pic.c
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@ -29,85 +29,85 @@
#define D(x) #define D(x)
#define R_RW_MASK 0 #define R_RW_MASK 0
#define R_R_VECT 1 #define R_R_VECT 1
#define R_R_MASKED_VECT 2 #define R_R_MASKED_VECT 2
#define R_R_NMI 3 #define R_R_NMI 3
#define R_R_GURU 4 #define R_R_GURU 4
#define R_MAX 5 #define R_MAX 5
struct fs_pic_state struct fs_pic_state
{ {
CPUState *env; CPUState *env;
uint32_t regs[R_MAX]; uint32_t regs[R_MAX];
}; };
static void pic_update(struct fs_pic_state *fs) static void pic_update(struct fs_pic_state *fs)
{ {
CPUState *env = fs->env; CPUState *env = fs->env;
uint32_t vector = 0; uint32_t vector = 0;
int i; int i;
fs->regs[R_R_MASKED_VECT] = fs->regs[R_R_VECT] & fs->regs[R_RW_MASK]; fs->regs[R_R_MASKED_VECT] = fs->regs[R_R_VECT] & fs->regs[R_RW_MASK];
/* The ETRAX interrupt controller signals interrupts to teh core /* The ETRAX interrupt controller signals interrupts to teh core
through an interrupt request wire and an irq vector bus. If through an interrupt request wire and an irq vector bus. If
multiple interrupts are simultaneously active it chooses vector multiple interrupts are simultaneously active it chooses vector
0x30 and lets the sw choose the priorities. */ 0x30 and lets the sw choose the priorities. */
if (fs->regs[R_R_MASKED_VECT]) { if (fs->regs[R_R_MASKED_VECT]) {
uint32_t mv = fs->regs[R_R_MASKED_VECT]; uint32_t mv = fs->regs[R_R_MASKED_VECT];
for (i = 0; i < 31; i++) { for (i = 0; i < 31; i++) {
if (mv & 1) { if (mv & 1) {
vector = 0x31 + i; vector = 0x31 + i;
/* Check for multiple interrupts. */ /* Check for multiple interrupts. */
if (mv > 1) if (mv > 1)
vector = 0x30; vector = 0x30;
break; break;
} }
mv >>= 1; mv >>= 1;
} }
if (vector) { if (vector) {
env->interrupt_vector = vector; env->interrupt_vector = vector;
D(printf("%s vector=%x\n", __func__, vector)); D(printf("%s vector=%x\n", __func__, vector));
cpu_interrupt(env, CPU_INTERRUPT_HARD); cpu_interrupt(env, CPU_INTERRUPT_HARD);
} }
} else { } else {
env->interrupt_vector = 0; env->interrupt_vector = 0;
cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
D(printf("%s reset irqs\n", __func__)); D(printf("%s reset irqs\n", __func__));
} }
} }
static uint32_t pic_readl (void *opaque, target_phys_addr_t addr) static uint32_t pic_readl (void *opaque, target_phys_addr_t addr)
{ {
struct fs_pic_state *fs = opaque; struct fs_pic_state *fs = opaque;
uint32_t rval; uint32_t rval;
rval = fs->regs[addr >> 2]; rval = fs->regs[addr >> 2];
D(printf("%s %x=%x\n", __func__, addr, rval)); D(printf("%s %x=%x\n", __func__, addr, rval));
return rval; return rval;
} }
static void static void
pic_writel (void *opaque, target_phys_addr_t addr, uint32_t value) pic_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{ {
struct fs_pic_state *fs = opaque; struct fs_pic_state *fs = opaque;
D(printf("%s addr=%x val=%x\n", __func__, addr, value)); D(printf("%s addr=%x val=%x\n", __func__, addr, value));
if (addr == R_RW_MASK) { if (addr == R_RW_MASK) {
fs->regs[R_RW_MASK] = value; fs->regs[R_RW_MASK] = value;
pic_update(fs); pic_update(fs);
} }
} }
static CPUReadMemoryFunc *pic_read[] = { static CPUReadMemoryFunc *pic_read[] = {
NULL, NULL, NULL, NULL,
&pic_readl, &pic_readl,
}; };
static CPUWriteMemoryFunc *pic_write[] = { static CPUWriteMemoryFunc *pic_write[] = {
NULL, NULL, NULL, NULL,
&pic_writel, &pic_writel,
}; };
void pic_info(Monitor *mon) void pic_info(Monitor *mon)
@ -119,47 +119,47 @@ void irq_info(Monitor *mon)
} }
static void nmi_handler(void *opaque, int irq, int level) static void nmi_handler(void *opaque, int irq, int level)
{ {
struct fs_pic_state *fs = (void *)opaque; struct fs_pic_state *fs = (void *)opaque;
CPUState *env = fs->env; CPUState *env = fs->env;
uint32_t mask; uint32_t mask;
mask = 1 << irq; mask = 1 << irq;
if (level) if (level)
fs->regs[R_R_NMI] |= mask; fs->regs[R_R_NMI] |= mask;
else else
fs->regs[R_R_NMI] &= ~mask; fs->regs[R_R_NMI] &= ~mask;
if (fs->regs[R_R_NMI]) if (fs->regs[R_R_NMI])
cpu_interrupt(env, CPU_INTERRUPT_NMI); cpu_interrupt(env, CPU_INTERRUPT_NMI);
else else
cpu_reset_interrupt(env, CPU_INTERRUPT_NMI); cpu_reset_interrupt(env, CPU_INTERRUPT_NMI);
} }
static void irq_handler(void *opaque, int irq, int level) static void irq_handler(void *opaque, int irq, int level)
{ {
struct fs_pic_state *fs = (void *)opaque; struct fs_pic_state *fs = (void *)opaque;
if (irq >= 30) if (irq >= 30)
return nmi_handler(opaque, irq, level); return nmi_handler(opaque, irq, level);
irq -= 1; irq -= 1;
fs->regs[R_R_VECT] &= ~(1 << irq); fs->regs[R_R_VECT] &= ~(1 << irq);
fs->regs[R_R_VECT] |= (!!level << irq); fs->regs[R_R_VECT] |= (!!level << irq);
pic_update(fs); pic_update(fs);
} }
qemu_irq *etraxfs_pic_init(CPUState *env, target_phys_addr_t base) qemu_irq *etraxfs_pic_init(CPUState *env, target_phys_addr_t base)
{ {
struct fs_pic_state *fs = NULL; struct fs_pic_state *fs = NULL;
qemu_irq *irq; qemu_irq *irq;
int intr_vect_regs; int intr_vect_regs;
fs = qemu_mallocz(sizeof *fs); fs = qemu_mallocz(sizeof *fs);
fs->env = env; fs->env = env;
irq = qemu_allocate_irqs(irq_handler, fs, 32); irq = qemu_allocate_irqs(irq_handler, fs, 32);
intr_vect_regs = cpu_register_io_memory(0, pic_read, pic_write, fs); intr_vect_regs = cpu_register_io_memory(0, pic_read, pic_write, fs);
cpu_register_physical_memory(base, R_MAX * 4, intr_vect_regs); cpu_register_physical_memory(base, R_MAX * 4, intr_vect_regs);
return irq; return irq;
} }