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sh_timer: convert to memory API

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Signed-off-by: Benoit Canet <benoit.canet@gmail.com>
Signed-off-by: Avi Kivity <avi@redhat.com>
This commit is contained in:
Benoît Canet 2011-11-17 14:23:00 +01:00 committed by Avi Kivity
parent 1a4004c772
commit 89e2945140
3 changed files with 28 additions and 22 deletions
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3
hw/sh.h
View File

@ -31,7 +31,8 @@ int sh7750_register_io_device(struct SH7750State *s,
#define TMU012_FEAT_TOCR (1 << 0) #define TMU012_FEAT_TOCR (1 << 0)
#define TMU012_FEAT_3CHAN (1 << 1) #define TMU012_FEAT_3CHAN (1 << 1)
#define TMU012_FEAT_EXTCLK (1 << 2) #define TMU012_FEAT_EXTCLK (1 << 2)
void tmu012_init(target_phys_addr_t base, int feat, uint32_t freq, void tmu012_init(struct MemoryRegion *sysmem, target_phys_addr_t base,
int feat, uint32_t freq,
qemu_irq ch0_irq, qemu_irq ch1_irq, qemu_irq ch0_irq, qemu_irq ch1_irq,
qemu_irq ch2_irq0, qemu_irq ch2_irq1); qemu_irq ch2_irq0, qemu_irq ch2_irq1);

4
hw/sh7750.c
View File

@ -780,7 +780,7 @@ SH7750State *sh7750_init(CPUSH4State * cpu, MemoryRegion *sysmem)
NULL, NULL,
s->intc.irqs[SCIF_BRI]); s->intc.irqs[SCIF_BRI]);
tmu012_init(0x1fd80000, tmu012_init(sysmem, 0x1fd80000,
TMU012_FEAT_TOCR | TMU012_FEAT_3CHAN | TMU012_FEAT_EXTCLK, TMU012_FEAT_TOCR | TMU012_FEAT_3CHAN | TMU012_FEAT_EXTCLK,
s->periph_freq, s->periph_freq,
s->intc.irqs[TMU0], s->intc.irqs[TMU0],
@ -804,7 +804,7 @@ SH7750State *sh7750_init(CPUSH4State * cpu, MemoryRegion *sysmem)
sh_intc_register_sources(&s->intc, sh_intc_register_sources(&s->intc,
_INTC_ARRAY(vectors_tmu34), _INTC_ARRAY(vectors_tmu34),
NULL, 0); NULL, 0);
tmu012_init(0x1e100000, 0, s->periph_freq, tmu012_init(sysmem, 0x1e100000, 0, s->periph_freq,
s->intc.irqs[TMU3], s->intc.irqs[TMU3],
s->intc.irqs[TMU4], s->intc.irqs[TMU4],
NULL, NULL); NULL, NULL);

43
hw/sh_timer.c
View File

@ -11,6 +11,7 @@
#include "hw.h" #include "hw.h"
#include "sh.h" #include "sh.h"
#include "qemu-timer.h" #include "qemu-timer.h"
#include "exec-memory.h"
//#define DEBUG_TIMER //#define DEBUG_TIMER
@ -210,6 +211,9 @@ static void *sh_timer_init(uint32_t freq, int feat, qemu_irq irq)
} }
typedef struct { typedef struct {
MemoryRegion iomem;
MemoryRegion iomem_p4;
MemoryRegion iomem_a7;
void *timer[3]; void *timer[3];
int level[3]; int level[3];
uint32_t tocr; uint32_t tocr;
@ -217,7 +221,8 @@ typedef struct {
int feat; int feat;
} tmu012_state; } tmu012_state;
static uint32_t tmu012_read(void *opaque, target_phys_addr_t offset) static uint64_t tmu012_read(void *opaque, target_phys_addr_t offset,
unsigned size)
{ {
tmu012_state *s = (tmu012_state *)opaque; tmu012_state *s = (tmu012_state *)opaque;
@ -248,7 +253,7 @@ static uint32_t tmu012_read(void *opaque, target_phys_addr_t offset)
} }
static void tmu012_write(void *opaque, target_phys_addr_t offset, static void tmu012_write(void *opaque, target_phys_addr_t offset,
uint32_t value) uint64_t value, unsigned size)
{ {
tmu012_state *s = (tmu012_state *)opaque; tmu012_state *s = (tmu012_state *)opaque;
@ -291,23 +296,17 @@ static void tmu012_write(void *opaque, target_phys_addr_t offset,
} }
} }
static CPUReadMemoryFunc * const tmu012_readfn[] = { static const MemoryRegionOps tmu012_ops = {
tmu012_read, .read = tmu012_read,
tmu012_read, .write = tmu012_write,
tmu012_read .endianness = DEVICE_NATIVE_ENDIAN,
}; };
static CPUWriteMemoryFunc * const tmu012_writefn[] = { void tmu012_init(MemoryRegion *sysmem, target_phys_addr_t base,
tmu012_write, int feat, uint32_t freq,
tmu012_write,
tmu012_write
};
void tmu012_init(target_phys_addr_t base, int feat, uint32_t freq,
qemu_irq ch0_irq, qemu_irq ch1_irq, qemu_irq ch0_irq, qemu_irq ch1_irq,
qemu_irq ch2_irq0, qemu_irq ch2_irq1) qemu_irq ch2_irq0, qemu_irq ch2_irq1)
{ {
int iomemtype;
tmu012_state *s; tmu012_state *s;
int timer_feat = (feat & TMU012_FEAT_EXTCLK) ? TIMER_FEAT_EXTCLK : 0; int timer_feat = (feat & TMU012_FEAT_EXTCLK) ? TIMER_FEAT_EXTCLK : 0;
@ -318,10 +317,16 @@ void tmu012_init(target_phys_addr_t base, int feat, uint32_t freq,
if (feat & TMU012_FEAT_3CHAN) if (feat & TMU012_FEAT_3CHAN)
s->timer[2] = sh_timer_init(freq, timer_feat | TIMER_FEAT_CAPT, s->timer[2] = sh_timer_init(freq, timer_feat | TIMER_FEAT_CAPT,
ch2_irq0); /* ch2_irq1 not supported */ ch2_irq0); /* ch2_irq1 not supported */
iomemtype = cpu_register_io_memory(tmu012_readfn,
tmu012_writefn, s, memory_region_init_io(&s->iomem, &tmu012_ops, s,
DEVICE_NATIVE_ENDIAN); "timer", 0x100000000ULL);
cpu_register_physical_memory(P4ADDR(base), 0x00001000, iomemtype);
cpu_register_physical_memory(A7ADDR(base), 0x00001000, iomemtype); memory_region_init_alias(&s->iomem_p4, "timer-p4",
&s->iomem, 0, 0x1000);
memory_region_add_subregion(sysmem, P4ADDR(base), &s->iomem_p4);
memory_region_init_alias(&s->iomem_a7, "timer-a7",
&s->iomem, 0, 0x1000);
memory_region_add_subregion(sysmem, A7ADDR(base), &s->iomem_a7);
/* ??? Save/restore. */ /* ??? Save/restore. */
} }