target/sparc: convert to TranslatorOps
Notes: - Moved the cross-page check from the end of translate_insn to init_disas_context. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Cc: Artyom Tarasenko <atar4qemu@gmail.com> Signed-off-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Emilio G. Cota
Richard Henderson
parent
af00be490b
commit
6e61bc9410
@ -5737,99 +5737,91 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn)
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}
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}
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}
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}
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void gen_intermediate_code(CPUState *cs, TranslationBlock * tb)
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static void sparc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
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{
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{
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DisasContext *dc = container_of(dcbase, DisasContext, base);
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CPUSPARCState *env = cs->env_ptr;
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CPUSPARCState *env = cs->env_ptr;
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DisasContext dc1, *dc = &dc1;
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int bound;
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int max_insns;
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unsigned int insn;
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memset(dc, 0, sizeof(DisasContext));
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dc->base.tb = tb;
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dc->base.pc_first = tb->pc;
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dc->base.pc_next = tb->pc;
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dc->base.is_jmp = DISAS_NEXT;
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dc->base.num_insns = 0;
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dc->base.singlestep_enabled = cs->singlestep_enabled;
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dc->pc = dc->base.pc_first;
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dc->pc = dc->base.pc_first;
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dc->npc = (target_ulong) tb->cs_base;
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dc->npc = (target_ulong)dc->base.tb->cs_base;
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dc->cc_op = CC_OP_DYNAMIC;
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dc->cc_op = CC_OP_DYNAMIC;
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dc->mem_idx = tb->flags & TB_FLAG_MMU_MASK;
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dc->mem_idx = dc->base.tb->flags & TB_FLAG_MMU_MASK;
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dc->def = &env->def;
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dc->def = &env->def;
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dc->fpu_enabled = tb_fpu_enabled(tb->flags);
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dc->fpu_enabled = tb_fpu_enabled(dc->base.tb->flags);
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dc->address_mask_32bit = tb_am_enabled(tb->flags);
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dc->address_mask_32bit = tb_am_enabled(dc->base.tb->flags);
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#ifndef CONFIG_USER_ONLY
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#ifndef CONFIG_USER_ONLY
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dc->supervisor = (tb->flags & TB_FLAG_SUPER) != 0;
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dc->supervisor = (dc->base.tb->flags & TB_FLAG_SUPER) != 0;
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#endif
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#endif
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#ifdef TARGET_SPARC64
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#ifdef TARGET_SPARC64
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dc->fprs_dirty = 0;
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dc->fprs_dirty = 0;
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dc->asi = (tb->flags >> TB_FLAG_ASI_SHIFT) & 0xff;
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dc->asi = (dc->base.tb->flags >> TB_FLAG_ASI_SHIFT) & 0xff;
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#ifndef CONFIG_USER_ONLY
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#ifndef CONFIG_USER_ONLY
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dc->hypervisor = (tb->flags & TB_FLAG_HYPER) != 0;
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dc->hypervisor = (dc->base.tb->flags & TB_FLAG_HYPER) != 0;
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#endif
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#endif
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#endif
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#endif
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/*
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* if we reach a page boundary, we stop generation so that the
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* PC of a TT_TFAULT exception is always in the right page
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*/
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bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4;
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dc->base.max_insns = MIN(dc->base.max_insns, bound);
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}
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max_insns = tb_cflags(tb) & CF_COUNT_MASK;
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static void sparc_tr_tb_start(DisasContextBase *db, CPUState *cs)
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if (max_insns == 0) {
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{
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max_insns = CF_COUNT_MASK;
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}
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static void sparc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
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{
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DisasContext *dc = container_of(dcbase, DisasContext, base);
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if (dc->npc & JUMP_PC) {
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assert(dc->jump_pc[1] == dc->pc + 4);
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tcg_gen_insn_start(dc->pc, dc->jump_pc[0] | JUMP_PC);
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} else {
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tcg_gen_insn_start(dc->pc, dc->npc);
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}
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}
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if (max_insns > TCG_MAX_INSNS) {
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}
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max_insns = TCG_MAX_INSNS;
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static bool sparc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs,
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const CPUBreakpoint *bp)
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{
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DisasContext *dc = container_of(dcbase, DisasContext, base);
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if (dc->pc != dc->base.pc_first) {
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save_state(dc);
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}
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}
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if (dc->base.singlestep_enabled || singlestep) {
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gen_helper_debug(cpu_env);
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max_insns = 1;
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tcg_gen_exit_tb(0);
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dc->base.is_jmp = DISAS_NORETURN;
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/* update pc_next so that the current instruction is included in tb->size */
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dc->base.pc_next += 4;
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return true;
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}
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static void sparc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
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{
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DisasContext *dc = container_of(dcbase, DisasContext, base);
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CPUSPARCState *env = cs->env_ptr;
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unsigned int insn;
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insn = cpu_ldl_code(env, dc->pc);
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dc->base.pc_next += 4;
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disas_sparc_insn(dc, insn);
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if (dc->base.is_jmp == DISAS_NORETURN) {
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return;
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}
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}
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if (dc->pc != dc->base.pc_next) {
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gen_tb_start(tb);
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dc->base.is_jmp = DISAS_TOO_MANY;
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do {
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if (dc->npc & JUMP_PC) {
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assert(dc->jump_pc[1] == dc->pc + 4);
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tcg_gen_insn_start(dc->pc, dc->jump_pc[0] | JUMP_PC);
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} else {
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tcg_gen_insn_start(dc->pc, dc->npc);
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}
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dc->base.num_insns++;
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if (unlikely(cpu_breakpoint_test(cs, dc->base.pc_next, BP_ANY))) {
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if (dc->pc != dc->base.pc_first) {
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save_state(dc);
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}
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gen_helper_debug(cpu_env);
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tcg_gen_exit_tb(0);
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dc->base.is_jmp = DISAS_NORETURN;
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dc->base.pc_next += 4;
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goto exit_gen_loop;
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}
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if (dc->base.num_insns == max_insns && (tb_cflags(tb) & CF_LAST_IO)) {
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gen_io_start();
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}
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insn = cpu_ldl_code(env, dc->pc);
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dc->base.pc_next += 4;
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disas_sparc_insn(dc, insn);
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if (dc->base.is_jmp == DISAS_NORETURN) {
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break;
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}
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/* if the next PC is different, we abort now */
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if (dc->pc != dc->base.pc_next) {
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break;
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}
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/* if we reach a page boundary, we stop generation so that the
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PC of a TT_TFAULT exception is always in the right page */
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if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
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break;
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} while (!tcg_op_buf_full() &&
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(dc->pc - dc->base.pc_first) < (TARGET_PAGE_SIZE - 32) &&
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dc->base.num_insns < max_insns);
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exit_gen_loop:
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if (tb_cflags(tb) & CF_LAST_IO) {
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gen_io_end();
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}
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}
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}
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static void sparc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
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{
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DisasContext *dc = container_of(dcbase, DisasContext, base);
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if (dc->base.is_jmp != DISAS_NORETURN) {
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if (dc->base.is_jmp != DISAS_NORETURN) {
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if (dc->pc != DYNAMIC_PC &&
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if (dc->pc != DYNAMIC_PC &&
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(dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
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(dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
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@ -5843,23 +5835,29 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock * tb)
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tcg_gen_exit_tb(0);
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tcg_gen_exit_tb(0);
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}
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}
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}
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}
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gen_tb_end(tb, dc->base.num_insns);
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}
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tb->size = dc->base.pc_next - dc->base.pc_first;
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static void sparc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu)
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tb->icount = dc->base.num_insns;
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{
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qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first));
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log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size);
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}
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#ifdef DEBUG_DISAS
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static const TranslatorOps sparc_tr_ops = {
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if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)
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.init_disas_context = sparc_tr_init_disas_context,
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&& qemu_log_in_addr_range(dc->base.pc_first)) {
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.tb_start = sparc_tr_tb_start,
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qemu_log_lock();
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.insn_start = sparc_tr_insn_start,
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qemu_log("--------------\n");
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.breakpoint_check = sparc_tr_breakpoint_check,
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qemu_log("IN: %s\n", lookup_symbol(dc->base.pc_first));
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.translate_insn = sparc_tr_translate_insn,
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log_target_disas(cs, dc->base.pc_first,
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.tb_stop = sparc_tr_tb_stop,
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dc->base.pc_next - dc->base.pc_first);
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.disas_log = sparc_tr_disas_log,
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qemu_log("\n");
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};
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qemu_log_unlock();
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}
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void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
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#endif
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{
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DisasContext dc = {};
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translator_loop(&sparc_tr_ops, &dc.base, cs, tb);
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}
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}
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void sparc_tcg_init(void)
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void sparc_tcg_init(void)
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