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target/arm: [tcg,a64] Port to init_disas_context

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Incrementally paves the way towards using the generic instruction translation
loop.

Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Alex Benneé <alex.benee@linaro.org>
Message-Id: <150002340430.22386.10889954302345646107.stgit@frigg.lan>
[rth: Adjust for max_insns interface change.]
Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Lluís Vilanova 2017-07-14 12:10:04 +03:00 committed by Richard Henderson
parent 1d8a553523
commit 5c03990665
1 changed files with 24 additions and 14 deletions
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38
target/arm/translate-a64.c
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@ -11200,21 +11200,12 @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s)
free_tmp_a64(s); free_tmp_a64(s);
} }
void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs, static int aarch64_tr_init_disas_context(DisasContextBase *dcbase,
TranslationBlock *tb) CPUState *cpu, int max_insns)
{ {
CPUARMState *env = cs->env_ptr;
ARMCPU *cpu = arm_env_get_cpu(env);
DisasContext *dc = container_of(dcbase, DisasContext, base); DisasContext *dc = container_of(dcbase, DisasContext, base);
target_ulong next_page_start; CPUARMState *env = cpu->env_ptr;
int max_insns; ARMCPU *arm_cpu = arm_env_get_cpu(env);
dc->base.tb = tb;
dc->base.pc_first = dc->base.tb->pc;
dc->base.pc_next = dc->base.pc_first;
dc->base.is_jmp = DISAS_NEXT;
dc->base.num_insns = 0;
dc->base.singlestep_enabled = cs->singlestep_enabled;
dc->pc = dc->base.pc_first; dc->pc = dc->base.pc_first;
dc->condjmp = 0; dc->condjmp = 0;
@ -11240,7 +11231,7 @@ void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs,
dc->fp_excp_el = ARM_TBFLAG_FPEXC_EL(dc->base.tb->flags); dc->fp_excp_el = ARM_TBFLAG_FPEXC_EL(dc->base.tb->flags);
dc->vec_len = 0; dc->vec_len = 0;
dc->vec_stride = 0; dc->vec_stride = 0;
dc->cp_regs = cpu->cp_regs; dc->cp_regs = arm_cpu->cp_regs;
dc->features = env->features; dc->features = env->features;
/* Single step state. The code-generation logic here is: /* Single step state. The code-generation logic here is:
@ -11265,6 +11256,24 @@ void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs,
init_tmp_a64_array(dc); init_tmp_a64_array(dc);
return max_insns;
}
void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs,
TranslationBlock *tb)
{
CPUARMState *env = cs->env_ptr;
DisasContext *dc = container_of(dcbase, DisasContext, base);
target_ulong next_page_start;
int max_insns;
dc->base.tb = tb;
dc->base.pc_first = dc->base.tb->pc;
dc->base.pc_next = dc->base.pc_first;
dc->base.is_jmp = DISAS_NEXT;
dc->base.num_insns = 0;
dc->base.singlestep_enabled = cs->singlestep_enabled;
next_page_start = (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; next_page_start = (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
max_insns = dc->base.tb->cflags & CF_COUNT_MASK; max_insns = dc->base.tb->cflags & CF_COUNT_MASK;
if (max_insns == 0) { if (max_insns == 0) {
@ -11273,6 +11282,7 @@ void gen_intermediate_code_a64(DisasContextBase *dcbase, CPUState *cs,
if (max_insns > TCG_MAX_INSNS) { if (max_insns > TCG_MAX_INSNS) {
max_insns = TCG_MAX_INSNS; max_insns = TCG_MAX_INSNS;
} }
max_insns = aarch64_tr_init_disas_context(&dc->base, cs, max_insns);
gen_tb_start(tb); gen_tb_start(tb);