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Fix MIPS MT GPR accesses, thanks Stefan Weil.

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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4307 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
ths 2008-05-03 11:06:59 +00:00
parent 50cfa95cbd
commit 5b2808bfc0
2 changed files with 10 additions and 10 deletions
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16
target-mips/op.c
View File

@ -2300,7 +2300,7 @@ void op_mftgpr(void)
{ {
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
T0 = env->gpr[PARAM1][other_tc]; T0 = env->gpr[other_tc][PARAM1];
FORCE_RET(); FORCE_RET();
} }
@ -2308,7 +2308,7 @@ void op_mftlo(void)
{ {
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
T0 = env->LO[PARAM1][other_tc]; T0 = env->LO[other_tc][PARAM1];
FORCE_RET(); FORCE_RET();
} }
@ -2316,7 +2316,7 @@ void op_mfthi(void)
{ {
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
T0 = env->HI[PARAM1][other_tc]; T0 = env->HI[other_tc][PARAM1];
FORCE_RET(); FORCE_RET();
} }
@ -2324,7 +2324,7 @@ void op_mftacx(void)
{ {
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
T0 = env->ACX[PARAM1][other_tc]; T0 = env->ACX[other_tc][PARAM1];
FORCE_RET(); FORCE_RET();
} }
@ -2340,7 +2340,7 @@ void op_mttgpr(void)
{ {
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
T0 = env->gpr[PARAM1][other_tc]; T0 = env->gpr[other_tc][PARAM1];
FORCE_RET(); FORCE_RET();
} }
@ -2348,7 +2348,7 @@ void op_mttlo(void)
{ {
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
T0 = env->LO[PARAM1][other_tc]; T0 = env->LO[other_tc][PARAM1];
FORCE_RET(); FORCE_RET();
} }
@ -2356,7 +2356,7 @@ void op_mtthi(void)
{ {
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
T0 = env->HI[PARAM1][other_tc]; T0 = env->HI[other_tc][PARAM1];
FORCE_RET(); FORCE_RET();
} }
@ -2364,7 +2364,7 @@ void op_mttacx(void)
{ {
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
T0 = env->ACX[PARAM1][other_tc]; T0 = env->ACX[other_tc][PARAM1];
FORCE_RET(); FORCE_RET();
} }

4
target-mips/op_template.c
View File

@ -52,13 +52,13 @@ void glue(op_load_gpr_T2_gpr, REG) (void)
void glue(op_load_srsgpr_T0_gpr, REG) (void) void glue(op_load_srsgpr_T0_gpr, REG) (void)
{ {
T0 = env->gpr[REG][(env->CP0_SRSCtl >> CP0SRSCtl_PSS) & 0xf]; T0 = env->gpr[(env->CP0_SRSCtl >> CP0SRSCtl_PSS) & 0xf][REG];
FORCE_RET(); FORCE_RET();
} }
void glue(op_store_T0_srsgpr_gpr, REG) (void) void glue(op_store_T0_srsgpr_gpr, REG) (void)
{ {
env->gpr[REG][(env->CP0_SRSCtl >> CP0SRSCtl_PSS) & 0xf] = T0; env->gpr[(env->CP0_SRSCtl >> CP0SRSCtl_PSS) & 0xf][REG] = T0;
FORCE_RET(); FORCE_RET();
} }
#endif #endif