Merge commit 'ff71f2e8cacefae99179993204172bc65e4303df' into staging
* commit 'ff71f2e8cacefae99179993204172bc65e4303df': (21 commits) rtl8139: do the network/host communication only in normal operating mode rtl8139: correctly check the opmode net: move compute_mcast_idx() to net.h rtl8139: support byte read to TxStatus registers rtl8139: remove unused marco rtl8139: limit transmission buffer size in c+ mode pci_regs: Add PCI_EXP_TYPE_PCIE_BRIDGE virtio-net: add DATA_VALID flag pci_bridge: upper 32 bit are long registers pci: fix bridge IO/BASE pcie: drop functionality moved to core pci: set memory type for memory behind the bridge pci: add standard bridge device slotid: add slot id capability shpc: standard hot plug controller pci_bridge: user-friendly default bus name pci: make another unused extern function static pci: don't export an internal function pci_regs: Fix value of PCI_EXP_TYPE_RC_EC. pci: Do not check if a bus exist in pci_parse_devaddr. ...
This commit is contained in:
Anthony Liguori
commit
4e1957acc8
@ -213,8 +213,10 @@ hw-obj-$(CONFIG_VIRTIO) += virtio-console.o
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hw-obj-y += usb/libhw.o
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hw-obj-y += usb/libhw.o
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hw-obj-$(CONFIG_VIRTIO_PCI) += virtio-pci.o
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hw-obj-$(CONFIG_VIRTIO_PCI) += virtio-pci.o
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hw-obj-y += fw_cfg.o
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hw-obj-y += fw_cfg.o
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hw-obj-$(CONFIG_PCI) += pci.o pci_bridge.o
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hw-obj-$(CONFIG_PCI) += pci.o pci_bridge.o pci_bridge_dev.o
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hw-obj-$(CONFIG_PCI) += msix.o msi.o
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hw-obj-$(CONFIG_PCI) += msix.o msi.o
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hw-obj-$(CONFIG_PCI) += shpc.o
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hw-obj-$(CONFIG_PCI) += slotid_cap.o
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hw-obj-$(CONFIG_PCI) += pci_host.o pcie_host.o
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hw-obj-$(CONFIG_PCI) += pci_host.o pcie_host.o
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hw-obj-$(CONFIG_PCI) += ioh3420.o xio3130_upstream.o xio3130_downstream.o
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hw-obj-$(CONFIG_PCI) += ioh3420.o xio3130_upstream.o xio3130_downstream.o
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hw-obj-y += watchdog.o
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hw-obj-y += watchdog.o
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@ -322,33 +322,8 @@ static const uint16_t eepro100_mdi_mask[] = {
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0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
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0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
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};
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};
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#define POLYNOMIAL 0x04c11db6
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static E100PCIDeviceInfo *eepro100_get_class(EEPRO100State *s);
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static E100PCIDeviceInfo *eepro100_get_class(EEPRO100State *s);
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/* From FreeBSD */
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/* XXX: optimize */
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static unsigned compute_mcast_idx(const uint8_t * ep)
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{
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uint32_t crc;
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int carry, i, j;
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uint8_t b;
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crc = 0xffffffff;
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for (i = 0; i < 6; i++) {
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b = *ep++;
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for (j = 0; j < 8; j++) {
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carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
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crc <<= 1;
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b >>= 1;
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if (carry) {
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crc = ((crc ^ POLYNOMIAL) | carry);
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}
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}
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}
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return (crc & BITS(7, 2)) >> 2;
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}
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/* Read a 16 bit control/status (CSR) register. */
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/* Read a 16 bit control/status (CSR) register. */
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static uint16_t e100_read_reg2(EEPRO100State *s, E100RegisterOffset addr)
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static uint16_t e100_read_reg2(EEPRO100State *s, E100RegisterOffset addr)
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{
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{
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24
hw/ne2000.c
24
hw/ne2000.c
@ -150,30 +150,6 @@ static void ne2000_update_irq(NE2000State *s)
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qemu_set_irq(s->irq, (isr != 0));
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qemu_set_irq(s->irq, (isr != 0));
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}
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}
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#define POLYNOMIAL 0x04c11db6
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/* From FreeBSD */
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/* XXX: optimize */
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static int compute_mcast_idx(const uint8_t *ep)
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{
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uint32_t crc;
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int carry, i, j;
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uint8_t b;
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crc = 0xffffffff;
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for (i = 0; i < 6; i++) {
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b = *ep++;
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for (j = 0; j < 8; j++) {
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carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
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crc <<= 1;
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b >>= 1;
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if (carry)
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crc = ((crc ^ POLYNOMIAL) | carry);
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}
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}
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return (crc >> 26);
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}
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static int ne2000_buffer_full(NE2000State *s)
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static int ne2000_buffer_full(NE2000State *s)
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{
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{
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int avail, index, boundary;
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int avail, index, boundary;
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@ -351,31 +351,6 @@ static int open_eth_can_receive(VLANClientState *nc)
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(rx_desc(s)->len_flags & RXD_E);
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(rx_desc(s)->len_flags & RXD_E);
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}
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}
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#define POLYNOMIAL 0x04c11db6
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/* From FreeBSD */
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/* XXX: optimize */
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static unsigned compute_mcast_idx(const uint8_t *ep)
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{
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uint32_t crc;
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int carry, i, j;
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uint8_t b;
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crc = 0xffffffff;
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for (i = 0; i < 6; i++) {
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b = *ep++;
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for (j = 0; j < 8; j++) {
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carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
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crc <<= 1;
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b >>= 1;
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if (carry) {
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crc = ((crc ^ POLYNOMIAL) | carry);
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}
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}
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}
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return crc >> 26;
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}
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static ssize_t open_eth_receive(VLANClientState *nc,
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static ssize_t open_eth_receive(VLANClientState *nc,
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const uint8_t *buf, size_t size)
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const uint8_t *buf, size_t size)
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{
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{
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28
hw/pci.c
28
hw/pci.c
@ -63,6 +63,7 @@ struct BusInfo pci_bus_info = {
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}
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}
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};
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};
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static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num);
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static void pci_update_mappings(PCIDevice *d);
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static void pci_update_mappings(PCIDevice *d);
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static void pci_set_irq(void *opaque, int irq_num, int level);
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static void pci_set_irq(void *opaque, int irq_num, int level);
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static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom);
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static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom);
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@ -478,7 +479,7 @@ static void pci_set_default_subsystem_id(PCIDevice *pci_dev)
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* Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
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* Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
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* [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
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* [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
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*/
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*/
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int pci_parse_devaddr(const char *addr, int *domp, int *busp,
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static int pci_parse_devaddr(const char *addr, int *domp, int *busp,
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unsigned int *slotp, unsigned int *funcp)
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unsigned int *slotp, unsigned int *funcp)
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{
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{
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const char *p;
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const char *p;
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@ -529,10 +530,6 @@ int pci_parse_devaddr(const char *addr, int *domp, int *busp,
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if (*e)
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if (*e)
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return -1;
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return -1;
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/* Note: QEMU doesn't implement domains other than 0 */
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if (!pci_find_bus(pci_find_root_bus(dom), bus))
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return -1;
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*domp = dom;
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*domp = dom;
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*busp = bus;
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*busp = bus;
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*slotp = slot;
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*slotp = slot;
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@ -562,7 +559,7 @@ PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
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if (!devaddr) {
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if (!devaddr) {
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*devfnp = -1;
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*devfnp = -1;
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return pci_find_bus(pci_find_root_bus(0), 0);
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return pci_find_bus_nr(pci_find_root_bus(0), 0);
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}
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}
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if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) {
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if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) {
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@ -570,7 +567,7 @@ PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
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}
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}
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*devfnp = PCI_DEVFN(slot, 0);
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*devfnp = PCI_DEVFN(slot, 0);
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return pci_find_bus(pci_find_root_bus(dom), bus);
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return pci_find_bus_nr(pci_find_root_bus(dom), bus);
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}
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}
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static void pci_init_cmask(PCIDevice *dev)
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static void pci_init_cmask(PCIDevice *dev)
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@ -636,8 +633,8 @@ static void pci_init_mask_bridge(PCIDevice *d)
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memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
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memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
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/* Supported memory and i/o types */
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/* Supported memory and i/o types */
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d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_32;
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d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16;
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d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_32;
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d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16;
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pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE,
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pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE,
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PCI_PREF_RANGE_TYPE_64);
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PCI_PREF_RANGE_TYPE_64);
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pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT,
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pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT,
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@ -666,8 +663,11 @@ static void pci_init_mask_bridge(PCIDevice *d)
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pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL,
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pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL,
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PCI_BRIDGE_CTL_DISCARD_STATUS);
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PCI_BRIDGE_CTL_DISCARD_STATUS);
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d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK;
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d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK;
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d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK;
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pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE,
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pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE,
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PCI_PREF_RANGE_TYPE_MASK);
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PCI_PREF_RANGE_TYPE_MASK);
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pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT,
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PCI_PREF_RANGE_TYPE_MASK);
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}
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}
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static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev)
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static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev)
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@ -1143,7 +1143,7 @@ static void pci_for_each_device_under_bus(PCIBus *bus,
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void pci_for_each_device(PCIBus *bus, int bus_num,
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void pci_for_each_device(PCIBus *bus, int bus_num,
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void (*fn)(PCIBus *b, PCIDevice *d))
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void (*fn)(PCIBus *b, PCIDevice *d))
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{
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{
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bus = pci_find_bus(bus, bus_num);
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bus = pci_find_bus_nr(bus, bus_num);
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if (bus) {
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if (bus) {
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pci_for_each_device_under_bus(bus, fn);
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pci_for_each_device_under_bus(bus, fn);
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@ -1230,7 +1230,7 @@ static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus,
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info->bus.prefetchable_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
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info->bus.prefetchable_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
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if (dev->config[PCI_SECONDARY_BUS] != 0) {
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if (dev->config[PCI_SECONDARY_BUS] != 0) {
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PCIBus *child_bus = pci_find_bus(bus, dev->config[PCI_SECONDARY_BUS]);
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PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]);
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if (child_bus) {
|
if (child_bus) {
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info->has_devices = true;
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info->has_devices = true;
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info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]);
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info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]);
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@ -1309,7 +1309,7 @@ static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num)
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{
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{
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PciInfo *info = NULL;
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PciInfo *info = NULL;
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bus = pci_find_bus(bus, bus_num);
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bus = pci_find_bus_nr(bus, bus_num);
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if (bus) {
|
if (bus) {
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info = g_malloc0(sizeof(*info));
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info = g_malloc0(sizeof(*info));
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info->bus = bus_num;
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info->bus = bus_num;
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@ -1419,7 +1419,7 @@ static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num)
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bus_num <= dev->config[PCI_SUBORDINATE_BUS];
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bus_num <= dev->config[PCI_SUBORDINATE_BUS];
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}
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}
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PCIBus *pci_find_bus(PCIBus *bus, int bus_num)
|
static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num)
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{
|
{
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PCIBus *sec;
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PCIBus *sec;
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@ -1455,7 +1455,7 @@ PCIBus *pci_find_bus(PCIBus *bus, int bus_num)
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|
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PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn)
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PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn)
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{
|
{
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bus = pci_find_bus(bus, bus_num);
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bus = pci_find_bus_nr(bus, bus_num);
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if (!bus)
|
if (!bus)
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return NULL;
|
return NULL;
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11
hw/pci.h
11
hw/pci.h
@ -126,6 +126,11 @@ enum {
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/* command register SERR bit enabled */
|
/* command register SERR bit enabled */
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#define QEMU_PCI_CAP_SERR_BITNR 4
|
#define QEMU_PCI_CAP_SERR_BITNR 4
|
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QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
|
QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
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|
/* Standard hot plug controller. */
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|
#define QEMU_PCI_SHPC_BITNR 5
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|
QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR),
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|
#define QEMU_PCI_SLOTID_BITNR 6
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|
QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR),
|
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};
|
};
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|
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#define TYPE_PCI_DEVICE "pci-device"
|
#define TYPE_PCI_DEVICE "pci-device"
|
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@ -230,6 +235,9 @@ struct PCIDevice {
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/* PCI Express */
|
/* PCI Express */
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PCIExpressDevice exp;
|
PCIExpressDevice exp;
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|
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|
/* SHPC */
|
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|
SHPCDevice *shpc;
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|
|
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/* Location of option rom */
|
/* Location of option rom */
|
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char *romfile;
|
char *romfile;
|
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bool has_rom;
|
bool has_rom;
|
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@ -299,13 +307,10 @@ int pci_bus_num(PCIBus *s);
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void pci_for_each_device(PCIBus *bus, int bus_num, void (*fn)(PCIBus *bus, PCIDevice *d));
|
void pci_for_each_device(PCIBus *bus, int bus_num, void (*fn)(PCIBus *bus, PCIDevice *d));
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PCIBus *pci_find_root_bus(int domain);
|
PCIBus *pci_find_root_bus(int domain);
|
||||||
int pci_find_domain(const PCIBus *bus);
|
int pci_find_domain(const PCIBus *bus);
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PCIBus *pci_find_bus(PCIBus *bus, int bus_num);
|
|
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PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
|
PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
|
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int pci_qdev_find_device(const char *id, PCIDevice **pdev);
|
int pci_qdev_find_device(const char *id, PCIDevice **pdev);
|
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PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr);
|
PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr);
|
||||||
|
|
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int pci_parse_devaddr(const char *addr, int *domp, int *busp,
|
|
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unsigned int *slotp, unsigned int *funcp);
|
|
||||||
int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
|
int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
|
||||||
unsigned *slotp);
|
unsigned *slotp);
|
||||||
|
|
||||||
|
|||||||
@ -249,8 +249,8 @@ void pci_bridge_disable_base_limit(PCIDevice *dev)
|
|||||||
PCI_PREF_RANGE_MASK & 0xffff);
|
PCI_PREF_RANGE_MASK & 0xffff);
|
||||||
pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_LIMIT,
|
pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_LIMIT,
|
||||||
PCI_PREF_RANGE_MASK & 0xffff);
|
PCI_PREF_RANGE_MASK & 0xffff);
|
||||||
pci_set_word(conf + PCI_PREF_BASE_UPPER32, 0);
|
pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0);
|
||||||
pci_set_word(conf + PCI_PREF_LIMIT_UPPER32, 0);
|
pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* reset bridge specific configuration registers */
|
/* reset bridge specific configuration registers */
|
||||||
@ -285,8 +285,8 @@ void pci_bridge_reset_reg(PCIDevice *dev)
|
|||||||
PCI_PREF_RANGE_MASK & 0xffff);
|
PCI_PREF_RANGE_MASK & 0xffff);
|
||||||
pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_LIMIT,
|
pci_word_test_and_clear_mask(conf + PCI_PREF_MEMORY_LIMIT,
|
||||||
PCI_PREF_RANGE_MASK & 0xffff);
|
PCI_PREF_RANGE_MASK & 0xffff);
|
||||||
pci_set_word(conf + PCI_PREF_BASE_UPPER32, 0);
|
pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0);
|
||||||
pci_set_word(conf + PCI_PREF_LIMIT_UPPER32, 0);
|
pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0);
|
||||||
|
|
||||||
pci_set_word(conf + PCI_BRIDGE_CONTROL, 0);
|
pci_set_word(conf + PCI_BRIDGE_CONTROL, 0);
|
||||||
}
|
}
|
||||||
@ -305,8 +305,8 @@ int pci_bridge_initfn(PCIDevice *dev)
|
|||||||
PCIBridge *br = DO_UPCAST(PCIBridge, dev, dev);
|
PCIBridge *br = DO_UPCAST(PCIBridge, dev, dev);
|
||||||
PCIBus *sec_bus = &br->sec_bus;
|
PCIBus *sec_bus = &br->sec_bus;
|
||||||
|
|
||||||
pci_set_word(dev->config + PCI_STATUS,
|
pci_word_test_and_set_mask(dev->config + PCI_STATUS,
|
||||||
PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
|
PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
|
||||||
pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_PCI);
|
pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_PCI);
|
||||||
dev->config[PCI_HEADER_TYPE] =
|
dev->config[PCI_HEADER_TYPE] =
|
||||||
(dev->config[PCI_HEADER_TYPE] & PCI_HEADER_TYPE_MULTI_FUNCTION) |
|
(dev->config[PCI_HEADER_TYPE] & PCI_HEADER_TYPE_MULTI_FUNCTION) |
|
||||||
@ -314,6 +314,16 @@ int pci_bridge_initfn(PCIDevice *dev)
|
|||||||
pci_set_word(dev->config + PCI_SEC_STATUS,
|
pci_set_word(dev->config + PCI_SEC_STATUS,
|
||||||
PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
|
PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* If we don't specify the name, the bus will be addressed as <id>.0, where
|
||||||
|
* id is the device id.
|
||||||
|
* Since PCI Bridge devices have a single bus each, we don't need the index:
|
||||||
|
* let users address the bus using the device name.
|
||||||
|
*/
|
||||||
|
if (!br->bus_name && dev->qdev.id && *dev->qdev.id) {
|
||||||
|
br->bus_name = dev->qdev.id;
|
||||||
|
}
|
||||||
|
|
||||||
qbus_create_inplace(&sec_bus->qbus, &pci_bus_info, &dev->qdev,
|
qbus_create_inplace(&sec_bus->qbus, &pci_bus_info, &dev->qdev,
|
||||||
br->bus_name);
|
br->bus_name);
|
||||||
sec_bus->parent_dev = dev;
|
sec_bus->parent_dev = dev;
|
||||||
|
|||||||
174
hw/pci_bridge_dev.c
Normal file
174
hw/pci_bridge_dev.c
Normal file
@ -0,0 +1,174 @@
|
|||||||
|
/*
|
||||||
|
* Standard PCI Bridge Device
|
||||||
|
*
|
||||||
|
* Copyright (c) 2011 Red Hat Inc. Author: Michael S. Tsirkin <mst@redhat.com>
|
||||||
|
*
|
||||||
|
* http://www.pcisig.com/specifications/conventional/pci_to_pci_bridge_architecture/
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License along
|
||||||
|
* with this program; if not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "pci_bridge.h"
|
||||||
|
#include "pci_ids.h"
|
||||||
|
#include "msi.h"
|
||||||
|
#include "shpc.h"
|
||||||
|
#include "slotid_cap.h"
|
||||||
|
#include "memory.h"
|
||||||
|
#include "pci_internals.h"
|
||||||
|
|
||||||
|
#define REDHAT_PCI_VENDOR_ID 0x1b36
|
||||||
|
#define PCI_BRIDGE_DEV_VENDOR_ID REDHAT_PCI_VENDOR_ID
|
||||||
|
#define PCI_BRIDGE_DEV_DEVICE_ID 0x1
|
||||||
|
|
||||||
|
struct PCIBridgeDev {
|
||||||
|
PCIBridge bridge;
|
||||||
|
MemoryRegion bar;
|
||||||
|
uint8_t chassis_nr;
|
||||||
|
#define PCI_BRIDGE_DEV_F_MSI_REQ 0
|
||||||
|
uint32_t flags;
|
||||||
|
};
|
||||||
|
typedef struct PCIBridgeDev PCIBridgeDev;
|
||||||
|
|
||||||
|
/* Mapping mandated by PCI-to-PCI Bridge architecture specification,
|
||||||
|
* revision 1.2 */
|
||||||
|
/* Table 9-1: Interrupt Binding for Devices Behind a Bridge */
|
||||||
|
static int pci_bridge_dev_map_irq_fn(PCIDevice *dev, int irq_num)
|
||||||
|
{
|
||||||
|
return (irq_num + PCI_SLOT(dev->devfn)) % PCI_NUM_PINS;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int pci_bridge_dev_initfn(PCIDevice *dev)
|
||||||
|
{
|
||||||
|
PCIBridge *br = DO_UPCAST(PCIBridge, dev, dev);
|
||||||
|
PCIBridgeDev *bridge_dev = DO_UPCAST(PCIBridgeDev, bridge, br);
|
||||||
|
int err;
|
||||||
|
pci_bridge_map_irq(br, NULL, pci_bridge_dev_map_irq_fn);
|
||||||
|
err = pci_bridge_initfn(dev);
|
||||||
|
if (err) {
|
||||||
|
goto bridge_error;
|
||||||
|
}
|
||||||
|
memory_region_init(&bridge_dev->bar, "shpc-bar", shpc_bar_size(dev));
|
||||||
|
err = shpc_init(dev, &br->sec_bus, &bridge_dev->bar, 0);
|
||||||
|
if (err) {
|
||||||
|
goto shpc_error;
|
||||||
|
}
|
||||||
|
err = slotid_cap_init(dev, 0, bridge_dev->chassis_nr, 0);
|
||||||
|
if (err) {
|
||||||
|
goto slotid_error;
|
||||||
|
}
|
||||||
|
if ((bridge_dev->flags & (1 << PCI_BRIDGE_DEV_F_MSI_REQ)) &&
|
||||||
|
msi_supported) {
|
||||||
|
err = msi_init(dev, 0, 1, true, true);
|
||||||
|
if (err < 0) {
|
||||||
|
goto msi_error;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
/* TODO: spec recommends using 64 bit prefetcheable BAR.
|
||||||
|
* Check whether that works well. */
|
||||||
|
pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY |
|
||||||
|
PCI_BASE_ADDRESS_MEM_TYPE_64, &bridge_dev->bar);
|
||||||
|
dev->config[PCI_INTERRUPT_PIN] = 0x1;
|
||||||
|
return 0;
|
||||||
|
msi_error:
|
||||||
|
slotid_cap_cleanup(dev);
|
||||||
|
slotid_error:
|
||||||
|
shpc_cleanup(dev, &bridge_dev->bar);
|
||||||
|
shpc_error:
|
||||||
|
memory_region_destroy(&bridge_dev->bar);
|
||||||
|
bridge_error:
|
||||||
|
return err;
|
||||||
|
}
|
||||||
|
|
||||||
|
static int pci_bridge_dev_exitfn(PCIDevice *dev)
|
||||||
|
{
|
||||||
|
PCIBridge *br = DO_UPCAST(PCIBridge, dev, dev);
|
||||||
|
PCIBridgeDev *bridge_dev = DO_UPCAST(PCIBridgeDev, bridge, br);
|
||||||
|
int ret;
|
||||||
|
if (msi_present(dev)) {
|
||||||
|
msi_uninit(dev);
|
||||||
|
}
|
||||||
|
slotid_cap_cleanup(dev);
|
||||||
|
shpc_cleanup(dev, &bridge_dev->bar);
|
||||||
|
memory_region_destroy(&bridge_dev->bar);
|
||||||
|
ret = pci_bridge_exitfn(dev);
|
||||||
|
assert(!ret);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void pci_bridge_dev_write_config(PCIDevice *d,
|
||||||
|
uint32_t address, uint32_t val, int len)
|
||||||
|
{
|
||||||
|
pci_bridge_write_config(d, address, val, len);
|
||||||
|
if (msi_present(d)) {
|
||||||
|
msi_write_config(d, address, val, len);
|
||||||
|
}
|
||||||
|
shpc_cap_write_config(d, address, val, len);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void qdev_pci_bridge_dev_reset(DeviceState *qdev)
|
||||||
|
{
|
||||||
|
PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev);
|
||||||
|
pci_bridge_reset(qdev);
|
||||||
|
if (msi_present(dev)) {
|
||||||
|
msi_reset(dev);
|
||||||
|
}
|
||||||
|
shpc_reset(dev);
|
||||||
|
}
|
||||||
|
|
||||||
|
static Property pci_bridge_dev_properties[] = {
|
||||||
|
/* Note: 0 is not a legal chassis number. */
|
||||||
|
DEFINE_PROP_UINT8("chassis_nr", PCIBridgeDev, chassis_nr, 0),
|
||||||
|
DEFINE_PROP_BIT("msi", PCIBridgeDev, flags, PCI_BRIDGE_DEV_F_MSI_REQ, true),
|
||||||
|
DEFINE_PROP_END_OF_LIST(),
|
||||||
|
};
|
||||||
|
|
||||||
|
static const VMStateDescription pci_bridge_dev_vmstate = {
|
||||||
|
.name = "pci_bridge",
|
||||||
|
.fields = (VMStateField[]) {
|
||||||
|
VMSTATE_PCI_DEVICE(bridge.dev, PCIBridgeDev),
|
||||||
|
SHPC_VMSTATE(bridge.dev.shpc, PCIBridgeDev),
|
||||||
|
VMSTATE_END_OF_LIST()
|
||||||
|
}
|
||||||
|
};
|
||||||
|
|
||||||
|
static void pci_bridge_dev_class_init(ObjectClass *klass, void *data)
|
||||||
|
{
|
||||||
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
||||||
|
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
|
||||||
|
k->init = pci_bridge_dev_initfn;
|
||||||
|
k->exit = pci_bridge_dev_exitfn;
|
||||||
|
k->config_write = pci_bridge_dev_write_config;
|
||||||
|
k->vendor_id = PCI_BRIDGE_DEV_VENDOR_ID;
|
||||||
|
k->device_id = PCI_BRIDGE_DEV_DEVICE_ID;
|
||||||
|
k->class_id = PCI_CLASS_BRIDGE_PCI;
|
||||||
|
k->is_bridge = 1,
|
||||||
|
dc->desc = "Standard PCI Bridge";
|
||||||
|
dc->reset = qdev_pci_bridge_dev_reset;
|
||||||
|
dc->props = pci_bridge_dev_properties;
|
||||||
|
dc->vmsd = &pci_bridge_dev_vmstate;
|
||||||
|
}
|
||||||
|
|
||||||
|
static TypeInfo pci_bridge_dev_info = {
|
||||||
|
.name = "pci-bridge",
|
||||||
|
.parent = TYPE_PCI_DEVICE,
|
||||||
|
.instance_size = sizeof(PCIBridgeDev),
|
||||||
|
.class_init = pci_bridge_dev_class_init,
|
||||||
|
};
|
||||||
|
|
||||||
|
static void pci_bridge_dev_register(void)
|
||||||
|
{
|
||||||
|
type_register_static(&pci_bridge_dev_info);
|
||||||
|
}
|
||||||
|
|
||||||
|
type_init(pci_bridge_dev_register);
|
||||||
@ -392,8 +392,9 @@
|
|||||||
#define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */
|
#define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */
|
||||||
#define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
|
#define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
|
||||||
#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */
|
#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */
|
||||||
|
#define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIE Bridge */
|
||||||
#define PCI_EXP_TYPE_RC_END 0x9 /* Root Complex Integrated Endpoint */
|
#define PCI_EXP_TYPE_RC_END 0x9 /* Root Complex Integrated Endpoint */
|
||||||
#define PCI_EXP_TYPE_RC_EC 0x10 /* Root Complex Event Collector */
|
#define PCI_EXP_TYPE_RC_EC 0xa /* Root Complex Event Collector */
|
||||||
#define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
|
#define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
|
||||||
#define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */
|
#define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */
|
||||||
#define PCI_EXP_DEVCAP 4 /* Device capabilities */
|
#define PCI_EXP_DEVCAP 4 /* Device capabilities */
|
||||||
|
|||||||
@ -27,23 +27,13 @@ void pcie_port_init_reg(PCIDevice *d)
|
|||||||
pci_set_word(d->config + PCI_STATUS, 0);
|
pci_set_word(d->config + PCI_STATUS, 0);
|
||||||
pci_set_word(d->config + PCI_SEC_STATUS, 0);
|
pci_set_word(d->config + PCI_SEC_STATUS, 0);
|
||||||
|
|
||||||
/* Unlike conventional pci bridge, some bits are hardwared to 0. */
|
/* Unlike conventional pci bridge, some bits are hardwired to 0. */
|
||||||
pci_set_word(d->wmask + PCI_BRIDGE_CONTROL,
|
pci_set_word(d->wmask + PCI_BRIDGE_CONTROL,
|
||||||
PCI_BRIDGE_CTL_PARITY |
|
PCI_BRIDGE_CTL_PARITY |
|
||||||
PCI_BRIDGE_CTL_ISA |
|
PCI_BRIDGE_CTL_ISA |
|
||||||
PCI_BRIDGE_CTL_VGA |
|
PCI_BRIDGE_CTL_VGA |
|
||||||
PCI_BRIDGE_CTL_SERR |
|
PCI_BRIDGE_CTL_SERR |
|
||||||
PCI_BRIDGE_CTL_BUS_RESET);
|
PCI_BRIDGE_CTL_BUS_RESET);
|
||||||
|
|
||||||
/* 7.5.3.5 Prefetchable Memory Base Limit
|
|
||||||
* The Prefetchable Memory Base and Prefetchable Memory Limit registers
|
|
||||||
* must indicate that 64-bit addresses are supported, as defined in
|
|
||||||
* PCI-to-PCI Bridge Architecture Specification, Revision 1.2.
|
|
||||||
*/
|
|
||||||
pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE,
|
|
||||||
PCI_PREF_RANGE_TYPE_64);
|
|
||||||
pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT,
|
|
||||||
PCI_PREF_RANGE_TYPE_64);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
/**************************************************************************
|
/**************************************************************************
|
||||||
|
|||||||
88
hw/rtl8139.c
88
hw/rtl8139.c
@ -65,9 +65,6 @@
|
|||||||
|
|
||||||
#define PCI_FREQUENCY 33000000L
|
#define PCI_FREQUENCY 33000000L
|
||||||
|
|
||||||
/* debug RTL8139 card C+ mode only */
|
|
||||||
//#define DEBUG_RTL8139CP 1
|
|
||||||
|
|
||||||
#define SET_MASKED(input, mask, curr) \
|
#define SET_MASKED(input, mask, curr) \
|
||||||
( ( (input) & ~(mask) ) | ( (curr) & (mask) ) )
|
( ( (input) & ~(mask) ) | ( (curr) & (mask) ) )
|
||||||
|
|
||||||
@ -335,8 +332,10 @@ enum CSCRBits {
|
|||||||
};
|
};
|
||||||
|
|
||||||
enum Cfg9346Bits {
|
enum Cfg9346Bits {
|
||||||
Cfg9346_Lock = 0x00,
|
Cfg9346_Normal = 0x00,
|
||||||
Cfg9346_Unlock = 0xC0,
|
Cfg9346_Autoload = 0x40,
|
||||||
|
Cfg9346_Programming = 0x80,
|
||||||
|
Cfg9346_ConfigWrite = 0xC0,
|
||||||
};
|
};
|
||||||
|
|
||||||
typedef enum {
|
typedef enum {
|
||||||
@ -711,30 +710,6 @@ static void rtl8139_update_irq(RTL8139State *s)
|
|||||||
qemu_set_irq(s->dev.irq[0], (isr != 0));
|
qemu_set_irq(s->dev.irq[0], (isr != 0));
|
||||||
}
|
}
|
||||||
|
|
||||||
#define POLYNOMIAL 0x04c11db6
|
|
||||||
|
|
||||||
/* From FreeBSD */
|
|
||||||
/* XXX: optimize */
|
|
||||||
static int compute_mcast_idx(const uint8_t *ep)
|
|
||||||
{
|
|
||||||
uint32_t crc;
|
|
||||||
int carry, i, j;
|
|
||||||
uint8_t b;
|
|
||||||
|
|
||||||
crc = 0xffffffff;
|
|
||||||
for (i = 0; i < 6; i++) {
|
|
||||||
b = *ep++;
|
|
||||||
for (j = 0; j < 8; j++) {
|
|
||||||
carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
|
|
||||||
crc <<= 1;
|
|
||||||
b >>= 1;
|
|
||||||
if (carry)
|
|
||||||
crc = ((crc ^ POLYNOMIAL) | carry);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
return (crc >> 26);
|
|
||||||
}
|
|
||||||
|
|
||||||
static int rtl8139_RxWrap(RTL8139State *s)
|
static int rtl8139_RxWrap(RTL8139State *s)
|
||||||
{
|
{
|
||||||
/* wrapping enabled; assume 1.5k more buffer space if size < 65536 */
|
/* wrapping enabled; assume 1.5k more buffer space if size < 65536 */
|
||||||
@ -816,6 +791,9 @@ static int rtl8139_can_receive(VLANClientState *nc)
|
|||||||
return 1;
|
return 1;
|
||||||
if (!rtl8139_receiver_enabled(s))
|
if (!rtl8139_receiver_enabled(s))
|
||||||
return 1;
|
return 1;
|
||||||
|
/* network/host communication happens only in normal mode */
|
||||||
|
if ((s->Cfg9346 & Chip9346_op_mask) != Cfg9346_Normal)
|
||||||
|
return 0;
|
||||||
|
|
||||||
if (rtl8139_cp_receiver_enabled(s)) {
|
if (rtl8139_cp_receiver_enabled(s)) {
|
||||||
/* ??? Flow control not implemented in c+ mode.
|
/* ??? Flow control not implemented in c+ mode.
|
||||||
@ -858,6 +836,12 @@ static ssize_t rtl8139_do_receive(VLANClientState *nc, const uint8_t *buf, size_
|
|||||||
return -1;
|
return -1;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/* check whether we are in normal mode */
|
||||||
|
if ((s->Cfg9346 & Chip9346_op_mask) != Cfg9346_Normal) {
|
||||||
|
DPRINTF("not in normal op mode\n");
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
/* XXX: check this */
|
/* XXX: check this */
|
||||||
if (s->RxConfig & AcceptAllPhys) {
|
if (s->RxConfig & AcceptAllPhys) {
|
||||||
/* promiscuous: receive all */
|
/* promiscuous: receive all */
|
||||||
@ -1478,7 +1462,7 @@ static uint32_t rtl8139_IntrMitigate_read(RTL8139State *s)
|
|||||||
|
|
||||||
static int rtl8139_config_writable(RTL8139State *s)
|
static int rtl8139_config_writable(RTL8139State *s)
|
||||||
{
|
{
|
||||||
if (s->Cfg9346 & Cfg9346_Unlock)
|
if ((s->Cfg9346 & Chip9346_op_mask) == Cfg9346_ConfigWrite)
|
||||||
{
|
{
|
||||||
return 1;
|
return 1;
|
||||||
}
|
}
|
||||||
@ -2061,13 +2045,12 @@ static int rtl8139_cplus_transmit_one(RTL8139State *s)
|
|||||||
s->cplus_txbuffer_len);
|
s->cplus_txbuffer_len);
|
||||||
}
|
}
|
||||||
|
|
||||||
while (s->cplus_txbuffer && s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len)
|
if (s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len)
|
||||||
{
|
{
|
||||||
s->cplus_txbuffer_len += CP_TX_BUFFER_SIZE;
|
/* The spec didn't tell the maximum size, stick to CP_TX_BUFFER_SIZE */
|
||||||
s->cplus_txbuffer = g_realloc(s->cplus_txbuffer, s->cplus_txbuffer_len);
|
txsize = s->cplus_txbuffer_len - s->cplus_txbuffer_offset;
|
||||||
|
DPRINTF("+++ C+ mode transmission buffer overrun, truncated descriptor"
|
||||||
DPRINTF("+++ C+ mode transmission buffer space changed to %d\n",
|
"length to %d\n", txsize);
|
||||||
s->cplus_txbuffer_len);
|
|
||||||
}
|
}
|
||||||
|
|
||||||
if (!s->cplus_txbuffer)
|
if (!s->cplus_txbuffer)
|
||||||
@ -2499,11 +2482,30 @@ static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32
|
|||||||
rtl8139_transmit(s);
|
rtl8139_transmit(s);
|
||||||
}
|
}
|
||||||
|
|
||||||
static uint32_t rtl8139_TxStatus_read(RTL8139State *s, uint32_t txRegOffset)
|
static uint32_t rtl8139_TxStatus_read(RTL8139State *s, uint8_t addr, int size)
|
||||||
{
|
{
|
||||||
uint32_t ret = s->TxStatus[txRegOffset/4];
|
uint32_t reg = (addr - TxStatus0) / 4;
|
||||||
|
uint32_t offset = addr & 0x3;
|
||||||
|
uint32_t ret = 0;
|
||||||
|
|
||||||
DPRINTF("TxStatus read offset=0x%x val=0x%08x\n", txRegOffset, ret);
|
if (addr & (size - 1)) {
|
||||||
|
DPRINTF("not implemented read for TxStatus addr=0x%x size=0x%x\n", addr,
|
||||||
|
size);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
switch (size) {
|
||||||
|
case 1: /* fall through */
|
||||||
|
case 2: /* fall through */
|
||||||
|
case 4:
|
||||||
|
ret = (s->TxStatus[reg] >> offset * 8) & ((1 << (size * 8)) - 1);
|
||||||
|
DPRINTF("TxStatus[%d] read addr=0x%x size=0x%x val=0x%08x\n", reg, addr,
|
||||||
|
size, ret);
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
DPRINTF("unsupported size 0x%x of TxStatus reading\n", size);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
return ret;
|
return ret;
|
||||||
}
|
}
|
||||||
@ -2974,6 +2976,9 @@ static uint32_t rtl8139_io_readb(void *opaque, uint8_t addr)
|
|||||||
case MAR0 ... MAR0+7:
|
case MAR0 ... MAR0+7:
|
||||||
ret = s->mult[addr - MAR0];
|
ret = s->mult[addr - MAR0];
|
||||||
break;
|
break;
|
||||||
|
case TxStatus0 ... TxStatus0+4*4-1:
|
||||||
|
ret = rtl8139_TxStatus_read(s, addr, 1);
|
||||||
|
break;
|
||||||
case ChipCmd:
|
case ChipCmd:
|
||||||
ret = rtl8139_ChipCmd_read(s);
|
ret = rtl8139_ChipCmd_read(s);
|
||||||
break;
|
break;
|
||||||
@ -3037,6 +3042,9 @@ static uint32_t rtl8139_io_readw(void *opaque, uint8_t addr)
|
|||||||
|
|
||||||
switch (addr)
|
switch (addr)
|
||||||
{
|
{
|
||||||
|
case TxAddr0 ... TxAddr0+4*4-1:
|
||||||
|
ret = rtl8139_TxStatus_read(s, addr, 2);
|
||||||
|
break;
|
||||||
case IntrMask:
|
case IntrMask:
|
||||||
ret = rtl8139_IntrMask_read(s);
|
ret = rtl8139_IntrMask_read(s);
|
||||||
break;
|
break;
|
||||||
@ -3127,7 +3135,7 @@ static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr)
|
|||||||
break;
|
break;
|
||||||
|
|
||||||
case TxStatus0 ... TxStatus0+4*4-1:
|
case TxStatus0 ... TxStatus0+4*4-1:
|
||||||
ret = rtl8139_TxStatus_read(s, addr-TxStatus0);
|
ret = rtl8139_TxStatus_read(s, addr, 4);
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case TxAddr0 ... TxAddr0+4*4-1:
|
case TxAddr0 ... TxAddr0+4*4-1:
|
||||||
|
|||||||
681
hw/shpc.c
Normal file
681
hw/shpc.c
Normal file
@ -0,0 +1,681 @@
|
|||||||
|
#include <strings.h>
|
||||||
|
#include <stdint.h>
|
||||||
|
#include "range.h"
|
||||||
|
#include "range.h"
|
||||||
|
#include "shpc.h"
|
||||||
|
#include "pci.h"
|
||||||
|
#include "pci_internals.h"
|
||||||
|
#include "msi.h"
|
||||||
|
|
||||||
|
/* TODO: model power only and disabled slot states. */
|
||||||
|
/* TODO: handle SERR and wakeups */
|
||||||
|
/* TODO: consider enabling 66MHz support */
|
||||||
|
|
||||||
|
/* TODO: remove fully only on state DISABLED and LED off.
|
||||||
|
* track state to properly record this. */
|
||||||
|
|
||||||
|
/* SHPC Working Register Set */
|
||||||
|
#define SHPC_BASE_OFFSET 0x00 /* 4 bytes */
|
||||||
|
#define SHPC_SLOTS_33 0x04 /* 4 bytes. Also encodes PCI-X slots. */
|
||||||
|
#define SHPC_SLOTS_66 0x08 /* 4 bytes. */
|
||||||
|
#define SHPC_NSLOTS 0x0C /* 1 byte */
|
||||||
|
#define SHPC_FIRST_DEV 0x0D /* 1 byte */
|
||||||
|
#define SHPC_PHYS_SLOT 0x0E /* 2 byte */
|
||||||
|
#define SHPC_PHYS_NUM_MAX 0x7ff
|
||||||
|
#define SHPC_PHYS_NUM_UP 0x2000
|
||||||
|
#define SHPC_PHYS_MRL 0x4000
|
||||||
|
#define SHPC_PHYS_BUTTON 0x8000
|
||||||
|
#define SHPC_SEC_BUS 0x10 /* 2 bytes */
|
||||||
|
#define SHPC_SEC_BUS_33 0x0
|
||||||
|
#define SHPC_SEC_BUS_66 0x1 /* Unused */
|
||||||
|
#define SHPC_SEC_BUS_MASK 0x7
|
||||||
|
#define SHPC_MSI_CTL 0x12 /* 1 byte */
|
||||||
|
#define SHPC_PROG_IFC 0x13 /* 1 byte */
|
||||||
|
#define SHPC_PROG_IFC_1_0 0x1
|
||||||
|
#define SHPC_CMD_CODE 0x14 /* 1 byte */
|
||||||
|
#define SHPC_CMD_TRGT 0x15 /* 1 byte */
|
||||||
|
#define SHPC_CMD_TRGT_MIN 0x1
|
||||||
|
#define SHPC_CMD_TRGT_MAX 0x1f
|
||||||
|
#define SHPC_CMD_STATUS 0x16 /* 2 bytes */
|
||||||
|
#define SHPC_CMD_STATUS_BUSY 0x1
|
||||||
|
#define SHPC_CMD_STATUS_MRL_OPEN 0x2
|
||||||
|
#define SHPC_CMD_STATUS_INVALID_CMD 0x4
|
||||||
|
#define SHPC_CMD_STATUS_INVALID_MODE 0x8
|
||||||
|
#define SHPC_INT_LOCATOR 0x18 /* 4 bytes */
|
||||||
|
#define SHPC_INT_COMMAND 0x1
|
||||||
|
#define SHPC_SERR_LOCATOR 0x1C /* 4 bytes */
|
||||||
|
#define SHPC_SERR_INT 0x20 /* 4 bytes */
|
||||||
|
#define SHPC_INT_DIS 0x1
|
||||||
|
#define SHPC_SERR_DIS 0x2
|
||||||
|
#define SHPC_CMD_INT_DIS 0x4
|
||||||
|
#define SHPC_ARB_SERR_DIS 0x8
|
||||||
|
#define SHPC_CMD_DETECTED 0x10000
|
||||||
|
#define SHPC_ARB_DETECTED 0x20000
|
||||||
|
/* 4 bytes * slot # (start from 0) */
|
||||||
|
#define SHPC_SLOT_REG(s) (0x24 + (s) * 4)
|
||||||
|
/* 2 bytes */
|
||||||
|
#define SHPC_SLOT_STATUS(s) (0x0 + SHPC_SLOT_REG(s))
|
||||||
|
|
||||||
|
/* Same slot state masks are used for command and status registers */
|
||||||
|
#define SHPC_SLOT_STATE_MASK 0x03
|
||||||
|
#define SHPC_SLOT_STATE_SHIFT \
|
||||||
|
(ffs(SHPC_SLOT_STATE_MASK) - 1)
|
||||||
|
|
||||||
|
#define SHPC_STATE_NO 0x0
|
||||||
|
#define SHPC_STATE_PWRONLY 0x1
|
||||||
|
#define SHPC_STATE_ENABLED 0x2
|
||||||
|
#define SHPC_STATE_DISABLED 0x3
|
||||||
|
|
||||||
|
#define SHPC_SLOT_PWR_LED_MASK 0xC
|
||||||
|
#define SHPC_SLOT_PWR_LED_SHIFT \
|
||||||
|
(ffs(SHPC_SLOT_PWR_LED_MASK) - 1)
|
||||||
|
#define SHPC_SLOT_ATTN_LED_MASK 0x30
|
||||||
|
#define SHPC_SLOT_ATTN_LED_SHIFT \
|
||||||
|
(ffs(SHPC_SLOT_ATTN_LED_MASK) - 1)
|
||||||
|
|
||||||
|
#define SHPC_LED_NO 0x0
|
||||||
|
#define SHPC_LED_ON 0x1
|
||||||
|
#define SHPC_LED_BLINK 0x2
|
||||||
|
#define SHPC_LED_OFF 0x3
|
||||||
|
|
||||||
|
#define SHPC_SLOT_STATUS_PWR_FAULT 0x40
|
||||||
|
#define SHPC_SLOT_STATUS_BUTTON 0x80
|
||||||
|
#define SHPC_SLOT_STATUS_MRL_OPEN 0x100
|
||||||
|
#define SHPC_SLOT_STATUS_66 0x200
|
||||||
|
#define SHPC_SLOT_STATUS_PRSNT_MASK 0xC00
|
||||||
|
#define SHPC_SLOT_STATUS_PRSNT_EMPTY 0x3
|
||||||
|
#define SHPC_SLOT_STATUS_PRSNT_25W 0x1
|
||||||
|
#define SHPC_SLOT_STATUS_PRSNT_15W 0x2
|
||||||
|
#define SHPC_SLOT_STATUS_PRSNT_7_5W 0x0
|
||||||
|
|
||||||
|
#define SHPC_SLOT_STATUS_PRSNT_PCIX 0x3000
|
||||||
|
|
||||||
|
|
||||||
|
/* 1 byte */
|
||||||
|
#define SHPC_SLOT_EVENT_LATCH(s) (0x2 + SHPC_SLOT_REG(s))
|
||||||
|
/* 1 byte */
|
||||||
|
#define SHPC_SLOT_EVENT_SERR_INT_DIS(d, s) (0x3 + SHPC_SLOT_REG(s))
|
||||||
|
#define SHPC_SLOT_EVENT_PRESENCE 0x01
|
||||||
|
#define SHPC_SLOT_EVENT_ISOLATED_FAULT 0x02
|
||||||
|
#define SHPC_SLOT_EVENT_BUTTON 0x04
|
||||||
|
#define SHPC_SLOT_EVENT_MRL 0x08
|
||||||
|
#define SHPC_SLOT_EVENT_CONNECTED_FAULT 0x10
|
||||||
|
/* Bits below are used for Serr/Int disable only */
|
||||||
|
#define SHPC_SLOT_EVENT_MRL_SERR_DIS 0x20
|
||||||
|
#define SHPC_SLOT_EVENT_CONNECTED_FAULT_SERR_DIS 0x40
|
||||||
|
|
||||||
|
#define SHPC_MIN_SLOTS 1
|
||||||
|
#define SHPC_MAX_SLOTS 31
|
||||||
|
#define SHPC_SIZEOF(d) SHPC_SLOT_REG((d)->shpc->nslots)
|
||||||
|
|
||||||
|
/* SHPC Slot identifiers */
|
||||||
|
|
||||||
|
/* Hotplug supported at 31 slots out of the total 32. We reserve slot 0,
|
||||||
|
and give the rest of them physical *and* pci numbers starting from 1, so
|
||||||
|
they match logical numbers. Note: this means that multiple slots must have
|
||||||
|
different chassis number values, to make chassis+physical slot unique.
|
||||||
|
TODO: make this configurable? */
|
||||||
|
#define SHPC_IDX_TO_LOGICAL(slot) ((slot) + 1)
|
||||||
|
#define SHPC_LOGICAL_TO_IDX(target) ((target) - 1)
|
||||||
|
#define SHPC_IDX_TO_PCI(slot) ((slot) + 1)
|
||||||
|
#define SHPC_PCI_TO_IDX(pci_slot) ((pci_slot) - 1)
|
||||||
|
#define SHPC_IDX_TO_PHYSICAL(slot) ((slot) + 1)
|
||||||
|
|
||||||
|
static int roundup_pow_of_two(int x)
|
||||||
|
{
|
||||||
|
x |= (x >> 1);
|
||||||
|
x |= (x >> 2);
|
||||||
|
x |= (x >> 4);
|
||||||
|
x |= (x >> 8);
|
||||||
|
x |= (x >> 16);
|
||||||
|
return x + 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
static uint16_t shpc_get_status(SHPCDevice *shpc, int slot, uint16_t msk)
|
||||||
|
{
|
||||||
|
uint8_t *status = shpc->config + SHPC_SLOT_STATUS(slot);
|
||||||
|
return (pci_get_word(status) & msk) >> (ffs(msk) - 1);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void shpc_set_status(SHPCDevice *shpc,
|
||||||
|
int slot, uint8_t value, uint16_t msk)
|
||||||
|
{
|
||||||
|
uint8_t *status = shpc->config + SHPC_SLOT_STATUS(slot);
|
||||||
|
pci_word_test_and_clear_mask(status, msk);
|
||||||
|
pci_word_test_and_set_mask(status, value << (ffs(msk) - 1));
|
||||||
|
}
|
||||||
|
|
||||||
|
static void shpc_interrupt_update(PCIDevice *d)
|
||||||
|
{
|
||||||
|
SHPCDevice *shpc = d->shpc;
|
||||||
|
int slot;
|
||||||
|
int level = 0;
|
||||||
|
uint32_t serr_int;
|
||||||
|
uint32_t int_locator = 0;
|
||||||
|
|
||||||
|
/* Update interrupt locator register */
|
||||||
|
for (slot = 0; slot < shpc->nslots; ++slot) {
|
||||||
|
uint8_t event = shpc->config[SHPC_SLOT_EVENT_LATCH(slot)];
|
||||||
|
uint8_t disable = shpc->config[SHPC_SLOT_EVENT_SERR_INT_DIS(d, slot)];
|
||||||
|
uint32_t mask = 1 << SHPC_IDX_TO_LOGICAL(slot);
|
||||||
|
if (event & ~disable) {
|
||||||
|
int_locator |= mask;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
serr_int = pci_get_long(shpc->config + SHPC_SERR_INT);
|
||||||
|
if ((serr_int & SHPC_CMD_DETECTED) && !(serr_int & SHPC_CMD_INT_DIS)) {
|
||||||
|
int_locator |= SHPC_INT_COMMAND;
|
||||||
|
}
|
||||||
|
pci_set_long(shpc->config + SHPC_INT_LOCATOR, int_locator);
|
||||||
|
level = (!(serr_int & SHPC_INT_DIS) && int_locator) ? 1 : 0;
|
||||||
|
if (msi_enabled(d) && shpc->msi_requested != level)
|
||||||
|
msi_notify(d, 0);
|
||||||
|
else
|
||||||
|
qemu_set_irq(d->irq[0], level);
|
||||||
|
shpc->msi_requested = level;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void shpc_set_sec_bus_speed(SHPCDevice *shpc, uint8_t speed)
|
||||||
|
{
|
||||||
|
switch (speed) {
|
||||||
|
case SHPC_SEC_BUS_33:
|
||||||
|
shpc->config[SHPC_SEC_BUS] &= ~SHPC_SEC_BUS_MASK;
|
||||||
|
shpc->config[SHPC_SEC_BUS] |= speed;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
pci_word_test_and_set_mask(shpc->config + SHPC_CMD_STATUS,
|
||||||
|
SHPC_CMD_STATUS_INVALID_MODE);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void shpc_reset(PCIDevice *d)
|
||||||
|
{
|
||||||
|
SHPCDevice *shpc = d->shpc;
|
||||||
|
int nslots = shpc->nslots;
|
||||||
|
int i;
|
||||||
|
memset(shpc->config, 0, SHPC_SIZEOF(d));
|
||||||
|
pci_set_byte(shpc->config + SHPC_NSLOTS, nslots);
|
||||||
|
pci_set_long(shpc->config + SHPC_SLOTS_33, nslots);
|
||||||
|
pci_set_long(shpc->config + SHPC_SLOTS_66, 0);
|
||||||
|
pci_set_byte(shpc->config + SHPC_FIRST_DEV, SHPC_IDX_TO_PCI(0));
|
||||||
|
pci_set_word(shpc->config + SHPC_PHYS_SLOT,
|
||||||
|
SHPC_IDX_TO_PHYSICAL(0) |
|
||||||
|
SHPC_PHYS_NUM_UP |
|
||||||
|
SHPC_PHYS_MRL |
|
||||||
|
SHPC_PHYS_BUTTON);
|
||||||
|
pci_set_long(shpc->config + SHPC_SERR_INT, SHPC_INT_DIS |
|
||||||
|
SHPC_SERR_DIS |
|
||||||
|
SHPC_CMD_INT_DIS |
|
||||||
|
SHPC_ARB_SERR_DIS);
|
||||||
|
pci_set_byte(shpc->config + SHPC_PROG_IFC, SHPC_PROG_IFC_1_0);
|
||||||
|
pci_set_word(shpc->config + SHPC_SEC_BUS, SHPC_SEC_BUS_33);
|
||||||
|
for (i = 0; i < shpc->nslots; ++i) {
|
||||||
|
pci_set_byte(shpc->config + SHPC_SLOT_EVENT_SERR_INT_DIS(d, i),
|
||||||
|
SHPC_SLOT_EVENT_PRESENCE |
|
||||||
|
SHPC_SLOT_EVENT_ISOLATED_FAULT |
|
||||||
|
SHPC_SLOT_EVENT_BUTTON |
|
||||||
|
SHPC_SLOT_EVENT_MRL |
|
||||||
|
SHPC_SLOT_EVENT_CONNECTED_FAULT |
|
||||||
|
SHPC_SLOT_EVENT_MRL_SERR_DIS |
|
||||||
|
SHPC_SLOT_EVENT_CONNECTED_FAULT_SERR_DIS);
|
||||||
|
if (shpc->sec_bus->devices[PCI_DEVFN(SHPC_IDX_TO_PCI(i), 0)]) {
|
||||||
|
shpc_set_status(shpc, i, SHPC_STATE_ENABLED, SHPC_SLOT_STATE_MASK);
|
||||||
|
shpc_set_status(shpc, i, 0, SHPC_SLOT_STATUS_MRL_OPEN);
|
||||||
|
shpc_set_status(shpc, i, SHPC_SLOT_STATUS_PRSNT_7_5W,
|
||||||
|
SHPC_SLOT_STATUS_PRSNT_MASK);
|
||||||
|
shpc_set_status(shpc, i, SHPC_LED_ON, SHPC_SLOT_PWR_LED_MASK);
|
||||||
|
} else {
|
||||||
|
shpc_set_status(shpc, i, SHPC_STATE_DISABLED, SHPC_SLOT_STATE_MASK);
|
||||||
|
shpc_set_status(shpc, i, 1, SHPC_SLOT_STATUS_MRL_OPEN);
|
||||||
|
shpc_set_status(shpc, i, SHPC_SLOT_STATUS_PRSNT_EMPTY,
|
||||||
|
SHPC_SLOT_STATUS_PRSNT_MASK);
|
||||||
|
shpc_set_status(shpc, i, SHPC_LED_OFF, SHPC_SLOT_PWR_LED_MASK);
|
||||||
|
}
|
||||||
|
shpc_set_status(shpc, i, 0, SHPC_SLOT_STATUS_66);
|
||||||
|
}
|
||||||
|
shpc_set_sec_bus_speed(shpc, SHPC_SEC_BUS_33);
|
||||||
|
shpc->msi_requested = 0;
|
||||||
|
shpc_interrupt_update(d);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void shpc_invalid_command(SHPCDevice *shpc)
|
||||||
|
{
|
||||||
|
pci_word_test_and_set_mask(shpc->config + SHPC_CMD_STATUS,
|
||||||
|
SHPC_CMD_STATUS_INVALID_CMD);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void shpc_free_devices_in_slot(SHPCDevice *shpc, int slot)
|
||||||
|
{
|
||||||
|
int devfn;
|
||||||
|
int pci_slot = SHPC_IDX_TO_PCI(slot);
|
||||||
|
for (devfn = PCI_DEVFN(pci_slot, 0);
|
||||||
|
devfn <= PCI_DEVFN(pci_slot, PCI_FUNC_MAX - 1);
|
||||||
|
++devfn) {
|
||||||
|
PCIDevice *affected_dev = shpc->sec_bus->devices[devfn];
|
||||||
|
if (affected_dev) {
|
||||||
|
qdev_free(&affected_dev->qdev);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static void shpc_slot_command(SHPCDevice *shpc, uint8_t target,
|
||||||
|
uint8_t state, uint8_t power, uint8_t attn)
|
||||||
|
{
|
||||||
|
uint8_t current_state;
|
||||||
|
int slot = SHPC_LOGICAL_TO_IDX(target);
|
||||||
|
if (target < SHPC_CMD_TRGT_MIN || slot >= shpc->nslots) {
|
||||||
|
shpc_invalid_command(shpc);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
current_state = shpc_get_status(shpc, slot, SHPC_SLOT_STATE_MASK);
|
||||||
|
if (current_state == SHPC_STATE_ENABLED && state == SHPC_STATE_PWRONLY) {
|
||||||
|
shpc_invalid_command(shpc);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
switch (power) {
|
||||||
|
case SHPC_LED_NO:
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
/* TODO: send event to monitor */
|
||||||
|
shpc_set_status(shpc, slot, power, SHPC_SLOT_PWR_LED_MASK);
|
||||||
|
}
|
||||||
|
switch (attn) {
|
||||||
|
case SHPC_LED_NO:
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
/* TODO: send event to monitor */
|
||||||
|
shpc_set_status(shpc, slot, attn, SHPC_SLOT_ATTN_LED_MASK);
|
||||||
|
}
|
||||||
|
|
||||||
|
if ((current_state == SHPC_STATE_DISABLED && state == SHPC_STATE_PWRONLY) ||
|
||||||
|
(current_state == SHPC_STATE_DISABLED && state == SHPC_STATE_ENABLED)) {
|
||||||
|
shpc_set_status(shpc, slot, state, SHPC_SLOT_STATE_MASK);
|
||||||
|
} else if ((current_state == SHPC_STATE_ENABLED ||
|
||||||
|
current_state == SHPC_STATE_PWRONLY) &&
|
||||||
|
state == SHPC_STATE_DISABLED) {
|
||||||
|
shpc_set_status(shpc, slot, state, SHPC_SLOT_STATE_MASK);
|
||||||
|
power = shpc_get_status(shpc, slot, SHPC_SLOT_PWR_LED_MASK);
|
||||||
|
/* TODO: track what monitor requested. */
|
||||||
|
/* Look at LED to figure out whether it's ok to remove the device. */
|
||||||
|
if (power == SHPC_LED_OFF) {
|
||||||
|
shpc_free_devices_in_slot(shpc, slot);
|
||||||
|
shpc_set_status(shpc, slot, 1, SHPC_SLOT_STATUS_MRL_OPEN);
|
||||||
|
shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_EMPTY,
|
||||||
|
SHPC_SLOT_STATUS_PRSNT_MASK);
|
||||||
|
shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
|
||||||
|
SHPC_SLOT_EVENT_BUTTON |
|
||||||
|
SHPC_SLOT_EVENT_MRL |
|
||||||
|
SHPC_SLOT_EVENT_PRESENCE;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static void shpc_command(SHPCDevice *shpc)
|
||||||
|
{
|
||||||
|
uint8_t code = pci_get_byte(shpc->config + SHPC_CMD_CODE);
|
||||||
|
uint8_t speed;
|
||||||
|
uint8_t target;
|
||||||
|
uint8_t attn;
|
||||||
|
uint8_t power;
|
||||||
|
uint8_t state;
|
||||||
|
int i;
|
||||||
|
|
||||||
|
/* Clear status from the previous command. */
|
||||||
|
pci_word_test_and_clear_mask(shpc->config + SHPC_CMD_STATUS,
|
||||||
|
SHPC_CMD_STATUS_BUSY |
|
||||||
|
SHPC_CMD_STATUS_MRL_OPEN |
|
||||||
|
SHPC_CMD_STATUS_INVALID_CMD |
|
||||||
|
SHPC_CMD_STATUS_INVALID_MODE);
|
||||||
|
switch (code) {
|
||||||
|
case 0x00 ... 0x3f:
|
||||||
|
target = shpc->config[SHPC_CMD_TRGT] & SHPC_CMD_TRGT_MAX;
|
||||||
|
state = (code & SHPC_SLOT_STATE_MASK) >> SHPC_SLOT_STATE_SHIFT;
|
||||||
|
power = (code & SHPC_SLOT_PWR_LED_MASK) >> SHPC_SLOT_PWR_LED_SHIFT;
|
||||||
|
attn = (code & SHPC_SLOT_ATTN_LED_MASK) >> SHPC_SLOT_ATTN_LED_SHIFT;
|
||||||
|
shpc_slot_command(shpc, target, state, power, attn);
|
||||||
|
break;
|
||||||
|
case 0x40 ... 0x47:
|
||||||
|
speed = code & SHPC_SEC_BUS_MASK;
|
||||||
|
shpc_set_sec_bus_speed(shpc, speed);
|
||||||
|
break;
|
||||||
|
case 0x48:
|
||||||
|
/* Power only all slots */
|
||||||
|
/* first verify no slots are enabled */
|
||||||
|
for (i = 0; i < shpc->nslots; ++i) {
|
||||||
|
state = shpc_get_status(shpc, i, SHPC_SLOT_STATE_MASK);
|
||||||
|
if (state == SHPC_STATE_ENABLED) {
|
||||||
|
shpc_invalid_command(shpc);
|
||||||
|
goto done;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
for (i = 0; i < shpc->nslots; ++i) {
|
||||||
|
if (!(shpc_get_status(shpc, i, SHPC_SLOT_STATUS_MRL_OPEN))) {
|
||||||
|
shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN,
|
||||||
|
SHPC_STATE_PWRONLY, SHPC_LED_ON, SHPC_LED_NO);
|
||||||
|
} else {
|
||||||
|
shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN,
|
||||||
|
SHPC_STATE_NO, SHPC_LED_OFF, SHPC_LED_NO);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
case 0x49:
|
||||||
|
/* Enable all slots */
|
||||||
|
/* TODO: Spec says this shall fail if some are already enabled.
|
||||||
|
* This doesn't make sense - why not? a spec bug? */
|
||||||
|
for (i = 0; i < shpc->nslots; ++i) {
|
||||||
|
state = shpc_get_status(shpc, i, SHPC_SLOT_STATE_MASK);
|
||||||
|
if (state == SHPC_STATE_ENABLED) {
|
||||||
|
shpc_invalid_command(shpc);
|
||||||
|
goto done;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
for (i = 0; i < shpc->nslots; ++i) {
|
||||||
|
if (!(shpc_get_status(shpc, i, SHPC_SLOT_STATUS_MRL_OPEN))) {
|
||||||
|
shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN,
|
||||||
|
SHPC_STATE_ENABLED, SHPC_LED_ON, SHPC_LED_NO);
|
||||||
|
} else {
|
||||||
|
shpc_slot_command(shpc, i + SHPC_CMD_TRGT_MIN,
|
||||||
|
SHPC_STATE_NO, SHPC_LED_OFF, SHPC_LED_NO);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
shpc_invalid_command(shpc);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
done:
|
||||||
|
pci_long_test_and_set_mask(shpc->config + SHPC_SERR_INT, SHPC_CMD_DETECTED);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void shpc_write(PCIDevice *d, unsigned addr, uint64_t val, int l)
|
||||||
|
{
|
||||||
|
SHPCDevice *shpc = d->shpc;
|
||||||
|
int i;
|
||||||
|
if (addr >= SHPC_SIZEOF(d)) {
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
l = MIN(l, SHPC_SIZEOF(d) - addr);
|
||||||
|
|
||||||
|
/* TODO: code duplicated from pci.c */
|
||||||
|
for (i = 0; i < l; val >>= 8, ++i) {
|
||||||
|
unsigned a = addr + i;
|
||||||
|
uint8_t wmask = shpc->wmask[a];
|
||||||
|
uint8_t w1cmask = shpc->w1cmask[a];
|
||||||
|
assert(!(wmask & w1cmask));
|
||||||
|
shpc->config[a] = (shpc->config[a] & ~wmask) | (val & wmask);
|
||||||
|
shpc->config[a] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
|
||||||
|
}
|
||||||
|
if (ranges_overlap(addr, l, SHPC_CMD_CODE, 2)) {
|
||||||
|
shpc_command(shpc);
|
||||||
|
}
|
||||||
|
shpc_interrupt_update(d);
|
||||||
|
}
|
||||||
|
|
||||||
|
static uint64_t shpc_read(PCIDevice *d, unsigned addr, int l)
|
||||||
|
{
|
||||||
|
uint64_t val = 0x0;
|
||||||
|
if (addr >= SHPC_SIZEOF(d)) {
|
||||||
|
return val;
|
||||||
|
}
|
||||||
|
l = MIN(l, SHPC_SIZEOF(d) - addr);
|
||||||
|
memcpy(&val, d->shpc->config + addr, l);
|
||||||
|
return val;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* SHPC Bridge Capability */
|
||||||
|
#define SHPC_CAP_LENGTH 0x08
|
||||||
|
#define SHPC_CAP_DWORD_SELECT 0x2 /* 1 byte */
|
||||||
|
#define SHPC_CAP_CxP 0x3 /* 1 byte: CSP, CIP */
|
||||||
|
#define SHPC_CAP_DWORD_DATA 0x4 /* 4 bytes */
|
||||||
|
#define SHPC_CAP_CSP_MASK 0x4
|
||||||
|
#define SHPC_CAP_CIP_MASK 0x8
|
||||||
|
|
||||||
|
static uint8_t shpc_cap_dword(PCIDevice *d)
|
||||||
|
{
|
||||||
|
return pci_get_byte(d->config + d->shpc->cap + SHPC_CAP_DWORD_SELECT);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Update dword data capability register */
|
||||||
|
static void shpc_cap_update_dword(PCIDevice *d)
|
||||||
|
{
|
||||||
|
unsigned data;
|
||||||
|
data = shpc_read(d, shpc_cap_dword(d) * 4, 4);
|
||||||
|
pci_set_long(d->config + d->shpc->cap + SHPC_CAP_DWORD_DATA, data);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Add SHPC capability to the config space for the device. */
|
||||||
|
static int shpc_cap_add_config(PCIDevice *d)
|
||||||
|
{
|
||||||
|
uint8_t *config;
|
||||||
|
int config_offset;
|
||||||
|
config_offset = pci_add_capability(d, PCI_CAP_ID_SHPC,
|
||||||
|
0, SHPC_CAP_LENGTH);
|
||||||
|
if (config_offset < 0) {
|
||||||
|
return config_offset;
|
||||||
|
}
|
||||||
|
config = d->config + config_offset;
|
||||||
|
|
||||||
|
pci_set_byte(config + SHPC_CAP_DWORD_SELECT, 0);
|
||||||
|
pci_set_byte(config + SHPC_CAP_CxP, 0);
|
||||||
|
pci_set_long(config + SHPC_CAP_DWORD_DATA, 0);
|
||||||
|
d->shpc->cap = config_offset;
|
||||||
|
/* Make dword select and data writeable. */
|
||||||
|
pci_set_byte(d->wmask + config_offset + SHPC_CAP_DWORD_SELECT, 0xff);
|
||||||
|
pci_set_long(d->wmask + config_offset + SHPC_CAP_DWORD_DATA, 0xffffffff);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static uint64_t shpc_mmio_read(void *opaque, target_phys_addr_t addr,
|
||||||
|
unsigned size)
|
||||||
|
{
|
||||||
|
return shpc_read(opaque, addr, size);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void shpc_mmio_write(void *opaque, target_phys_addr_t addr,
|
||||||
|
uint64_t val, unsigned size)
|
||||||
|
{
|
||||||
|
shpc_write(opaque, addr, val, size);
|
||||||
|
}
|
||||||
|
|
||||||
|
static const MemoryRegionOps shpc_mmio_ops = {
|
||||||
|
.read = shpc_mmio_read,
|
||||||
|
.write = shpc_mmio_write,
|
||||||
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
||||||
|
.valid = {
|
||||||
|
/* SHPC ECN requires dword accesses, but the original 1.0 spec doesn't.
|
||||||
|
* It's easier to suppport all sizes than worry about it. */
|
||||||
|
.min_access_size = 1,
|
||||||
|
.max_access_size = 4,
|
||||||
|
},
|
||||||
|
};
|
||||||
|
|
||||||
|
static int shpc_device_hotplug(DeviceState *qdev, PCIDevice *affected_dev,
|
||||||
|
PCIHotplugState hotplug_state)
|
||||||
|
{
|
||||||
|
int pci_slot = PCI_SLOT(affected_dev->devfn);
|
||||||
|
uint8_t state;
|
||||||
|
uint8_t led;
|
||||||
|
PCIDevice *d = DO_UPCAST(PCIDevice, qdev, qdev);
|
||||||
|
SHPCDevice *shpc = d->shpc;
|
||||||
|
int slot = SHPC_PCI_TO_IDX(pci_slot);
|
||||||
|
if (pci_slot < SHPC_IDX_TO_PCI(0) || slot >= shpc->nslots) {
|
||||||
|
error_report("Unsupported PCI slot %d for standard hotplug "
|
||||||
|
"controller. Valid slots are between %d and %d.",
|
||||||
|
pci_slot, SHPC_IDX_TO_PCI(0),
|
||||||
|
SHPC_IDX_TO_PCI(shpc->nslots) - 1);
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
/* Don't send event when device is enabled during qemu machine creation:
|
||||||
|
* it is present on boot, no hotplug event is necessary. We do send an
|
||||||
|
* event when the device is disabled later. */
|
||||||
|
if (hotplug_state == PCI_COLDPLUG_ENABLED) {
|
||||||
|
shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_MRL_OPEN);
|
||||||
|
shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_7_5W,
|
||||||
|
SHPC_SLOT_STATUS_PRSNT_MASK);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
if (hotplug_state == PCI_HOTPLUG_DISABLED) {
|
||||||
|
shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |= SHPC_SLOT_EVENT_BUTTON;
|
||||||
|
state = shpc_get_status(shpc, slot, SHPC_SLOT_STATE_MASK);
|
||||||
|
led = shpc_get_status(shpc, slot, SHPC_SLOT_PWR_LED_MASK);
|
||||||
|
if (state == SHPC_STATE_DISABLED && led == SHPC_LED_OFF) {
|
||||||
|
shpc_free_devices_in_slot(shpc, slot);
|
||||||
|
shpc_set_status(shpc, slot, 1, SHPC_SLOT_STATUS_MRL_OPEN);
|
||||||
|
shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_EMPTY,
|
||||||
|
SHPC_SLOT_STATUS_PRSNT_MASK);
|
||||||
|
shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
|
||||||
|
SHPC_SLOT_EVENT_MRL |
|
||||||
|
SHPC_SLOT_EVENT_PRESENCE;
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
/* This could be a cancellation of the previous removal.
|
||||||
|
* We check MRL state to figure out. */
|
||||||
|
if (shpc_get_status(shpc, slot, SHPC_SLOT_STATUS_MRL_OPEN)) {
|
||||||
|
shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_MRL_OPEN);
|
||||||
|
shpc_set_status(shpc, slot, SHPC_SLOT_STATUS_PRSNT_7_5W,
|
||||||
|
SHPC_SLOT_STATUS_PRSNT_MASK);
|
||||||
|
shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
|
||||||
|
SHPC_SLOT_EVENT_BUTTON |
|
||||||
|
SHPC_SLOT_EVENT_MRL |
|
||||||
|
SHPC_SLOT_EVENT_PRESENCE;
|
||||||
|
} else {
|
||||||
|
/* Press attention button to cancel removal */
|
||||||
|
shpc->config[SHPC_SLOT_EVENT_LATCH(slot)] |=
|
||||||
|
SHPC_SLOT_EVENT_BUTTON;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
shpc_set_status(shpc, slot, 0, SHPC_SLOT_STATUS_66);
|
||||||
|
shpc_interrupt_update(d);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Initialize the SHPC structure in bridge's BAR. */
|
||||||
|
int shpc_init(PCIDevice *d, PCIBus *sec_bus, MemoryRegion *bar, unsigned offset)
|
||||||
|
{
|
||||||
|
int i, ret;
|
||||||
|
int nslots = SHPC_MAX_SLOTS; /* TODO: qdev property? */
|
||||||
|
SHPCDevice *shpc = d->shpc = g_malloc0(sizeof(*d->shpc));
|
||||||
|
shpc->sec_bus = sec_bus;
|
||||||
|
ret = shpc_cap_add_config(d);
|
||||||
|
if (ret) {
|
||||||
|
g_free(d->shpc);
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
if (nslots < SHPC_MIN_SLOTS) {
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
if (nslots > SHPC_MAX_SLOTS ||
|
||||||
|
SHPC_IDX_TO_PCI(nslots) > PCI_SLOT_MAX) {
|
||||||
|
/* TODO: report an error mesage that makes sense. */
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
shpc->nslots = nslots;
|
||||||
|
shpc->config = g_malloc0(SHPC_SIZEOF(d));
|
||||||
|
shpc->cmask = g_malloc0(SHPC_SIZEOF(d));
|
||||||
|
shpc->wmask = g_malloc0(SHPC_SIZEOF(d));
|
||||||
|
shpc->w1cmask = g_malloc0(SHPC_SIZEOF(d));
|
||||||
|
|
||||||
|
shpc_reset(d);
|
||||||
|
|
||||||
|
pci_set_long(shpc->config + SHPC_BASE_OFFSET, offset);
|
||||||
|
|
||||||
|
pci_set_byte(shpc->wmask + SHPC_CMD_CODE, 0xff);
|
||||||
|
pci_set_byte(shpc->wmask + SHPC_CMD_TRGT, SHPC_CMD_TRGT_MAX);
|
||||||
|
pci_set_byte(shpc->wmask + SHPC_CMD_TRGT, SHPC_CMD_TRGT_MAX);
|
||||||
|
pci_set_long(shpc->wmask + SHPC_SERR_INT,
|
||||||
|
SHPC_INT_DIS |
|
||||||
|
SHPC_SERR_DIS |
|
||||||
|
SHPC_CMD_INT_DIS |
|
||||||
|
SHPC_ARB_SERR_DIS);
|
||||||
|
pci_set_long(shpc->w1cmask + SHPC_SERR_INT,
|
||||||
|
SHPC_CMD_DETECTED |
|
||||||
|
SHPC_ARB_DETECTED);
|
||||||
|
for (i = 0; i < nslots; ++i) {
|
||||||
|
pci_set_byte(shpc->wmask +
|
||||||
|
SHPC_SLOT_EVENT_SERR_INT_DIS(d, i),
|
||||||
|
SHPC_SLOT_EVENT_PRESENCE |
|
||||||
|
SHPC_SLOT_EVENT_ISOLATED_FAULT |
|
||||||
|
SHPC_SLOT_EVENT_BUTTON |
|
||||||
|
SHPC_SLOT_EVENT_MRL |
|
||||||
|
SHPC_SLOT_EVENT_CONNECTED_FAULT |
|
||||||
|
SHPC_SLOT_EVENT_MRL_SERR_DIS |
|
||||||
|
SHPC_SLOT_EVENT_CONNECTED_FAULT_SERR_DIS);
|
||||||
|
pci_set_byte(shpc->w1cmask +
|
||||||
|
SHPC_SLOT_EVENT_LATCH(i),
|
||||||
|
SHPC_SLOT_EVENT_PRESENCE |
|
||||||
|
SHPC_SLOT_EVENT_ISOLATED_FAULT |
|
||||||
|
SHPC_SLOT_EVENT_BUTTON |
|
||||||
|
SHPC_SLOT_EVENT_MRL |
|
||||||
|
SHPC_SLOT_EVENT_CONNECTED_FAULT);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* TODO: init cmask */
|
||||||
|
memory_region_init_io(&shpc->mmio, &shpc_mmio_ops, d, "shpc-mmio",
|
||||||
|
SHPC_SIZEOF(d));
|
||||||
|
shpc_cap_update_dword(d);
|
||||||
|
memory_region_add_subregion(bar, offset, &shpc->mmio);
|
||||||
|
pci_bus_hotplug(sec_bus, shpc_device_hotplug, &d->qdev);
|
||||||
|
|
||||||
|
d->cap_present |= QEMU_PCI_CAP_SHPC;
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
int shpc_bar_size(PCIDevice *d)
|
||||||
|
{
|
||||||
|
return roundup_pow_of_two(SHPC_SLOT_REG(SHPC_MAX_SLOTS));
|
||||||
|
}
|
||||||
|
|
||||||
|
void shpc_cleanup(PCIDevice *d, MemoryRegion *bar)
|
||||||
|
{
|
||||||
|
SHPCDevice *shpc = d->shpc;
|
||||||
|
d->cap_present &= ~QEMU_PCI_CAP_SHPC;
|
||||||
|
memory_region_del_subregion(bar, &shpc->mmio);
|
||||||
|
/* TODO: cleanup config space changes? */
|
||||||
|
g_free(shpc->config);
|
||||||
|
g_free(shpc->cmask);
|
||||||
|
g_free(shpc->wmask);
|
||||||
|
g_free(shpc->w1cmask);
|
||||||
|
memory_region_destroy(&shpc->mmio);
|
||||||
|
g_free(shpc);
|
||||||
|
}
|
||||||
|
|
||||||
|
void shpc_cap_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
|
||||||
|
{
|
||||||
|
if (!ranges_overlap(addr, l, d->shpc->cap, SHPC_CAP_LENGTH)) {
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
if (ranges_overlap(addr, l, d->shpc->cap + SHPC_CAP_DWORD_DATA, 4)) {
|
||||||
|
unsigned dword_data;
|
||||||
|
dword_data = pci_get_long(d->shpc->config + d->shpc->cap
|
||||||
|
+ SHPC_CAP_DWORD_DATA);
|
||||||
|
shpc_write(d, shpc_cap_dword(d) * 4, dword_data, 4);
|
||||||
|
}
|
||||||
|
/* Update cap dword data in case guest is going to read it. */
|
||||||
|
shpc_cap_update_dword(d);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void shpc_save(QEMUFile *f, void *pv, size_t size)
|
||||||
|
{
|
||||||
|
PCIDevice *d = container_of(pv, PCIDevice, shpc);
|
||||||
|
qemu_put_buffer(f, d->shpc->config, SHPC_SIZEOF(d));
|
||||||
|
}
|
||||||
|
|
||||||
|
static int shpc_load(QEMUFile *f, void *pv, size_t size)
|
||||||
|
{
|
||||||
|
PCIDevice *d = container_of(pv, PCIDevice, shpc);
|
||||||
|
int ret = qemu_get_buffer(f, d->shpc->config, SHPC_SIZEOF(d));
|
||||||
|
if (ret != SHPC_SIZEOF(d)) {
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
/* Make sure we don't lose notifications. An extra interrupt is harmless. */
|
||||||
|
d->shpc->msi_requested = 0;
|
||||||
|
shpc_interrupt_update(d);
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
VMStateInfo shpc_vmstate_info = {
|
||||||
|
.name = "shpc",
|
||||||
|
.get = shpc_load,
|
||||||
|
.put = shpc_save,
|
||||||
|
};
|
||||||
48
hw/shpc.h
Normal file
48
hw/shpc.h
Normal file
@ -0,0 +1,48 @@
|
|||||||
|
#ifndef SHPC_H
|
||||||
|
#define SHPC_H
|
||||||
|
|
||||||
|
#include "qemu-common.h"
|
||||||
|
#include "memory.h"
|
||||||
|
#include "vmstate.h"
|
||||||
|
|
||||||
|
struct SHPCDevice {
|
||||||
|
/* Capability offset in device's config space */
|
||||||
|
int cap;
|
||||||
|
|
||||||
|
/* # of hot-pluggable slots */
|
||||||
|
int nslots;
|
||||||
|
|
||||||
|
/* SHPC WRS: working register set */
|
||||||
|
uint8_t *config;
|
||||||
|
|
||||||
|
/* Used to enable checks on load. Note that writable bits are
|
||||||
|
* never checked even if set in cmask. */
|
||||||
|
uint8_t *cmask;
|
||||||
|
|
||||||
|
/* Used to implement R/W bytes */
|
||||||
|
uint8_t *wmask;
|
||||||
|
|
||||||
|
/* Used to implement RW1C(Write 1 to Clear) bytes */
|
||||||
|
uint8_t *w1cmask;
|
||||||
|
|
||||||
|
/* MMIO for the SHPC BAR */
|
||||||
|
MemoryRegion mmio;
|
||||||
|
|
||||||
|
/* Bus controlled by this SHPC */
|
||||||
|
PCIBus *sec_bus;
|
||||||
|
|
||||||
|
/* MSI already requested for this event */
|
||||||
|
int msi_requested;
|
||||||
|
};
|
||||||
|
|
||||||
|
void shpc_reset(PCIDevice *d);
|
||||||
|
int shpc_bar_size(PCIDevice *dev);
|
||||||
|
int shpc_init(PCIDevice *dev, PCIBus *sec_bus, MemoryRegion *bar, unsigned off);
|
||||||
|
void shpc_cleanup(PCIDevice *dev, MemoryRegion *bar);
|
||||||
|
void shpc_cap_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int len);
|
||||||
|
|
||||||
|
extern VMStateInfo shpc_vmstate_info;
|
||||||
|
#define SHPC_VMSTATE(_field, _type) \
|
||||||
|
VMSTATE_BUFFER_UNSAFE_INFO(_field, _type, 0, shpc_vmstate_info, 0)
|
||||||
|
|
||||||
|
#endif
|
||||||
44
hw/slotid_cap.c
Normal file
44
hw/slotid_cap.c
Normal file
@ -0,0 +1,44 @@
|
|||||||
|
#include "slotid_cap.h"
|
||||||
|
#include "pci.h"
|
||||||
|
|
||||||
|
#define SLOTID_CAP_LENGTH 4
|
||||||
|
#define SLOTID_NSLOTS_SHIFT (ffs(PCI_SID_ESR_NSLOTS) - 1)
|
||||||
|
|
||||||
|
int slotid_cap_init(PCIDevice *d, int nslots,
|
||||||
|
uint8_t chassis,
|
||||||
|
unsigned offset)
|
||||||
|
{
|
||||||
|
int cap;
|
||||||
|
if (!chassis) {
|
||||||
|
error_report("Bridge chassis not specified. Each bridge is required "
|
||||||
|
"to be assigned a unique chassis id > 0.");
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
if (nslots < 0 || nslots > (PCI_SID_ESR_NSLOTS >> SLOTID_NSLOTS_SHIFT)) {
|
||||||
|
/* TODO: error report? */
|
||||||
|
return -EINVAL;
|
||||||
|
}
|
||||||
|
|
||||||
|
cap = pci_add_capability(d, PCI_CAP_ID_SLOTID, offset, SLOTID_CAP_LENGTH);
|
||||||
|
if (cap < 0) {
|
||||||
|
return cap;
|
||||||
|
}
|
||||||
|
/* We make each chassis unique, this way each bridge is First in Chassis */
|
||||||
|
d->config[cap + PCI_SID_ESR] = PCI_SID_ESR_FIC |
|
||||||
|
(nslots << SLOTID_NSLOTS_SHIFT);
|
||||||
|
d->cmask[cap + PCI_SID_ESR] = 0xff;
|
||||||
|
d->config[cap + PCI_SID_CHASSIS_NR] = chassis;
|
||||||
|
/* Note: Chassis number register is non-volatile,
|
||||||
|
so we don't reset it. */
|
||||||
|
/* TODO: store in eeprom? */
|
||||||
|
d->wmask[cap + PCI_SID_CHASSIS_NR] = 0xff;
|
||||||
|
|
||||||
|
d->cap_present |= QEMU_PCI_CAP_SLOTID;
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
void slotid_cap_cleanup(PCIDevice *d)
|
||||||
|
{
|
||||||
|
/* TODO: cleanup config space? */
|
||||||
|
d->cap_present &= ~QEMU_PCI_CAP_SLOTID;
|
||||||
|
}
|
||||||
11
hw/slotid_cap.h
Normal file
11
hw/slotid_cap.h
Normal file
@ -0,0 +1,11 @@
|
|||||||
|
#ifndef PCI_SLOTID_CAP_H
|
||||||
|
#define PCI_SLOTID_CAP_H
|
||||||
|
|
||||||
|
#include "qemu-common.h"
|
||||||
|
|
||||||
|
int slotid_cap_init(PCIDevice *dev, int nslots,
|
||||||
|
uint8_t chassis,
|
||||||
|
unsigned offset);
|
||||||
|
void slotid_cap_cleanup(PCIDevice *dev);
|
||||||
|
|
||||||
|
#endif
|
||||||
@ -79,6 +79,7 @@ struct virtio_net_config
|
|||||||
struct virtio_net_hdr
|
struct virtio_net_hdr
|
||||||
{
|
{
|
||||||
#define VIRTIO_NET_HDR_F_NEEDS_CSUM 1 // Use csum_start, csum_offset
|
#define VIRTIO_NET_HDR_F_NEEDS_CSUM 1 // Use csum_start, csum_offset
|
||||||
|
#define VIRTIO_NET_HDR_F_DATA_VALID 2 // Csum is valid
|
||||||
uint8_t flags;
|
uint8_t flags;
|
||||||
#define VIRTIO_NET_HDR_GSO_NONE 0 // Not a GSO frame
|
#define VIRTIO_NET_HDR_GSO_NONE 0 // Not a GSO frame
|
||||||
#define VIRTIO_NET_HDR_GSO_TCPV4 1 // GSO frame, IPv4 TCP (TSO)
|
#define VIRTIO_NET_HDR_GSO_TCPV4 1 // GSO frame, IPv4 TCP (TSO)
|
||||||
|
|||||||
23
net.c
23
net.c
@ -1475,3 +1475,26 @@ int net_client_parse(QemuOptsList *opts_list, const char *optarg)
|
|||||||
default_net = 0;
|
default_net = 0;
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/* From FreeBSD */
|
||||||
|
/* XXX: optimize */
|
||||||
|
unsigned compute_mcast_idx(const uint8_t *ep)
|
||||||
|
{
|
||||||
|
uint32_t crc;
|
||||||
|
int carry, i, j;
|
||||||
|
uint8_t b;
|
||||||
|
|
||||||
|
crc = 0xffffffff;
|
||||||
|
for (i = 0; i < 6; i++) {
|
||||||
|
b = *ep++;
|
||||||
|
for (j = 0; j < 8; j++) {
|
||||||
|
carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
|
||||||
|
crc <<= 1;
|
||||||
|
b >>= 1;
|
||||||
|
if (carry) {
|
||||||
|
crc = ((crc ^ POLYNOMIAL) | carry);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return crc >> 26;
|
||||||
|
}
|
||||||
|
|||||||
3
net.h
3
net.h
@ -182,6 +182,9 @@ void qdev_set_nic_properties(DeviceState *dev, NICInfo *nd);
|
|||||||
|
|
||||||
int net_handle_fd_param(Monitor *mon, const char *param);
|
int net_handle_fd_param(Monitor *mon, const char *param);
|
||||||
|
|
||||||
|
#define POLYNOMIAL 0x04c11db6
|
||||||
|
unsigned compute_mcast_idx(const uint8_t *ep);
|
||||||
|
|
||||||
#define vmstate_offset_macaddr(_state, _field) \
|
#define vmstate_offset_macaddr(_state, _field) \
|
||||||
vmstate_offset_array(_state, _field.a, uint8_t, \
|
vmstate_offset_array(_state, _field.a, uint8_t, \
|
||||||
sizeof(typeof_field(_state, _field)))
|
sizeof(typeof_field(_state, _field)))
|
||||||
|
|||||||
@ -258,6 +258,7 @@ typedef struct SSIBus SSIBus;
|
|||||||
typedef struct EventNotifier EventNotifier;
|
typedef struct EventNotifier EventNotifier;
|
||||||
typedef struct VirtIODevice VirtIODevice;
|
typedef struct VirtIODevice VirtIODevice;
|
||||||
typedef struct QEMUSGList QEMUSGList;
|
typedef struct QEMUSGList QEMUSGList;
|
||||||
|
typedef struct SHPCDevice SHPCDevice;
|
||||||
|
|
||||||
typedef uint64_t pcibus_t;
|
typedef uint64_t pcibus_t;
|
||||||
|
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user