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target/arm: Remove redundant shift tests

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The immediate shift generator functions already test for,
and eliminate, the case of a shift by zero.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190808202616.13782-4-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2019-08-08 13:26:12 -07:00 committed by Peter Maydell
parent d1f8755fc9
commit 464eaa9571
1 changed files with 7 additions and 12 deletions
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9
target/arm/translate.c
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@ -8811,7 +8811,6 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
shift = (insn >> 10) & 3; shift = (insn >> 10) & 3;
/* ??? In many cases it's not necessary to do a /* ??? In many cases it's not necessary to do a
rotate, a shift is sufficient. */ rotate, a shift is sufficient. */
if (shift != 0)
tcg_gen_rotri_i32(tmp, tmp, shift * 8); tcg_gen_rotri_i32(tmp, tmp, shift * 8);
op1 = (insn >> 20) & 7; op1 = (insn >> 20) & 7;
switch (op1) { switch (op1) {
@ -9889,7 +9888,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
shift = (insn >> 4) & 3; shift = (insn >> 4) & 3;
/* ??? In many cases it's not necessary to do a /* ??? In many cases it's not necessary to do a
rotate, a shift is sufficient. */ rotate, a shift is sufficient. */
if (shift != 0)
tcg_gen_rotri_i32(tmp, tmp, shift * 8); tcg_gen_rotri_i32(tmp, tmp, shift * 8);
op = (insn >> 20) & 7; op = (insn >> 20) & 7;
switch (op) { switch (op) {
@ -10617,10 +10615,9 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
case 7: case 7:
goto illegal_op; goto illegal_op;
default: /* Saturate. */ default: /* Saturate. */
if (shift) { if (op & 1) {
if (op & 1)
tcg_gen_sari_i32(tmp, tmp, shift); tcg_gen_sari_i32(tmp, tmp, shift);
else } else {
tcg_gen_shli_i32(tmp, tmp, shift); tcg_gen_shli_i32(tmp, tmp, shift);
} }
tmp2 = tcg_const_i32(imm); tmp2 = tcg_const_i32(imm);
@ -10812,9 +10809,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
goto illegal_op; goto illegal_op;
} }
tmp = load_reg(s, rm); tmp = load_reg(s, rm);
if (shift) {
tcg_gen_shli_i32(tmp, tmp, shift); tcg_gen_shli_i32(tmp, tmp, shift);
}
tcg_gen_add_i32(addr, addr, tmp); tcg_gen_add_i32(addr, addr, tmp);
tcg_temp_free_i32(tmp); tcg_temp_free_i32(tmp);
break; break;