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Revert "target/arm: Use unallocated_encoding for aarch32"

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This reverts commit 3cb36637157088892e9e33ddb1034bffd1251d3b.

Despite the fact that the text for the call to gen_exception_insn
is identical for aarch64 and aarch32, the implementation inside
gen_exception_insn is totally different.

This fixes exceptions raised from aarch64.

Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Message-id: 20190826151536.6771-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2019-08-26 08:15:35 -07:00 committed by Peter Maydell
parent fec105c2ab
commit 429a71d67e
5 changed files with 21 additions and 15 deletions
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7
target/arm/translate-a64.c
View File

@ -338,6 +338,13 @@ static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest)
} }
} }
void unallocated_encoding(DisasContext *s)
{
/* Unallocated and reserved encodings are uncategorized */
gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
default_exception_el(s));
}
static void init_tmp_a64_array(DisasContext *s) static void init_tmp_a64_array(DisasContext *s)
{ {
#ifdef CONFIG_DEBUG_TCG #ifdef CONFIG_DEBUG_TCG

2
target/arm/translate-a64.h
View File

@ -18,6 +18,8 @@
#ifndef TARGET_ARM_TRANSLATE_A64_H #ifndef TARGET_ARM_TRANSLATE_A64_H
#define TARGET_ARM_TRANSLATE_A64_H #define TARGET_ARM_TRANSLATE_A64_H
void unallocated_encoding(DisasContext *s);
#define unsupported_encoding(s, insn) \ #define unsupported_encoding(s, insn) \
do { \ do { \
qemu_log_mask(LOG_UNIMP, \ qemu_log_mask(LOG_UNIMP, \

3
target/arm/translate-vfp.inc.c
View File

@ -108,7 +108,8 @@ static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled)
if (!s->vfp_enabled && !ignore_vfp_enabled) { if (!s->vfp_enabled && !ignore_vfp_enabled) {
assert(!arm_dc_feature(s, ARM_FEATURE_M)); assert(!arm_dc_feature(s, ARM_FEATURE_M));
unallocated_encoding(s); gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
default_exception_el(s));
return false; return false;
} }

22
target/arm/translate.c
View File

@ -1231,13 +1231,6 @@ static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn)
s->base.is_jmp = DISAS_NORETURN; s->base.is_jmp = DISAS_NORETURN;
} }
void unallocated_encoding(DisasContext *s)
{
/* Unallocated and reserved encodings are uncategorized */
gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
default_exception_el(s));
}
/* Force a TB lookup after an instruction that changes the CPU state. */ /* Force a TB lookup after an instruction that changes the CPU state. */
static inline void gen_lookup_tb(DisasContext *s) static inline void gen_lookup_tb(DisasContext *s)
{ {
@ -1268,7 +1261,8 @@ static inline void gen_hlt(DisasContext *s, int imm)
return; return;
} }
unallocated_encoding(s); gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
default_exception_el(s));
} }
static inline void gen_add_data_offset(DisasContext *s, unsigned int insn, static inline void gen_add_data_offset(DisasContext *s, unsigned int insn,
@ -7580,7 +7574,8 @@ static void gen_srs(DisasContext *s,
} }
if (undef) { if (undef) {
unallocated_encoding(s); gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
default_exception_el(s));
return; return;
} }
@ -9201,7 +9196,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
break; break;
default: default:
illegal_op: illegal_op:
unallocated_encoding(s); gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
default_exception_el(s));
break; break;
} }
} }
@ -10886,7 +10882,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
} }
return; return;
illegal_op: illegal_op:
unallocated_encoding(s); gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
default_exception_el(s));
} }
static void disas_thumb_insn(DisasContext *s, uint32_t insn) static void disas_thumb_insn(DisasContext *s, uint32_t insn)
@ -11709,7 +11706,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
return; return;
illegal_op: illegal_op:
undef: undef:
unallocated_encoding(s); gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
default_exception_el(s));
} }
static bool insn_crosses_page(CPUARMState *env, DisasContext *s) static bool insn_crosses_page(CPUARMState *env, DisasContext *s)

2
target/arm/translate.h
View File

@ -99,8 +99,6 @@ typedef struct DisasCompare {
bool value_global; bool value_global;
} DisasCompare; } DisasCompare;
void unallocated_encoding(DisasContext *s);
/* Share the TCG temporaries common between 32 and 64 bit modes. */ /* Share the TCG temporaries common between 32 and 64 bit modes. */
extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF; extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF;
extern TCGv_i64 cpu_exclusive_addr; extern TCGv_i64 cpu_exclusive_addr;