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target/arm: Add predicate registers for SVE

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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20180123035349.24538-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2018-01-22 19:53:46 -08:00 committed by Peter Maydell
parent c39c2b9043
commit 3c7d30866f
1 changed files with 12 additions and 0 deletions
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12
target/arm/cpu.h
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@ -188,6 +188,13 @@ typedef struct ARMVectorReg {
uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16);
} ARMVectorReg; } ARMVectorReg;
/* In AArch32 mode, predicate registers do not exist at all. */
#ifdef TARGET_AARCH64
typedef struct ARMPredicateReg {
uint64_t p[2 * ARM_MAX_VQ / 8] QEMU_ALIGNED(16);
} ARMPredicateReg;
#endif
typedef struct CPUARMState { typedef struct CPUARMState {
/* Regs for current mode. */ /* Regs for current mode. */
@ -515,6 +522,11 @@ typedef struct CPUARMState {
struct { struct {
ARMVectorReg zregs[32]; ARMVectorReg zregs[32];
#ifdef TARGET_AARCH64
/* Store FFR as pregs[16] to make it easier to treat as any other. */
ARMPredicateReg pregs[17];
#endif
uint32_t xregs[16]; uint32_t xregs[16];
/* We store these fpcsr fields separately for convenience. */ /* We store these fpcsr fields separately for convenience. */
int vec_len; int vec_len;