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target-ppc: fix evmergelo and evmergelohi

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For 32-bit PPC targets, we translated:

evmergelo rX, rX, rY

as:

rX-lo = rY-lo
rX-hi = rX-lo

which is wrong, because we should be transferring rX-lo first.  This
problem is fixed by swapping the order in which we write the parts of
rX.

Similarly, we translated:

evmergelohi rX, rX, rY

as:

rX-lo = rY-hi
rX-hi = rX-lo

In this case, we can't swap the assignment statements, because that
would just cause problems for:

evmergelohi rX, rY, rX

Instead, we detect the first case and save rX-lo in a temporary
variable:

tmp = rX-lo
rX-lo = rY-hi
rX-hi = tmp

These problems don't occur on PPC64 targets because we don't split the
SPE registers into hi/lo parts for such targets.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Nathan Froyd 2009-06-04 13:46:41 -07:00 committed by Aurelien Jarno
parent f55e9d9a40
commit 33890b3e0d
1 changed files with 11 additions and 3 deletions
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14
target-ppc/translate.c
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@ -6908,8 +6908,8 @@ static always_inline void gen_evmergelo (DisasContext *ctx)
tcg_temp_free(t0); tcg_temp_free(t0);
tcg_temp_free(t1); tcg_temp_free(t1);
#else #else
tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
#endif #endif
} }
static always_inline void gen_evmergehilo (DisasContext *ctx) static always_inline void gen_evmergehilo (DisasContext *ctx)
@ -6946,8 +6946,16 @@ static always_inline void gen_evmergelohi (DisasContext *ctx)
tcg_temp_free(t0); tcg_temp_free(t0);
tcg_temp_free(t1); tcg_temp_free(t1);
#else #else
tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]); if (rD(ctx->opcode) == rA(ctx->opcode)) {
tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); TCGv_i32 tmp = tcg_temp_new_i32();
tcg_gen_mov_i32(tmp, cpu_gpr[rA(ctx->opcode)]);
tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], tmp);
tcg_temp_free_i32(tmp);
} else {
tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
}
#endif #endif
} }
static always_inline void gen_evsplati (DisasContext *ctx) static always_inline void gen_evsplati (DisasContext *ctx)