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target-arm: Add SPSR entries for EL2/HYP and EL3/MON

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Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 1400980132-25949-12-git-send-email-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Edgar E. Iglesias 2014-05-27 17:09:52 +01:00 committed by Peter Maydell
parent 1b1742386c
commit 28c9457df0
4 changed files with 12 additions and 6 deletions
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4
target-arm/cpu.h
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@ -143,7 +143,7 @@ typedef struct CPUARMState {
uint32_t spsr; uint32_t spsr;
/* Banked registers. */ /* Banked registers. */
uint64_t banked_spsr[6]; uint64_t banked_spsr[8];
uint32_t banked_r13[6]; uint32_t banked_r13[6];
uint32_t banked_r14[6]; uint32_t banked_r14[6];
@ -563,7 +563,9 @@ enum arm_cpu_mode {
ARM_CPU_MODE_FIQ = 0x11, ARM_CPU_MODE_FIQ = 0x11,
ARM_CPU_MODE_IRQ = 0x12, ARM_CPU_MODE_IRQ = 0x12,
ARM_CPU_MODE_SVC = 0x13, ARM_CPU_MODE_SVC = 0x13,
ARM_CPU_MODE_MON = 0x16,
ARM_CPU_MODE_ABT = 0x17, ARM_CPU_MODE_ABT = 0x17,
ARM_CPU_MODE_HYP = 0x1a,
ARM_CPU_MODE_UND = 0x1b, ARM_CPU_MODE_UND = 0x1b,
ARM_CPU_MODE_SYS = 0x1f ARM_CPU_MODE_SYS = 0x1f
}; };

4
target-arm/helper.c
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@ -3108,6 +3108,10 @@ int bank_number(int mode)
return 4; return 4;
case ARM_CPU_MODE_FIQ: case ARM_CPU_MODE_FIQ:
return 5; return 5;
case ARM_CPU_MODE_HYP:
return 6;
case ARM_CPU_MODE_MON:
return 7;
} }
hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode); hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode);
} }

6
target-arm/machine.c
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@ -218,8 +218,8 @@ static int cpu_post_load(void *opaque, int version_id)
const VMStateDescription vmstate_arm_cpu = { const VMStateDescription vmstate_arm_cpu = {
.name = "cpu", .name = "cpu",
.version_id = 19, .version_id = 20,
.minimum_version_id = 19, .minimum_version_id = 20,
.pre_save = cpu_pre_save, .pre_save = cpu_pre_save,
.post_load = cpu_post_load, .post_load = cpu_post_load,
.fields = (VMStateField[]) { .fields = (VMStateField[]) {
@ -233,7 +233,7 @@ const VMStateDescription vmstate_arm_cpu = {
.offset = 0, .offset = 0,
}, },
VMSTATE_UINT32(env.spsr, ARMCPU), VMSTATE_UINT32(env.spsr, ARMCPU),
VMSTATE_UINT64_ARRAY(env.banked_spsr, ARMCPU, 6), VMSTATE_UINT64_ARRAY(env.banked_spsr, ARMCPU, 8),
VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 6), VMSTATE_UINT32_ARRAY(env.banked_r13, ARMCPU, 6),
VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 6), VMSTATE_UINT32_ARRAY(env.banked_r14, ARMCPU, 6),
VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5), VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5),

4
target-arm/translate.c
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@ -11052,8 +11052,8 @@ void gen_intermediate_code_pc(CPUARMState *env, TranslationBlock *tb)
} }
static const char *cpu_mode_names[16] = { static const char *cpu_mode_names[16] = {
"usr", "fiq", "irq", "svc", "???", "???", "???", "abt", "usr", "fiq", "irq", "svc", "???", "???", "mon", "abt",
"???", "???", "???", "und", "???", "???", "???", "sys" "???", "???", "hyp", "und", "???", "???", "???", "sys"
}; };
void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,