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target-ppc: Add float register read/write using XML

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Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6423 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
aurel32 2009-01-24 15:08:00 +00:00
parent 4e47ea6702
commit 2495152227
1 changed files with 32 additions and 0 deletions
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32
target-ppc/translate_init.c
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@ -9272,6 +9272,33 @@ static void dump_ppc_insns (CPUPPCState *env)
} }
#endif #endif
static int gdb_get_float_reg(CPUState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
stfq_p(mem_buf, env->fpr[n]);
return 8;
}
if (n == 32) {
/* FPSCR not implemented */
memset(mem_buf, 0, 4);
return 4;
}
return 0;
}
static int gdb_set_float_reg(CPUState *env, uint8_t *mem_buf, int n)
{
if (n < 32) {
env->fpr[n] = ldfq_p(mem_buf);
return 8;
}
if (n == 32) {
/* FPSCR not implemented */
return 4;
}
return 0;
}
int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def) int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def)
{ {
env->msr_mask = def->msr_mask; env->msr_mask = def->msr_mask;
@ -9284,6 +9311,11 @@ int cpu_ppc_register_internal (CPUPPCState *env, const ppc_def_t *def)
if (create_ppc_opcodes(env, def) < 0) if (create_ppc_opcodes(env, def) < 0)
return -1; return -1;
init_ppc_proc(env, def); init_ppc_proc(env, def);
if (def->insns_flags & PPC_FLOAT) {
gdb_register_coprocessor(env, gdb_get_float_reg, gdb_set_float_reg,
33, "power-fpu.xml", 0);
}
#if defined(PPC_DUMP_CPU) #if defined(PPC_DUMP_CPU)
{ {
const char *mmu_model, *excp_model, *bus_model; const char *mmu_model, *excp_model, *bus_model;