David Venhoff
cfcea9ee67
Based off b80915eb99
and compacted into a single commit so that it will fit on the uni git server
40 lines
1.5 KiB
Plaintext
40 lines
1.5 KiB
Plaintext
GENI based Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI)
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The QUP v3 core is a GENI based AHB slave that provides a common data path
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(an output FIFO and an input FIFO) for serial peripheral interface (SPI)
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mini-core.
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SPI in master mode supports up to 50MHz, up to four chip selects, programmable
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data path from 4 bits to 32 bits and numerous protocol variants.
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Required properties:
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- compatible: Must contain "qcom,geni-spi".
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- reg: Must contain SPI register location and length.
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- interrupts: Must contain SPI controller interrupts.
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- clock-names: Must contain "se".
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- clocks: Serial engine core clock needed by the device.
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- #address-cells: Must be <1> to define a chip select address on
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the SPI bus.
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- #size-cells: Must be <0>.
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SPI Controller nodes must be child of GENI based Qualcomm Universal
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Peripharal. Please refer GENI based QUP wrapper controller node bindings
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described in Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml.
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SPI slave nodes must be children of the SPI master node and conform to SPI bus
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binding as described in Documentation/devicetree/bindings/spi/spi-bus.txt.
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Example:
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spi0: spi@a84000 {
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compatible = "qcom,geni-spi";
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reg = <0xa84000 0x4000>;
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interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "se";
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clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qup_1_spi_2_active>;
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pinctrl-1 = <&qup_1_spi_2_sleep>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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