David Venhoff
cfcea9ee67
Based off b80915eb99
and compacted into a single commit so that it will fit on the uni git server
172 lines
3.7 KiB
Plaintext
172 lines
3.7 KiB
Plaintext
This document describes the generic device tree binding for describing the
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relationship between PCI(e) devices and IOMMU(s).
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Each PCI(e) device under a root complex is uniquely identified by its Requester
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ID (AKA RID). A Requester ID is a triplet of a Bus number, Device number, and
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Function number.
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For the purpose of this document, when treated as a numeric value, a RID is
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formatted such that:
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* Bits [15:8] are the Bus number.
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* Bits [7:3] are the Device number.
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* Bits [2:0] are the Function number.
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* Any other bits required for padding must be zero.
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IOMMUs may distinguish PCI devices through sideband data derived from the
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Requester ID. While a given PCI device can only master through one IOMMU, a
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root complex may split masters across a set of IOMMUs (e.g. with one IOMMU per
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bus).
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The generic 'iommus' property is insufficient to describe this relationship,
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and a mechanism is required to map from a PCI device to its IOMMU and sideband
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data.
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For generic IOMMU bindings, see
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Documentation/devicetree/bindings/iommu/iommu.txt.
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PCI root complex
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================
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Optional properties
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-------------------
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- iommu-map: Maps a Requester ID to an IOMMU and associated IOMMU specifier
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data.
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The property is an arbitrary number of tuples of
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(rid-base,iommu,iommu-base,length).
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Any RID r in the interval [rid-base, rid-base + length) is associated with
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the listed IOMMU, with the IOMMU specifier (r - rid-base + iommu-base).
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- iommu-map-mask: A mask to be applied to each Requester ID prior to being
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mapped to an IOMMU specifier per the iommu-map property.
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Example (1)
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===========
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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iommu: iommu@a {
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reg = <0xa 0x1>;
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compatible = "vendor,some-iommu";
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#iommu-cells = <1>;
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};
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pci: pci@f {
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reg = <0xf 0x1>;
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compatible = "vendor,pcie-root-complex";
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device_type = "pci";
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/*
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* The sideband data provided to the IOMMU is the RID,
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* identity-mapped.
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*/
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iommu-map = <0x0 &iommu 0x0 0x10000>;
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};
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};
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Example (2)
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===========
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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iommu: iommu@a {
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reg = <0xa 0x1>;
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compatible = "vendor,some-iommu";
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#iommu-cells = <1>;
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};
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pci: pci@f {
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reg = <0xf 0x1>;
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compatible = "vendor,pcie-root-complex";
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device_type = "pci";
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/*
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* The sideband data provided to the IOMMU is the RID with the
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* function bits masked out.
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*/
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iommu-map = <0x0 &iommu 0x0 0x10000>;
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iommu-map-mask = <0xfff8>;
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};
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};
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Example (3)
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===========
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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iommu: iommu@a {
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reg = <0xa 0x1>;
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compatible = "vendor,some-iommu";
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#iommu-cells = <1>;
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};
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pci: pci@f {
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reg = <0xf 0x1>;
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compatible = "vendor,pcie-root-complex";
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device_type = "pci";
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/*
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* The sideband data provided to the IOMMU is the RID,
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* but the high bits of the bus number are flipped.
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*/
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iommu-map = <0x0000 &iommu 0x8000 0x8000>,
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<0x8000 &iommu 0x0000 0x8000>;
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};
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};
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Example (4)
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===========
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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iommu_a: iommu@a {
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reg = <0xa 0x1>;
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compatible = "vendor,some-iommu";
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#iommu-cells = <1>;
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};
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iommu_b: iommu@b {
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reg = <0xb 0x1>;
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compatible = "vendor,some-iommu";
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#iommu-cells = <1>;
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};
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iommu_c: iommu@c {
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reg = <0xc 0x1>;
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compatible = "vendor,some-iommu";
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#iommu-cells = <1>;
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};
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pci: pci@f {
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reg = <0xf 0x1>;
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compatible = "vendor,pcie-root-complex";
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device_type = "pci";
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/*
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* Devices with bus number 0-127 are mastered via IOMMU
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* a, with sideband data being RID[14:0].
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* Devices with bus number 128-255 are mastered via
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* IOMMU b, with sideband data being RID[14:0].
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* No devices master via IOMMU c.
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*/
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iommu-map = <0x0000 &iommu_a 0x0000 0x8000>,
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<0x8000 &iommu_b 0x0000 0x8000>;
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};
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};
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