David Venhoff
cfcea9ee67
Based off b80915eb99
and compacted into a single commit so that it will fit on the uni git server
20 lines
629 B
Plaintext
20 lines
629 B
Plaintext
Altera SOCFPGA Arria10 FPGA Manager
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Required properties:
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- compatible : should contain "altr,socfpga-a10-fpga-mgr"
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- reg : base address and size for memory mapped io.
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- The first index is for FPGA manager register access.
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- The second index is for writing FPGA configuration data.
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- resets : Phandle and reset specifier for the device's reset.
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- clocks : Clocks used by the device.
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Example:
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fpga_mgr: fpga-mgr@ffd03000 {
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compatible = "altr,socfpga-a10-fpga-mgr";
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reg = <0xffd03000 0x100
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0xffcfe400 0x20>;
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clocks = <&l4_mp_clk>;
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resets = <&rst FPGAMGR_RESET>;
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};
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