David Venhoff
cfcea9ee67
Based off b80915eb99
and compacted into a single commit so that it will fit on the uni git server
99 lines
2.5 KiB
Plaintext
99 lines
2.5 KiB
Plaintext
Rockchip RK3288 specific extensions to the Analogix Display Port
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================================
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Required properties:
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- compatible: "rockchip,rk3288-dp",
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"rockchip,rk3399-edp";
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- reg: physical base address of the controller and length
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- clocks: from common clock binding: handle to dp clock.
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of memory mapped region.
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- clock-names: from common clock binding:
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Required elements: "dp" "pclk"
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- resets: Must contain an entry for each entry in reset-names.
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See ../reset/reset.txt for details.
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- pinctrl-names: Names corresponding to the chip hotplug pinctrl states.
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- pinctrl-0: pin-control mode. should be <&edp_hpd>
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- reset-names: Must include the name "dp"
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- rockchip,grf: this soc should set GRF regs, so need get grf here.
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- ports: there are 2 port nodes with endpoint definitions as defined in
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Documentation/devicetree/bindings/media/video-interfaces.txt.
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Port 0: contained 2 endpoints, connecting to the output of vop.
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Port 1: contained 1 endpoint, connecting to the input of panel.
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Optional property for different chips:
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- clocks: from common clock binding: handle to grf_vio clock.
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- clock-names: from common clock binding:
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Required elements: "grf"
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For the below properties, please refer to Analogix DP binding document:
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* Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
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- phys (required)
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- phy-names (required)
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- hpd-gpios (optional)
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- force-hpd (optional)
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-------------------------------------------------------------------------------
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Example:
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dp-controller: dp@ff970000 {
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compatible = "rockchip,rk3288-dp";
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reg = <0xff970000 0x4000>;
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interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
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clock-names = "dp", "pclk";
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phys = <&dp_phy>;
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phy-names = "dp";
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rockchip,grf = <&grf>;
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resets = <&cru 111>;
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reset-names = "dp";
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pinctrl-names = "default";
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pinctrl-0 = <&edp_hpd>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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edp_in: port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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edp_in_vopb: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&vopb_out_edp>;
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};
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edp_in_vopl: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&vopl_out_edp>;
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};
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};
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edp_out: port@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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edp_out_panel: endpoint {
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reg = <0>;
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remote-endpoint = <&panel_in_edp>
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};
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};
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};
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};
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pinctrl {
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edp {
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edp_hpd: edp-hpd {
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rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_none>;
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};
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};
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};
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