David Venhoff
cfcea9ee67
Based off b80915eb99
and compacted into a single commit so that it will fit on the uni git server
25 lines
477 B
Plaintext
25 lines
477 B
Plaintext
* Renesas H8/300 divider clock
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Required Properties:
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- compatible: Must be "renesas,h8300-div-clock"
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- clocks: Reference to the parent clocks ("extal1" and "extal2")
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- #clock-cells: Must be 1
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- reg: Base address and length of the divide rate selector
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- renesas,width: bit width of selector
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Example
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-------
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cclk: cclk {
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compatible = "renesas,h8300-div-clock";
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clocks = <&xclk>;
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#clock-cells = <0>;
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reg = <0xfee01b 2>;
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renesas,width = <2>;
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};
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