e38d3c5ce5
$ ./scripts/codeconverter/converter.py -i \ --pattern=TypeCheckMacro $(git grep -l '' -- '*.[ch]') Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Message-Id: <20200831210740.126168-12-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
74 lines
1.9 KiB
C
74 lines
1.9 KiB
C
/*
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* QEMU SiFive E PRCI (Power, Reset, Clock, Interrupt) interface
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*
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* Copyright (c) 2017 SiFive, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_SIFIVE_E_PRCI_H
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#define HW_SIFIVE_E_PRCI_H
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#include "qom/object.h"
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enum {
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SIFIVE_E_PRCI_HFROSCCFG = 0x0,
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SIFIVE_E_PRCI_HFXOSCCFG = 0x4,
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SIFIVE_E_PRCI_PLLCFG = 0x8,
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SIFIVE_E_PRCI_PLLOUTDIV = 0xC
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};
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enum {
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SIFIVE_E_PRCI_HFROSCCFG_RDY = (1 << 31),
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SIFIVE_E_PRCI_HFROSCCFG_EN = (1 << 30)
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};
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enum {
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SIFIVE_E_PRCI_HFXOSCCFG_RDY = (1 << 31),
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SIFIVE_E_PRCI_HFXOSCCFG_EN = (1 << 30)
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};
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enum {
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SIFIVE_E_PRCI_PLLCFG_PLLSEL = (1 << 16),
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SIFIVE_E_PRCI_PLLCFG_REFSEL = (1 << 17),
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SIFIVE_E_PRCI_PLLCFG_BYPASS = (1 << 18),
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SIFIVE_E_PRCI_PLLCFG_LOCK = (1 << 31)
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};
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enum {
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SIFIVE_E_PRCI_PLLOUTDIV_DIV1 = (1 << 8)
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};
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#define SIFIVE_E_PRCI_REG_SIZE 0x1000
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#define TYPE_SIFIVE_E_PRCI "riscv.sifive.e.prci"
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typedef struct SiFiveEPRCIState SiFiveEPRCIState;
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DECLARE_INSTANCE_CHECKER(SiFiveEPRCIState, SIFIVE_E_PRCI,
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TYPE_SIFIVE_E_PRCI)
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struct SiFiveEPRCIState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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MemoryRegion mmio;
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uint32_t hfrosccfg;
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uint32_t hfxosccfg;
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uint32_t pllcfg;
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uint32_t plloutdiv;
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};
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DeviceState *sifive_e_prci_create(hwaddr addr);
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#endif
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