299 lines
		
	
	
		
			8.4 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			299 lines
		
	
	
		
			8.4 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * KVM in-kernel OpenPIC
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|  *
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|  * Copyright 2013 Freescale Semiconductor, Inc.
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|  *
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|  * Permission is hereby granted, free of charge, to any person obtaining a copy
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|  * of this software and associated documentation files (the "Software"), to deal
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|  * in the Software without restriction, including without limitation the rights
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|  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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|  * copies of the Software, and to permit persons to whom the Software is
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|  * furnished to do so, subject to the following conditions:
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|  *
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|  * The above copyright notice and this permission notice shall be included in
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|  * all copies or substantial portions of the Software.
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|  *
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|  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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|  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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|  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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|  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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|  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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|  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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|  * THE SOFTWARE.
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|  */
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| 
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| #include "qemu/osdep.h"
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| #include "qapi/error.h"
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| #include "qemu-common.h"
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| #include "cpu.h"
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| #include <sys/ioctl.h>
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| #include "exec/address-spaces.h"
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| #include "hw/hw.h"
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| #include "hw/ppc/openpic.h"
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| #include "hw/pci/msi.h"
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| #include "hw/sysbus.h"
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| #include "sysemu/kvm.h"
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| #include "qemu/log.h"
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| 
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| #define GCR_RESET        0x80000000
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| 
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| #define KVM_OPENPIC(obj) \
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|     OBJECT_CHECK(KVMOpenPICState, (obj), TYPE_KVM_OPENPIC)
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| 
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| typedef struct KVMOpenPICState {
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|     /*< private >*/
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|     SysBusDevice parent_obj;
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|     /*< public >*/
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| 
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|     MemoryRegion mem;
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|     MemoryListener mem_listener;
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|     uint32_t fd;
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|     uint32_t model;
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|     hwaddr mapped;
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| } KVMOpenPICState;
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| 
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| static void kvm_openpic_set_irq(void *opaque, int n_IRQ, int level)
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| {
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|     kvm_set_irq(kvm_state, n_IRQ, level);
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| }
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| 
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| static void kvm_openpic_write(void *opaque, hwaddr addr, uint64_t val,
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|                               unsigned size)
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| {
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|     KVMOpenPICState *opp = opaque;
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|     struct kvm_device_attr attr;
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|     uint32_t val32 = val;
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|     int ret;
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| 
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|     attr.group = KVM_DEV_MPIC_GRP_REGISTER;
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|     attr.attr = addr;
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|     attr.addr = (uint64_t)(unsigned long)&val32;
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| 
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|     ret = ioctl(opp->fd, KVM_SET_DEVICE_ATTR, &attr);
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|     if (ret < 0) {
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|         qemu_log_mask(LOG_UNIMP, "%s: %s %" PRIx64 "\n", __func__,
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|                       strerror(errno), attr.attr);
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|     }
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| }
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| 
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| static void kvm_openpic_reset(DeviceState *d)
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| {
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|     KVMOpenPICState *opp = KVM_OPENPIC(d);
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| 
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|     /* Trigger the GCR.RESET bit to reset the PIC */
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|     kvm_openpic_write(opp, 0x1020, GCR_RESET, sizeof(uint32_t));
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| }
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| 
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| static uint64_t kvm_openpic_read(void *opaque, hwaddr addr, unsigned size)
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| {
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|     KVMOpenPICState *opp = opaque;
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|     struct kvm_device_attr attr;
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|     uint32_t val = 0xdeadbeef;
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|     int ret;
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| 
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|     attr.group = KVM_DEV_MPIC_GRP_REGISTER;
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|     attr.attr = addr;
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|     attr.addr = (uint64_t)(unsigned long)&val;
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| 
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|     ret = ioctl(opp->fd, KVM_GET_DEVICE_ATTR, &attr);
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|     if (ret < 0) {
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|         qemu_log_mask(LOG_UNIMP, "%s: %s %" PRIx64 "\n", __func__,
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|                       strerror(errno), attr.attr);
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|         return 0;
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|     }
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| 
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|     return val;
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| }
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| 
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| static const MemoryRegionOps kvm_openpic_mem_ops = {
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|     .write = kvm_openpic_write,
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|     .read  = kvm_openpic_read,
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|     .endianness = DEVICE_BIG_ENDIAN,
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|     .impl = {
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|         .min_access_size = 4,
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|         .max_access_size = 4,
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|     },
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| };
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| 
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| static void kvm_openpic_region_add(MemoryListener *listener,
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|                                    MemoryRegionSection *section)
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| {
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|     KVMOpenPICState *opp = container_of(listener, KVMOpenPICState,
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|                                         mem_listener);
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|     struct kvm_device_attr attr;
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|     uint64_t reg_base;
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|     int ret;
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| 
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|     if (section->address_space != &address_space_memory) {
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|         abort();
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|     }
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| 
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|     /* Ignore events on regions that are not us */
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|     if (section->mr != &opp->mem) {
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|         return;
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|     }
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| 
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|     if (opp->mapped) {
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|         /*
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|          * We can only map the MPIC once. Since we are already mapped,
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|          * the best we can do is ignore new maps.
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|          */
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|         return;
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|     }
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| 
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|     reg_base = section->offset_within_address_space;
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|     opp->mapped = reg_base;
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| 
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|     attr.group = KVM_DEV_MPIC_GRP_MISC;
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|     attr.attr = KVM_DEV_MPIC_BASE_ADDR;
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|     attr.addr = (uint64_t)(unsigned long)®_base;
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| 
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|     ret = ioctl(opp->fd, KVM_SET_DEVICE_ATTR, &attr);
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|     if (ret < 0) {
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|         fprintf(stderr, "%s: %s %" PRIx64 "\n", __func__,
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|                 strerror(errno), reg_base);
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|     }
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| }
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| 
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| static void kvm_openpic_region_del(MemoryListener *listener,
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|                                    MemoryRegionSection *section)
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| {
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|     KVMOpenPICState *opp = container_of(listener, KVMOpenPICState,
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|                                         mem_listener);
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|     struct kvm_device_attr attr;
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|     uint64_t reg_base = 0;
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|     int ret;
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| 
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|     /* Ignore events on regions that are not us */
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|     if (section->mr != &opp->mem) {
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|         return;
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|     }
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| 
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|     if (section->offset_within_address_space != opp->mapped) {
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|         /*
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|          * We can only map the MPIC once. This mapping was a secondary
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|          * one that we couldn't fulfill. Ignore it.
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|          */
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|         return;
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|     }
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|     opp->mapped = 0;
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| 
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|     attr.group = KVM_DEV_MPIC_GRP_MISC;
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|     attr.attr = KVM_DEV_MPIC_BASE_ADDR;
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|     attr.addr = (uint64_t)(unsigned long)®_base;
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| 
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|     ret = ioctl(opp->fd, KVM_SET_DEVICE_ATTR, &attr);
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|     if (ret < 0) {
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|         fprintf(stderr, "%s: %s %" PRIx64 "\n", __func__,
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|                 strerror(errno), reg_base);
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|     }
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| }
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| 
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| static void kvm_openpic_init(Object *obj)
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| {
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|     KVMOpenPICState *opp = KVM_OPENPIC(obj);
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| 
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|     memory_region_init_io(&opp->mem, OBJECT(opp), &kvm_openpic_mem_ops, opp,
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|                           "kvm-openpic", 0x40000);
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| }
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| 
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| static void kvm_openpic_realize(DeviceState *dev, Error **errp)
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| {
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|     SysBusDevice *d = SYS_BUS_DEVICE(dev);
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|     KVMOpenPICState *opp = KVM_OPENPIC(dev);
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|     KVMState *s = kvm_state;
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|     int kvm_openpic_model;
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|     struct kvm_create_device cd = {0};
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|     int ret, i;
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| 
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|     if (!kvm_check_extension(s, KVM_CAP_DEVICE_CTRL)) {
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|         error_setg(errp, "Kernel is lacking Device Control API");
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|         return;
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|     }
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| 
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|     switch (opp->model) {
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|     case OPENPIC_MODEL_FSL_MPIC_20:
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|         kvm_openpic_model = KVM_DEV_TYPE_FSL_MPIC_20;
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|         break;
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| 
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|     case OPENPIC_MODEL_FSL_MPIC_42:
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|         kvm_openpic_model = KVM_DEV_TYPE_FSL_MPIC_42;
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|         break;
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| 
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|     default:
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|         error_setg(errp, "Unsupported OpenPIC model %" PRIu32, opp->model);
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|         return;
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|     }
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| 
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|     cd.type = kvm_openpic_model;
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|     ret = kvm_vm_ioctl(s, KVM_CREATE_DEVICE, &cd);
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|     if (ret < 0) {
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|         error_setg(errp, "Can't create device %d: %s",
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|                    cd.type, strerror(errno));
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|         return;
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|     }
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|     opp->fd = cd.fd;
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| 
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|     sysbus_init_mmio(d, &opp->mem);
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|     qdev_init_gpio_in(dev, kvm_openpic_set_irq, OPENPIC_MAX_IRQ);
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| 
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|     opp->mem_listener.region_add = kvm_openpic_region_add;
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|     opp->mem_listener.region_del = kvm_openpic_region_del;
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|     memory_listener_register(&opp->mem_listener, &address_space_memory);
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| 
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|     /* indicate pic capabilities */
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|     msi_nonbroken = true;
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|     kvm_kernel_irqchip = true;
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|     kvm_async_interrupts_allowed = true;
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| 
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|     /* set up irq routing */
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|     kvm_init_irq_routing(kvm_state);
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|     for (i = 0; i < 256; ++i) {
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|         kvm_irqchip_add_irq_route(kvm_state, i, 0, i);
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|     }
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| 
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|     kvm_msi_via_irqfd_allowed = true;
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|     kvm_gsi_routing_allowed = true;
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| 
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|     kvm_irqchip_commit_routes(s);
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| }
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| 
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| int kvm_openpic_connect_vcpu(DeviceState *d, CPUState *cs)
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| {
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|     KVMOpenPICState *opp = KVM_OPENPIC(d);
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| 
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|     return kvm_vcpu_enable_cap(cs, KVM_CAP_IRQ_MPIC, 0, opp->fd,
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|                                kvm_arch_vcpu_id(cs));
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| }
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| 
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| static Property kvm_openpic_properties[] = {
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|     DEFINE_PROP_UINT32("model", KVMOpenPICState, model,
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|                        OPENPIC_MODEL_FSL_MPIC_20),
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|     DEFINE_PROP_END_OF_LIST(),
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| };
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| 
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| static void kvm_openpic_class_init(ObjectClass *oc, void *data)
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| {
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|     DeviceClass *dc = DEVICE_CLASS(oc);
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| 
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|     dc->realize = kvm_openpic_realize;
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|     dc->props = kvm_openpic_properties;
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|     dc->reset = kvm_openpic_reset;
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|     set_bit(DEVICE_CATEGORY_MISC, dc->categories);
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| }
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| 
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| static const TypeInfo kvm_openpic_info = {
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|     .name          = TYPE_KVM_OPENPIC,
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|     .parent        = TYPE_SYS_BUS_DEVICE,
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|     .instance_size = sizeof(KVMOpenPICState),
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|     .instance_init = kvm_openpic_init,
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|     .class_init    = kvm_openpic_class_init,
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| };
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| 
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| static void kvm_openpic_register_types(void)
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| {
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|     type_register_static(&kvm_openpic_info);
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| }
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| 
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| type_init(kvm_openpic_register_types)
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