edf5ca5dbe
PCIDeviceClass and PCIDevice are defined in pci.h. Many users of the header don't actually need them. Similar structs live in their own headers: PCIBusClass and PCIBus in pci_bus.h, PCIBridge in pci_bridge.h, PCIHostBridgeClass and PCIHostState in pci_host.h, PCIExpressHost in pcie_host.h, and PCIERootPortClass, PCIEPort, and PCIESlot in pcie_port.h. Move PCIDeviceClass and PCIDeviceClass to new pci_device.h, along with the code that needs them. Adjust include directives. This also enables the next commit. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20221222100330.380143-6-armbru@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
106 lines
3.0 KiB
C
106 lines
3.0 KiB
C
#ifndef MPTSAS_H
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#define MPTSAS_H
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#include "mpi.h"
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#include "hw/pci/pci_device.h"
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#define MPTSAS_NUM_PORTS 8
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#define MPTSAS_MAX_FRAMES 2048 /* Firmware limit at 65535 */
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#define MPTSAS_REQUEST_QUEUE_DEPTH 128
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#define MPTSAS_REPLY_QUEUE_DEPTH 128
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#define MPTSAS_MAXIMUM_CHAIN_DEPTH 0x22
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typedef struct MPTSASRequest MPTSASRequest;
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#define TYPE_MPTSAS1068 "mptsas1068"
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typedef struct MPTSASState MPTSASState;
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DECLARE_INSTANCE_CHECKER(MPTSASState, MPT_SAS,
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TYPE_MPTSAS1068)
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enum {
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DOORBELL_NONE,
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DOORBELL_WRITE,
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DOORBELL_READ
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};
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struct MPTSASState {
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PCIDevice dev;
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MemoryRegion mmio_io;
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MemoryRegion port_io;
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MemoryRegion diag_io;
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QEMUBH *request_bh;
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/* properties */
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OnOffAuto msi;
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uint64_t sas_addr;
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bool msi_in_use;
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/* Doorbell register */
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uint32_t state;
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uint8_t who_init;
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uint8_t doorbell_state;
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/* Buffer for requests that are sent through the doorbell register. */
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uint32_t doorbell_msg[256];
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int doorbell_idx;
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int doorbell_cnt;
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uint16_t doorbell_reply[256];
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int doorbell_reply_idx;
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int doorbell_reply_size;
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/* Other registers */
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uint8_t diagnostic_idx;
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uint32_t diagnostic;
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uint32_t intr_mask;
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uint32_t intr_status;
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/* Request queues */
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uint32_t request_post[MPTSAS_REQUEST_QUEUE_DEPTH + 1];
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uint16_t request_post_head;
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uint16_t request_post_tail;
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uint32_t reply_post[MPTSAS_REPLY_QUEUE_DEPTH + 1];
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uint16_t reply_post_head;
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uint16_t reply_post_tail;
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uint32_t reply_free[MPTSAS_REPLY_QUEUE_DEPTH + 1];
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uint16_t reply_free_head;
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uint16_t reply_free_tail;
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/* IOC Facts */
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hwaddr host_mfa_high_addr;
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hwaddr sense_buffer_high_addr;
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uint16_t max_devices;
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uint16_t max_buses;
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uint16_t reply_frame_size;
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SCSIBus bus;
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};
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void mptsas_fix_scsi_io_endianness(MPIMsgSCSIIORequest *req);
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void mptsas_fix_scsi_io_reply_endianness(MPIMsgSCSIIOReply *reply);
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void mptsas_fix_scsi_task_mgmt_endianness(MPIMsgSCSITaskMgmt *req);
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void mptsas_fix_scsi_task_mgmt_reply_endianness(MPIMsgSCSITaskMgmtReply *reply);
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void mptsas_fix_ioc_init_endianness(MPIMsgIOCInit *req);
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void mptsas_fix_ioc_init_reply_endianness(MPIMsgIOCInitReply *reply);
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void mptsas_fix_ioc_facts_endianness(MPIMsgIOCFacts *req);
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void mptsas_fix_ioc_facts_reply_endianness(MPIMsgIOCFactsReply *reply);
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void mptsas_fix_config_endianness(MPIMsgConfig *req);
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void mptsas_fix_config_reply_endianness(MPIMsgConfigReply *reply);
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void mptsas_fix_port_facts_endianness(MPIMsgPortFacts *req);
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void mptsas_fix_port_facts_reply_endianness(MPIMsgPortFactsReply *reply);
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void mptsas_fix_port_enable_endianness(MPIMsgPortEnable *req);
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void mptsas_fix_port_enable_reply_endianness(MPIMsgPortEnableReply *reply);
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void mptsas_fix_event_notification_endianness(MPIMsgEventNotify *req);
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void mptsas_fix_event_notification_reply_endianness(MPIMsgEventNotifyReply *reply);
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void mptsas_reply(MPTSASState *s, MPIDefaultReply *reply);
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void mptsas_process_config(MPTSASState *s, MPIMsgConfig *req);
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#endif /* MPTSAS_H */
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