Ard Biesheuvel f1ecb913d8 target-arm: add support for v8 SHA1 and SHA256 instructions ...

This adds support for the SHA1 and SHA256 instructions that are available
on some v8 implementations of Aarch32.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1401386724-26529-2-git-send-email-peter.maydell@linaro.org
[PMM:
 * rebase
 * fix bad indent
 * add a missing UNDEF check for Q!=1 in the 3-reg SHA1/SHA256 case
 * use g_assert_not_reached()
 * don't re-extract bit 6 for the 2-reg-misc encodings
 * set the ELF HWCAP2 bits for the new features
]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

2014-06-09 16:06:11 +01:00

..

arm_ldst.h

softmmu: introduce cpu_ldst.h

2014-06-05 16:10:33 +02:00

arm-semi.c

cpu: Move opaque field from CPU_COMMON to CPUState

2014-03-13 19:20:47 +01:00

cpu64.c

target-arm/cpu64.c: Actually register Cortex-A57 impdef registers

2014-06-09 15:43:22 +01:00

cpu-qom.h

target-arm: Dump 32-bit CPU state if 64 bit CPU is in AArch32

2014-04-17 21:34:06 +01:00

cpu.c

target-arm: add support for v8 SHA1 and SHA256 instructions

2014-06-09 16:06:11 +01:00

cpu.h

target-arm: add support for v8 SHA1 and SHA256 instructions

2014-06-09 16:06:11 +01:00

crypto_helper.c

target-arm: add support for v8 SHA1 and SHA256 instructions

2014-06-09 16:06:11 +01:00

gdbstub64.c

target-arm/gdbstub64.c: remove useless 'break' statement.

2014-04-17 21:34:06 +01:00

gdbstub.c

cpu: Introduce CPUClass::gdb_{read,write}_register()

2013-07-27 00:04:17 +02:00

helper-a64.c

tcg: Invert the inclusion of helper.h

2014-05-28 09:33:54 -07:00

helper-a64.h

target-arm: A64: Implement FCVTXN

2014-03-17 16:31:53 +00:00

helper.c

target-arm: Correct handling of UXN bit in ARMv8 LPAE page tables

2014-06-09 16:06:11 +01:00

helper.h

target-arm: add support for v8 SHA1 and SHA256 instructions

2014-06-09 16:06:11 +01:00

internals.h

target-arm: A64: Generalize update_spsel for the various ELs

2014-05-27 17:09:54 +01:00

iwmmxt_helper.c

tcg: Invert the inclusion of helper.h

2014-05-28 09:33:54 -07:00

kvm32.c

kvm: reset state from the CPU's reset method

2014-05-13 13:12:40 +02:00

kvm64.c

target-arm: Make elr_el1 an array

2014-05-27 17:09:51 +01:00

kvm_arm.h

kvm: reset state from the CPU's reset method

2014-05-13 13:12:40 +02:00

kvm-consts.h

target-arm/kvm-consts.h: Define QEMU constants for known KVM CPUs

2014-02-20 10:35:50 +00:00

kvm-stub.c

target-arm: Initialize cpreg list from KVM when using KVM

2013-06-25 18:16:10 +01:00

kvm.c

arm: vgic device control api support

2014-02-26 17:20:00 +00:00

machine.c

target-arm: Add SPSR entries for EL2/HYP and EL3/MON

2014-05-27 17:09:52 +01:00

Makefile.objs

target-arm: A64: add stubs for a64 specific helpers

2013-12-17 19:42:32 +00:00

neon_helper.c

tcg: Invert the inclusion of helper.h

2014-05-28 09:33:54 -07:00

op_addsub.h

Correct spelling of licensed

2011-07-23 11:26:12 -05:00

op_helper.c

softmmu: introduce cpu_ldst.h

2014-06-05 16:10:33 +02:00

translate-a64.c

target-arm: move arm_*_code to a separate file

2014-06-05 16:10:33 +02:00

translate.c

target-arm: add support for v8 SHA1 and SHA256 instructions

2014-06-09 16:06:11 +01:00

translate.h

target-arm: Use a 1:1 mapping between EL and MMU index

2014-05-27 17:09:51 +01:00