ec7d83acbd
This object is used to represent every multiplexer in the clock tree as well as every clock output, every presecaler, frequency multiplier, etc. This allows to use a generic approach for every component of the clock tree (except the PLLs). The migration handling is based on hw/misc/zynq_sclr.c. Three phase reset will be handled in a later commit. Signed-off-by: Arnaud Minier <arnaud.minier@telecom-paris.fr> Signed-off-by: Inès Varhol <ines.varhol@telecom-paris.fr> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20240303140643.81957-3-arnaud.minier@telecom-paris.fr Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
607 lines
17 KiB
C
607 lines
17 KiB
C
/*
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* STM32L4X5 RCC (Reset and clock control)
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*
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* Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr>
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* Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr>
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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* The reference used is the STMicroElectronics RM0351 Reference manual
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* for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs.
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*
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* Inspired by the BCM2835 CPRMAN clock manager implementation by Luc Michel.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "qemu/timer.h"
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#include "qapi/error.h"
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#include "migration/vmstate.h"
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#include "hw/misc/stm32l4x5_rcc.h"
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#include "hw/misc/stm32l4x5_rcc_internals.h"
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#include "hw/clock.h"
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#include "hw/irq.h"
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#include "hw/qdev-clock.h"
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#include "hw/qdev-properties.h"
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#include "hw/qdev-properties-system.h"
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#include "trace.h"
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#define HSE_DEFAULT_FRQ 48000000ULL
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#define HSI_FRQ 16000000ULL
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#define MSI_DEFAULT_FRQ 4000000ULL
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#define LSE_FRQ 32768ULL
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#define LSI_FRQ 32000ULL
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static void clock_mux_update(RccClockMuxState *mux)
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{
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uint64_t src_freq;
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Clock *current_source = mux->srcs[mux->src];
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uint32_t freq_multiplier = 0;
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/*
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* To avoid rounding errors, we use the clock period instead of the
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* frequency.
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* This means that the multiplier of the mux becomes the divider of
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* the clock and the divider of the mux becomes the multiplier of the
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* clock.
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*/
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if (mux->enabled && mux->divider) {
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freq_multiplier = mux->divider;
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}
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clock_set_mul_div(mux->out, freq_multiplier, mux->multiplier);
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clock_update(mux->out, clock_get(current_source));
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src_freq = clock_get_hz(current_source);
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/* TODO: can we simply detect if the config changed so that we reduce log spam ? */
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trace_stm32l4x5_rcc_mux_update(mux->id, mux->src, src_freq,
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mux->multiplier, mux->divider);
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}
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static void clock_mux_src_update(void *opaque, ClockEvent event)
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{
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RccClockMuxState **backref = opaque;
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RccClockMuxState *s = *backref;
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/*
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* The backref value is equal to:
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* s->backref + (sizeof(RccClockMuxState *) * update_src).
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* By subtracting we can get back the index of the updated clock.
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*/
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const uint32_t update_src = backref - s->backref;
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/* Only update if the clock that was updated is the current source */
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if (update_src == s->src) {
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clock_mux_update(s);
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}
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}
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static void clock_mux_init(Object *obj)
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{
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RccClockMuxState *s = RCC_CLOCK_MUX(obj);
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size_t i;
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for (i = 0; i < RCC_NUM_CLOCK_MUX_SRC; i++) {
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char *name = g_strdup_printf("srcs[%zu]", i);
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s->backref[i] = s;
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s->srcs[i] = qdev_init_clock_in(DEVICE(s), name,
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clock_mux_src_update,
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&s->backref[i],
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ClockUpdate);
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g_free(name);
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}
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s->out = qdev_init_clock_out(DEVICE(s), "out");
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}
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static void clock_mux_reset_hold(Object *obj)
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{ }
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static const VMStateDescription clock_mux_vmstate = {
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.name = TYPE_RCC_CLOCK_MUX,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32(id, RccClockMuxState),
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VMSTATE_ARRAY_CLOCK(srcs, RccClockMuxState,
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RCC_NUM_CLOCK_MUX_SRC),
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VMSTATE_BOOL(enabled, RccClockMuxState),
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VMSTATE_UINT32(src, RccClockMuxState),
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VMSTATE_UINT32(multiplier, RccClockMuxState),
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VMSTATE_UINT32(divider, RccClockMuxState),
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VMSTATE_END_OF_LIST()
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}
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};
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static void clock_mux_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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ResettableClass *rc = RESETTABLE_CLASS(klass);
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rc->phases.hold = clock_mux_reset_hold;
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dc->vmsd = &clock_mux_vmstate;
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}
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static void clock_mux_set_enable(RccClockMuxState *mux, bool enabled)
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{
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if (mux->enabled == enabled) {
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return;
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}
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if (enabled) {
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trace_stm32l4x5_rcc_mux_enable(mux->id);
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} else {
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trace_stm32l4x5_rcc_mux_disable(mux->id);
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}
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mux->enabled = enabled;
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clock_mux_update(mux);
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}
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static void clock_mux_set_factor(RccClockMuxState *mux,
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uint32_t multiplier, uint32_t divider)
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{
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if (mux->multiplier == multiplier && mux->divider == divider) {
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return;
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}
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trace_stm32l4x5_rcc_mux_set_factor(mux->id,
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mux->multiplier, multiplier, mux->divider, divider);
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mux->multiplier = multiplier;
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mux->divider = divider;
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clock_mux_update(mux);
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}
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static void clock_mux_set_source(RccClockMuxState *mux, RccClockMuxSource src)
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{
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if (mux->src == src) {
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return;
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}
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trace_stm32l4x5_rcc_mux_set_src(mux->id, mux->src, src);
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mux->src = src;
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clock_mux_update(mux);
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}
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static void rcc_update_irq(Stm32l4x5RccState *s)
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{
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if (s->cifr & CIFR_IRQ_MASK) {
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qemu_irq_raise(s->irq);
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} else {
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qemu_irq_lower(s->irq);
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}
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}
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static void stm32l4x5_rcc_reset_hold(Object *obj)
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{
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Stm32l4x5RccState *s = STM32L4X5_RCC(obj);
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s->cr = 0x00000063;
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/*
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* Factory-programmed calibration data
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* From the reference manual: 0x10XX 00XX
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* Value taken from a real card.
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*/
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s->icscr = 0x106E0082;
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s->cfgr = 0x0;
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s->pllcfgr = 0x00001000;
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s->pllsai1cfgr = 0x00001000;
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s->pllsai2cfgr = 0x00001000;
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s->cier = 0x0;
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s->cifr = 0x0;
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s->ahb1rstr = 0x0;
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s->ahb2rstr = 0x0;
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s->ahb3rstr = 0x0;
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s->apb1rstr1 = 0x0;
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s->apb1rstr2 = 0x0;
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s->apb2rstr = 0x0;
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s->ahb1enr = 0x00000100;
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s->ahb2enr = 0x0;
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s->ahb3enr = 0x0;
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s->apb1enr1 = 0x0;
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s->apb1enr2 = 0x0;
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s->apb2enr = 0x0;
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s->ahb1smenr = 0x00011303;
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s->ahb2smenr = 0x000532FF;
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s->ahb3smenr = 0x00000101;
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s->apb1smenr1 = 0xF2FECA3F;
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s->apb1smenr2 = 0x00000025;
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s->apb2smenr = 0x01677C01;
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s->ccipr = 0x0;
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s->bdcr = 0x0;
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s->csr = 0x0C000600;
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}
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static uint64_t stm32l4x5_rcc_read(void *opaque, hwaddr addr,
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unsigned int size)
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{
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Stm32l4x5RccState *s = opaque;
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uint64_t retvalue = 0;
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switch (addr) {
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case A_CR:
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retvalue = s->cr;
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break;
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case A_ICSCR:
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retvalue = s->icscr;
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break;
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case A_CFGR:
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retvalue = s->cfgr;
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break;
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case A_PLLCFGR:
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retvalue = s->pllcfgr;
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break;
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case A_PLLSAI1CFGR:
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retvalue = s->pllsai1cfgr;
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break;
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case A_PLLSAI2CFGR:
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retvalue = s->pllsai2cfgr;
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break;
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case A_CIER:
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retvalue = s->cier;
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break;
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case A_CIFR:
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retvalue = s->cifr;
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break;
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case A_CICR:
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/* CICR is write only, return the reset value = 0 */
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break;
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case A_AHB1RSTR:
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retvalue = s->ahb1rstr;
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break;
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case A_AHB2RSTR:
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retvalue = s->ahb2rstr;
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break;
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case A_AHB3RSTR:
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retvalue = s->ahb3rstr;
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break;
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case A_APB1RSTR1:
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retvalue = s->apb1rstr1;
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break;
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case A_APB1RSTR2:
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retvalue = s->apb1rstr2;
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break;
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case A_APB2RSTR:
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retvalue = s->apb2rstr;
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break;
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case A_AHB1ENR:
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retvalue = s->ahb1enr;
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break;
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case A_AHB2ENR:
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retvalue = s->ahb2enr;
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break;
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case A_AHB3ENR:
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retvalue = s->ahb3enr;
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break;
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case A_APB1ENR1:
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retvalue = s->apb1enr1;
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break;
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case A_APB1ENR2:
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retvalue = s->apb1enr2;
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break;
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case A_APB2ENR:
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retvalue = s->apb2enr;
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break;
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case A_AHB1SMENR:
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retvalue = s->ahb1smenr;
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break;
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case A_AHB2SMENR:
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retvalue = s->ahb2smenr;
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break;
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case A_AHB3SMENR:
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retvalue = s->ahb3smenr;
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break;
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case A_APB1SMENR1:
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retvalue = s->apb1smenr1;
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break;
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case A_APB1SMENR2:
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retvalue = s->apb1smenr2;
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break;
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case A_APB2SMENR:
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retvalue = s->apb2smenr;
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break;
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case A_CCIPR:
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retvalue = s->ccipr;
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break;
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case A_BDCR:
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retvalue = s->bdcr;
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break;
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case A_CSR:
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retvalue = s->csr;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
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break;
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}
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trace_stm32l4x5_rcc_read(addr, retvalue);
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return retvalue;
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}
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static void stm32l4x5_rcc_write(void *opaque, hwaddr addr,
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uint64_t val64, unsigned int size)
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{
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Stm32l4x5RccState *s = opaque;
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const uint32_t value = val64;
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trace_stm32l4x5_rcc_write(addr, value);
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switch (addr) {
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case A_CR:
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s->cr = (s->cr & CR_READ_SET_MASK) |
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(value & (CR_READ_SET_MASK | ~CR_READ_ONLY_MASK));
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break;
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case A_ICSCR:
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s->icscr = value & ~ICSCR_READ_ONLY_MASK;
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break;
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case A_CFGR:
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s->cfgr = value & ~CFGR_READ_ONLY_MASK;
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break;
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case A_PLLCFGR:
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s->pllcfgr = value;
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break;
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case A_PLLSAI1CFGR:
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s->pllsai1cfgr = value;
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break;
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case A_PLLSAI2CFGR:
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s->pllsai2cfgr = value;
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break;
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case A_CIER:
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s->cier = value;
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break;
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case A_CIFR:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Write attempt into read-only register (CIFR) 0x%"PRIx32"\n",
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__func__, value);
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break;
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case A_CICR:
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/* Clear interrupt flags by writing a 1 to the CICR register */
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s->cifr &= ~value;
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rcc_update_irq(s);
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break;
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/* Reset behaviors are not implemented */
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case A_AHB1RSTR:
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s->ahb1rstr = value;
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break;
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case A_AHB2RSTR:
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s->ahb2rstr = value;
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break;
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case A_AHB3RSTR:
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s->ahb3rstr = value;
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break;
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case A_APB1RSTR1:
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s->apb1rstr1 = value;
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break;
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case A_APB1RSTR2:
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s->apb1rstr2 = value;
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break;
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case A_APB2RSTR:
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s->apb2rstr = value;
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break;
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case A_AHB1ENR:
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s->ahb1enr = value;
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break;
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case A_AHB2ENR:
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s->ahb2enr = value;
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break;
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case A_AHB3ENR:
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s->ahb3enr = value;
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break;
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case A_APB1ENR1:
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s->apb1enr1 = value;
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break;
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case A_APB1ENR2:
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s->apb1enr2 = value;
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break;
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case A_APB2ENR:
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s->apb2enr = (s->apb2enr & APB2ENR_READ_SET_MASK) | value;
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break;
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/* Behaviors for Sleep and Stop modes are not implemented */
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case A_AHB1SMENR:
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s->ahb1smenr = value;
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break;
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case A_AHB2SMENR:
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s->ahb2smenr = value;
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break;
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case A_AHB3SMENR:
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s->ahb3smenr = value;
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break;
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case A_APB1SMENR1:
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s->apb1smenr1 = value;
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break;
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case A_APB1SMENR2:
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s->apb1smenr2 = value;
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break;
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case A_APB2SMENR:
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s->apb2smenr = value;
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break;
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case A_CCIPR:
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s->ccipr = value;
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break;
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case A_BDCR:
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s->bdcr = value & ~BDCR_READ_ONLY_MASK;
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break;
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case A_CSR:
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s->csr = value & ~CSR_READ_ONLY_MASK;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, addr);
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}
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}
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static const MemoryRegionOps stm32l4x5_rcc_ops = {
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.read = stm32l4x5_rcc_read,
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.write = stm32l4x5_rcc_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.max_access_size = 4,
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.min_access_size = 4,
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.unaligned = false
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},
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.impl = {
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.max_access_size = 4,
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.min_access_size = 4,
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.unaligned = false
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},
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};
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static const ClockPortInitArray stm32l4x5_rcc_clocks = {
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QDEV_CLOCK_IN(Stm32l4x5RccState, hsi16_rc, NULL, 0),
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QDEV_CLOCK_IN(Stm32l4x5RccState, msi_rc, NULL, 0),
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QDEV_CLOCK_IN(Stm32l4x5RccState, hse, NULL, 0),
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QDEV_CLOCK_IN(Stm32l4x5RccState, lsi_rc, NULL, 0),
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QDEV_CLOCK_IN(Stm32l4x5RccState, lse_crystal, NULL, 0),
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QDEV_CLOCK_IN(Stm32l4x5RccState, sai1_extclk, NULL, 0),
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QDEV_CLOCK_IN(Stm32l4x5RccState, sai2_extclk, NULL, 0),
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QDEV_CLOCK_END
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};
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static void stm32l4x5_rcc_init(Object *obj)
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{
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Stm32l4x5RccState *s = STM32L4X5_RCC(obj);
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size_t i;
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sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
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memory_region_init_io(&s->mmio, obj, &stm32l4x5_rcc_ops, s,
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TYPE_STM32L4X5_RCC, 0x400);
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sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
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qdev_init_clocks(DEVICE(s), stm32l4x5_rcc_clocks);
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for (i = 0; i < RCC_NUM_CLOCK_MUX; i++) {
|
|
|
|
object_initialize_child(obj, "clock[*]",
|
|
&s->clock_muxes[i],
|
|
TYPE_RCC_CLOCK_MUX);
|
|
|
|
}
|
|
|
|
s->gnd = clock_new(obj, "gnd");
|
|
}
|
|
|
|
static const VMStateDescription vmstate_stm32l4x5_rcc = {
|
|
.name = TYPE_STM32L4X5_RCC,
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_UINT32(cr, Stm32l4x5RccState),
|
|
VMSTATE_UINT32(icscr, Stm32l4x5RccState),
|
|
VMSTATE_UINT32(cfgr, Stm32l4x5RccState),
|
|
VMSTATE_UINT32(pllcfgr, Stm32l4x5RccState),
|
|
VMSTATE_UINT32(pllsai1cfgr, Stm32l4x5RccState),
|
|
VMSTATE_UINT32(pllsai2cfgr, Stm32l4x5RccState),
|
|
VMSTATE_UINT32(cier, Stm32l4x5RccState),
|
|
VMSTATE_UINT32(cifr, Stm32l4x5RccState),
|
|
VMSTATE_UINT32(ahb1rstr, Stm32l4x5RccState),
|
|
VMSTATE_UINT32(ahb2rstr, Stm32l4x5RccState),
|
|
VMSTATE_UINT32(ahb3rstr, Stm32l4x5RccState),
|
|
VMSTATE_UINT32(apb1rstr1, Stm32l4x5RccState),
|
|
VMSTATE_UINT32(apb1rstr2, Stm32l4x5RccState),
|
|
VMSTATE_UINT32(apb2rstr, Stm32l4x5RccState),
|
|
VMSTATE_UINT32(ahb1enr, Stm32l4x5RccState),
|
|
VMSTATE_UINT32(ahb2enr, Stm32l4x5RccState),
|
|
VMSTATE_UINT32(ahb3enr, Stm32l4x5RccState),
|
|
VMSTATE_UINT32(apb1enr1, Stm32l4x5RccState),
|
|
VMSTATE_UINT32(apb1enr2, Stm32l4x5RccState),
|
|
VMSTATE_UINT32(apb2enr, Stm32l4x5RccState),
|
|
VMSTATE_UINT32(ahb1smenr, Stm32l4x5RccState),
|
|
VMSTATE_UINT32(ahb2smenr, Stm32l4x5RccState),
|
|
VMSTATE_UINT32(ahb3smenr, Stm32l4x5RccState),
|
|
VMSTATE_UINT32(apb1smenr1, Stm32l4x5RccState),
|
|
VMSTATE_UINT32(apb1smenr2, Stm32l4x5RccState),
|
|
VMSTATE_UINT32(apb2smenr, Stm32l4x5RccState),
|
|
VMSTATE_UINT32(ccipr, Stm32l4x5RccState),
|
|
VMSTATE_UINT32(bdcr, Stm32l4x5RccState),
|
|
VMSTATE_UINT32(csr, Stm32l4x5RccState),
|
|
VMSTATE_CLOCK(hsi16_rc, Stm32l4x5RccState),
|
|
VMSTATE_CLOCK(msi_rc, Stm32l4x5RccState),
|
|
VMSTATE_CLOCK(hse, Stm32l4x5RccState),
|
|
VMSTATE_CLOCK(lsi_rc, Stm32l4x5RccState),
|
|
VMSTATE_CLOCK(lse_crystal, Stm32l4x5RccState),
|
|
VMSTATE_CLOCK(sai1_extclk, Stm32l4x5RccState),
|
|
VMSTATE_CLOCK(sai2_extclk, Stm32l4x5RccState),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
|
|
static void stm32l4x5_rcc_realize(DeviceState *dev, Error **errp)
|
|
{
|
|
Stm32l4x5RccState *s = STM32L4X5_RCC(dev);
|
|
size_t i;
|
|
|
|
if (s->hse_frequency < 4000000ULL ||
|
|
s->hse_frequency > 48000000ULL) {
|
|
error_setg(errp,
|
|
"HSE frequency is outside of the allowed [4-48]Mhz range: %" PRIx64 "",
|
|
s->hse_frequency);
|
|
return;
|
|
}
|
|
|
|
for (i = 0; i < RCC_NUM_CLOCK_MUX; i++) {
|
|
RccClockMuxState *clock_mux = &s->clock_muxes[i];
|
|
|
|
if (!qdev_realize(DEVICE(clock_mux), NULL, errp)) {
|
|
return;
|
|
}
|
|
}
|
|
|
|
clock_update_hz(s->msi_rc, MSI_DEFAULT_FRQ);
|
|
clock_update_hz(s->sai1_extclk, s->sai1_extclk_frequency);
|
|
clock_update_hz(s->sai2_extclk, s->sai2_extclk_frequency);
|
|
clock_update(s->gnd, 0);
|
|
|
|
/*
|
|
* Dummy values to make compilation pass.
|
|
* Removed in later commits.
|
|
*/
|
|
clock_mux_set_source(&s->clock_muxes[0], RCC_CLOCK_MUX_SRC_GND);
|
|
clock_mux_set_enable(&s->clock_muxes[0], true);
|
|
clock_mux_set_factor(&s->clock_muxes[0], 1, 1);
|
|
}
|
|
|
|
static Property stm32l4x5_rcc_properties[] = {
|
|
DEFINE_PROP_UINT64("hse_frequency", Stm32l4x5RccState,
|
|
hse_frequency, HSE_DEFAULT_FRQ),
|
|
DEFINE_PROP_UINT64("sai1_extclk_frequency", Stm32l4x5RccState,
|
|
sai1_extclk_frequency, 0),
|
|
DEFINE_PROP_UINT64("sai2_extclk_frequency", Stm32l4x5RccState,
|
|
sai2_extclk_frequency, 0),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static void stm32l4x5_rcc_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
ResettableClass *rc = RESETTABLE_CLASS(klass);
|
|
|
|
|
|
rc->phases.hold = stm32l4x5_rcc_reset_hold;
|
|
device_class_set_props(dc, stm32l4x5_rcc_properties);
|
|
dc->realize = stm32l4x5_rcc_realize;
|
|
dc->vmsd = &vmstate_stm32l4x5_rcc;
|
|
}
|
|
|
|
static const TypeInfo stm32l4x5_rcc_types[] = {
|
|
{
|
|
.name = TYPE_STM32L4X5_RCC,
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(Stm32l4x5RccState),
|
|
.instance_init = stm32l4x5_rcc_init,
|
|
.class_init = stm32l4x5_rcc_class_init,
|
|
}, {
|
|
.name = TYPE_RCC_CLOCK_MUX,
|
|
.parent = TYPE_DEVICE,
|
|
.instance_size = sizeof(RccClockMuxState),
|
|
.instance_init = clock_mux_init,
|
|
.class_init = clock_mux_class_init,
|
|
}
|
|
};
|
|
|
|
DEFINE_TYPES(stm32l4x5_rcc_types)
|