e1b72c55b1
Both 'netduinoplus2' and 'olimex-stm32-h405' machines ignore the CPU type requested by the command line. This might confuse users, since the following will create a machine with a Cortex-M4 CPU: $ qemu-system-aarch64 -M netduinoplus2 -cpu cortex-r5f Set the MachineClass::valid_cpu_types field (introduced in commit c9cf636d48 "machine: Add a valid_cpu_types property"). Remove the now unused MachineClass::default_cpu_type field. We now get: $ qemu-system-aarch64 -M netduinoplus2 -cpu cortex-r5f qemu-system-aarch64: Invalid CPU type: cortex-r5f-arm-cpu The valid types are: cortex-m4-arm-cpu Since the SoC family can only use Cortex-M4 CPUs, hard-code the CPU type name at the SoC level, removing the QOM property entirely. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Gavin Shan <gshan@redhat.com> Message-id: 20231117071704.35040-3-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
74 lines
2.5 KiB
C
74 lines
2.5 KiB
C
/*
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* ST STM32VLDISCOVERY machine
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* Olimex STM32-H405 machine
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*
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* Copyright (c) 2022 Felipe Balbi <balbi@kernel.org>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "hw/boards.h"
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#include "hw/qdev-properties.h"
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#include "hw/qdev-clock.h"
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#include "qemu/error-report.h"
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#include "hw/arm/stm32f405_soc.h"
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#include "hw/arm/boot.h"
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/* olimex-stm32-h405 implementation is derived from netduinoplus2 */
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/* Main SYSCLK frequency in Hz (168MHz) */
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#define SYSCLK_FRQ 168000000ULL
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static void olimex_stm32_h405_init(MachineState *machine)
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{
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DeviceState *dev;
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Clock *sysclk;
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/* This clock doesn't need migration because it is fixed-frequency */
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sysclk = clock_new(OBJECT(machine), "SYSCLK");
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clock_set_hz(sysclk, SYSCLK_FRQ);
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dev = qdev_new(TYPE_STM32F405_SOC);
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qdev_connect_clock_in(dev, "sysclk", sysclk);
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sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
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armv7m_load_kernel(ARM_CPU(first_cpu),
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machine->kernel_filename,
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0, FLASH_SIZE);
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}
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static void olimex_stm32_h405_machine_init(MachineClass *mc)
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{
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static const char * const valid_cpu_types[] = {
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ARM_CPU_TYPE_NAME("cortex-m4"),
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NULL
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};
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mc->desc = "Olimex STM32-H405 (Cortex-M4)";
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mc->init = olimex_stm32_h405_init;
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mc->valid_cpu_types = valid_cpu_types;
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/* SRAM pre-allocated as part of the SoC instantiation */
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mc->default_ram_size = 0;
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}
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DEFINE_MACHINE("olimex-stm32-h405", olimex_stm32_h405_machine_init)
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