e14b5a23d8
Introduce ARMMMUFaultInfo to propagate MMU Fault information across the MMU translation code path. This is in preparation for adding Stage-2 translation. No functional changes. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1445864527-14520-11-git-send-email-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
435 lines
14 KiB
C
435 lines
14 KiB
C
/*
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* QEMU ARM CPU -- internal functions and types
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*
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* Copyright (c) 2014 Linaro Ltd
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see
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* <http://www.gnu.org/licenses/gpl-2.0.html>
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*
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* This header defines functions, types, etc which need to be shared
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* between different source files within target-arm/ but which are
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* private to it and not required by the rest of QEMU.
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*/
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#ifndef TARGET_ARM_INTERNALS_H
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#define TARGET_ARM_INTERNALS_H
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static inline bool excp_is_internal(int excp)
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{
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/* Return true if this exception number represents a QEMU-internal
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* exception that will not be passed to the guest.
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*/
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return excp == EXCP_INTERRUPT
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|| excp == EXCP_HLT
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|| excp == EXCP_DEBUG
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|| excp == EXCP_HALTED
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|| excp == EXCP_EXCEPTION_EXIT
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|| excp == EXCP_KERNEL_TRAP
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|| excp == EXCP_SEMIHOST
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|| excp == EXCP_STREX;
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}
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/* Exception names for debug logging; note that not all of these
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* precisely correspond to architectural exceptions.
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*/
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static const char * const excnames[] = {
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[EXCP_UDEF] = "Undefined Instruction",
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[EXCP_SWI] = "SVC",
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[EXCP_PREFETCH_ABORT] = "Prefetch Abort",
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[EXCP_DATA_ABORT] = "Data Abort",
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[EXCP_IRQ] = "IRQ",
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[EXCP_FIQ] = "FIQ",
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[EXCP_BKPT] = "Breakpoint",
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[EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
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[EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
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[EXCP_STREX] = "QEMU intercept of STREX",
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[EXCP_HVC] = "Hypervisor Call",
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[EXCP_HYP_TRAP] = "Hypervisor Trap",
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[EXCP_SMC] = "Secure Monitor Call",
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[EXCP_VIRQ] = "Virtual IRQ",
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[EXCP_VFIQ] = "Virtual FIQ",
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[EXCP_SEMIHOST] = "Semihosting call",
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};
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static inline void arm_log_exception(int idx)
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{
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if (qemu_loglevel_mask(CPU_LOG_INT)) {
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const char *exc = NULL;
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if (idx >= 0 && idx < ARRAY_SIZE(excnames)) {
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exc = excnames[idx];
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}
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if (!exc) {
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exc = "unknown";
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}
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qemu_log_mask(CPU_LOG_INT, "Taking exception %d [%s]\n", idx, exc);
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}
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}
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/* Scale factor for generic timers, ie number of ns per tick.
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* This gives a 62.5MHz timer.
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*/
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#define GTIMER_SCALE 16
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/*
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* For AArch64, map a given EL to an index in the banked_spsr array.
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* Note that this mapping and the AArch32 mapping defined in bank_number()
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* must agree such that the AArch64<->AArch32 SPSRs have the architecturally
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* mandated mapping between each other.
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*/
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static inline unsigned int aarch64_banked_spsr_index(unsigned int el)
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{
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static const unsigned int map[4] = {
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[1] = 1, /* EL1. */
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[2] = 6, /* EL2. */
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[3] = 7, /* EL3. */
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};
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assert(el >= 1 && el <= 3);
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return map[el];
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}
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int bank_number(int mode);
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void switch_mode(CPUARMState *, int);
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void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu);
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void arm_translate_init(void);
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enum arm_fprounding {
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FPROUNDING_TIEEVEN,
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FPROUNDING_POSINF,
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FPROUNDING_NEGINF,
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FPROUNDING_ZERO,
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FPROUNDING_TIEAWAY,
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FPROUNDING_ODD
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};
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int arm_rmode_to_sf(int rmode);
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static inline void aarch64_save_sp(CPUARMState *env, int el)
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{
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if (env->pstate & PSTATE_SP) {
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env->sp_el[el] = env->xregs[31];
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} else {
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env->sp_el[0] = env->xregs[31];
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}
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}
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static inline void aarch64_restore_sp(CPUARMState *env, int el)
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{
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if (env->pstate & PSTATE_SP) {
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env->xregs[31] = env->sp_el[el];
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} else {
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env->xregs[31] = env->sp_el[0];
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}
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}
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static inline void update_spsel(CPUARMState *env, uint32_t imm)
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{
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unsigned int cur_el = arm_current_el(env);
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/* Update PSTATE SPSel bit; this requires us to update the
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* working stack pointer in xregs[31].
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*/
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if (!((imm ^ env->pstate) & PSTATE_SP)) {
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return;
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}
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aarch64_save_sp(env, cur_el);
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env->pstate = deposit32(env->pstate, 0, 1, imm);
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/* We rely on illegal updates to SPsel from EL0 to get trapped
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* at translation time.
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*/
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assert(cur_el >= 1 && cur_el <= 3);
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aarch64_restore_sp(env, cur_el);
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}
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/*
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* arm_pamax
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* @cpu: ARMCPU
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*
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* Returns the implementation defined bit-width of physical addresses.
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* The ARMv8 reference manuals refer to this as PAMax().
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*/
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static inline unsigned int arm_pamax(ARMCPU *cpu)
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{
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static const unsigned int pamax_map[] = {
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[0] = 32,
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[1] = 36,
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[2] = 40,
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[3] = 42,
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[4] = 44,
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[5] = 48,
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};
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unsigned int parange = extract32(cpu->id_aa64mmfr0, 0, 4);
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/* id_aa64mmfr0 is a read-only register so values outside of the
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* supported mappings can be considered an implementation error. */
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assert(parange < ARRAY_SIZE(pamax_map));
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return pamax_map[parange];
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}
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/* Return true if extended addresses are enabled.
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* This is always the case if our translation regime is 64 bit,
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* but depends on TTBCR.EAE for 32 bit.
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*/
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static inline bool extended_addresses_enabled(CPUARMState *env)
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{
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TCR *tcr = &env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1];
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return arm_el_is_aa64(env, 1) ||
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(arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EAE));
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}
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/* Valid Syndrome Register EC field values */
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enum arm_exception_class {
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EC_UNCATEGORIZED = 0x00,
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EC_WFX_TRAP = 0x01,
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EC_CP15RTTRAP = 0x03,
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EC_CP15RRTTRAP = 0x04,
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EC_CP14RTTRAP = 0x05,
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EC_CP14DTTRAP = 0x06,
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EC_ADVSIMDFPACCESSTRAP = 0x07,
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EC_FPIDTRAP = 0x08,
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EC_CP14RRTTRAP = 0x0c,
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EC_ILLEGALSTATE = 0x0e,
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EC_AA32_SVC = 0x11,
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EC_AA32_HVC = 0x12,
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EC_AA32_SMC = 0x13,
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EC_AA64_SVC = 0x15,
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EC_AA64_HVC = 0x16,
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EC_AA64_SMC = 0x17,
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EC_SYSTEMREGISTERTRAP = 0x18,
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EC_INSNABORT = 0x20,
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EC_INSNABORT_SAME_EL = 0x21,
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EC_PCALIGNMENT = 0x22,
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EC_DATAABORT = 0x24,
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EC_DATAABORT_SAME_EL = 0x25,
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EC_SPALIGNMENT = 0x26,
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EC_AA32_FPTRAP = 0x28,
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EC_AA64_FPTRAP = 0x2c,
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EC_SERROR = 0x2f,
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EC_BREAKPOINT = 0x30,
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EC_BREAKPOINT_SAME_EL = 0x31,
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EC_SOFTWARESTEP = 0x32,
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EC_SOFTWARESTEP_SAME_EL = 0x33,
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EC_WATCHPOINT = 0x34,
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EC_WATCHPOINT_SAME_EL = 0x35,
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EC_AA32_BKPT = 0x38,
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EC_VECTORCATCH = 0x3a,
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EC_AA64_BKPT = 0x3c,
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};
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#define ARM_EL_EC_SHIFT 26
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#define ARM_EL_IL_SHIFT 25
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#define ARM_EL_IL (1 << ARM_EL_IL_SHIFT)
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/* Utility functions for constructing various kinds of syndrome value.
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* Note that in general we follow the AArch64 syndrome values; in a
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* few cases the value in HSR for exceptions taken to AArch32 Hyp
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* mode differs slightly, so if we ever implemented Hyp mode then the
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* syndrome value would need some massaging on exception entry.
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* (One example of this is that AArch64 defaults to IL bit set for
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* exceptions which don't specifically indicate information about the
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* trapping instruction, whereas AArch32 defaults to IL bit clear.)
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*/
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static inline uint32_t syn_uncategorized(void)
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{
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return (EC_UNCATEGORIZED << ARM_EL_EC_SHIFT) | ARM_EL_IL;
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}
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static inline uint32_t syn_aa64_svc(uint32_t imm16)
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{
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return (EC_AA64_SVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
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}
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static inline uint32_t syn_aa64_hvc(uint32_t imm16)
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{
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return (EC_AA64_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
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}
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static inline uint32_t syn_aa64_smc(uint32_t imm16)
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{
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return (EC_AA64_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
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}
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static inline uint32_t syn_aa32_svc(uint32_t imm16, bool is_thumb)
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{
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return (EC_AA32_SVC << ARM_EL_EC_SHIFT) | (imm16 & 0xffff)
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| (is_thumb ? 0 : ARM_EL_IL);
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}
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static inline uint32_t syn_aa32_hvc(uint32_t imm16)
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{
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return (EC_AA32_HVC << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
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}
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static inline uint32_t syn_aa32_smc(void)
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{
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return (EC_AA32_SMC << ARM_EL_EC_SHIFT) | ARM_EL_IL;
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}
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static inline uint32_t syn_aa64_bkpt(uint32_t imm16)
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{
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return (EC_AA64_BKPT << ARM_EL_EC_SHIFT) | ARM_EL_IL | (imm16 & 0xffff);
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}
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static inline uint32_t syn_aa32_bkpt(uint32_t imm16, bool is_thumb)
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{
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return (EC_AA32_BKPT << ARM_EL_EC_SHIFT) | (imm16 & 0xffff)
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| (is_thumb ? 0 : ARM_EL_IL);
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}
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static inline uint32_t syn_aa64_sysregtrap(int op0, int op1, int op2,
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int crn, int crm, int rt,
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int isread)
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{
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return (EC_SYSTEMREGISTERTRAP << ARM_EL_EC_SHIFT) | ARM_EL_IL
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| (op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (rt << 5)
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| (crm << 1) | isread;
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}
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static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int opc2,
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int crn, int crm, int rt, int isread,
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bool is_thumb)
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{
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return (EC_CP14RTTRAP << ARM_EL_EC_SHIFT)
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| (is_thumb ? 0 : ARM_EL_IL)
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| (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14)
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| (crn << 10) | (rt << 5) | (crm << 1) | isread;
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}
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static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int opc2,
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int crn, int crm, int rt, int isread,
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bool is_thumb)
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{
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return (EC_CP15RTTRAP << ARM_EL_EC_SHIFT)
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| (is_thumb ? 0 : ARM_EL_IL)
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| (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14)
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| (crn << 10) | (rt << 5) | (crm << 1) | isread;
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}
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static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int crm,
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int rt, int rt2, int isread,
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bool is_thumb)
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{
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return (EC_CP14RRTTRAP << ARM_EL_EC_SHIFT)
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| (is_thumb ? 0 : ARM_EL_IL)
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| (cv << 24) | (cond << 20) | (opc1 << 16)
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| (rt2 << 10) | (rt << 5) | (crm << 1) | isread;
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}
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static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm,
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int rt, int rt2, int isread,
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bool is_thumb)
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{
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return (EC_CP15RRTTRAP << ARM_EL_EC_SHIFT)
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| (is_thumb ? 0 : ARM_EL_IL)
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| (cv << 24) | (cond << 20) | (opc1 << 16)
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| (rt2 << 10) | (rt << 5) | (crm << 1) | isread;
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}
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static inline uint32_t syn_fp_access_trap(int cv, int cond, bool is_thumb)
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{
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return (EC_ADVSIMDFPACCESSTRAP << ARM_EL_EC_SHIFT)
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| (is_thumb ? 0 : ARM_EL_IL)
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| (cv << 24) | (cond << 20);
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}
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static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc)
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{
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return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
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| (ea << 9) | (s1ptw << 7) | fsc;
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}
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static inline uint32_t syn_data_abort(int same_el, int ea, int cm, int s1ptw,
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int wnr, int fsc)
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{
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return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
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| (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc;
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}
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static inline uint32_t syn_swstep(int same_el, int isv, int ex)
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{
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return (EC_SOFTWARESTEP << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
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| (isv << 24) | (ex << 6) | 0x22;
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}
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static inline uint32_t syn_watchpoint(int same_el, int cm, int wnr)
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{
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return (EC_WATCHPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
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| (cm << 8) | (wnr << 6) | 0x22;
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}
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static inline uint32_t syn_breakpoint(int same_el)
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{
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return (EC_BREAKPOINT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
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| ARM_EL_IL | 0x22;
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}
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static inline uint32_t syn_wfx(int cv, int cond, int ti)
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{
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return (EC_WFX_TRAP << ARM_EL_EC_SHIFT) |
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(cv << 24) | (cond << 20) | ti;
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}
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/* Update a QEMU watchpoint based on the information the guest has set in the
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* DBGWCR<n>_EL1 and DBGWVR<n>_EL1 registers.
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*/
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void hw_watchpoint_update(ARMCPU *cpu, int n);
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/* Update the QEMU watchpoints for every guest watchpoint. This does a
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* complete delete-and-reinstate of the QEMU watchpoint list and so is
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* suitable for use after migration or on reset.
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*/
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void hw_watchpoint_update_all(ARMCPU *cpu);
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/* Update a QEMU breakpoint based on the information the guest has set in the
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* DBGBCR<n>_EL1 and DBGBVR<n>_EL1 registers.
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*/
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void hw_breakpoint_update(ARMCPU *cpu, int n);
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/* Update the QEMU breakpoints for every guest breakpoint. This does a
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* complete delete-and-reinstate of the QEMU breakpoint list and so is
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* suitable for use after migration or on reset.
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*/
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void hw_breakpoint_update_all(ARMCPU *cpu);
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/* Callback function for when a watchpoint or breakpoint triggers. */
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void arm_debug_excp_handler(CPUState *cs);
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#ifdef CONFIG_USER_ONLY
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static inline bool arm_is_psci_call(ARMCPU *cpu, int excp_type)
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{
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return false;
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}
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#else
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/* Return true if the r0/x0 value indicates that this SMC/HVC is a PSCI call. */
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bool arm_is_psci_call(ARMCPU *cpu, int excp_type);
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/* Actually handle a PSCI call */
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void arm_handle_psci_call(ARMCPU *cpu);
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#endif
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/**
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* ARMMMUFaultInfo: Information describing an ARM MMU Fault
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* @s2addr: Address that caused a fault at stage 2
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* @stage2: True if we faulted at stage 2
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* @s1ptw: True if we faulted at stage 2 while doing a stage 1 page-table walk
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*/
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typedef struct ARMMMUFaultInfo ARMMMUFaultInfo;
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struct ARMMMUFaultInfo {
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target_ulong s2addr;
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bool stage2;
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bool s1ptw;
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};
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/* Do a page table walk and add page to TLB if possible */
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bool arm_tlb_fill(CPUState *cpu, vaddr address, int rw, int mmu_idx,
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uint32_t *fsr, ARMMMUFaultInfo *fi);
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#endif
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