9925c8bb81
Using a macro for the PLIC configuration doesn't make the code any easier to read. Instead it makes it harder to figure out what is going on, so let's remove it. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20211022060133.3045020-1-alistair.francis@opensource.wdc.com
95 lines
2.5 KiB
C
95 lines
2.5 KiB
C
/*
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* QEMU RISC-V VirtIO machine interface
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*
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* Copyright (c) 2017 SiFive, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_RISCV_VIRT_H
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#define HW_RISCV_VIRT_H
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#include "hw/riscv/riscv_hart.h"
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#include "hw/sysbus.h"
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#include "hw/block/flash.h"
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#include "qom/object.h"
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#define VIRT_CPUS_MAX 8
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#define VIRT_SOCKETS_MAX 8
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#define TYPE_RISCV_VIRT_MACHINE MACHINE_TYPE_NAME("virt")
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typedef struct RISCVVirtState RISCVVirtState;
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DECLARE_INSTANCE_CHECKER(RISCVVirtState, RISCV_VIRT_MACHINE,
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TYPE_RISCV_VIRT_MACHINE)
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struct RISCVVirtState {
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/*< private >*/
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MachineState parent;
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/*< public >*/
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RISCVHartArrayState soc[VIRT_SOCKETS_MAX];
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DeviceState *plic[VIRT_SOCKETS_MAX];
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PFlashCFI01 *flash[2];
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FWCfgState *fw_cfg;
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int fdt_size;
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bool have_aclint;
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};
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enum {
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VIRT_DEBUG,
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VIRT_MROM,
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VIRT_TEST,
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VIRT_RTC,
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VIRT_CLINT,
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VIRT_ACLINT_SSWI,
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VIRT_PLIC,
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VIRT_UART0,
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VIRT_VIRTIO,
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VIRT_FW_CFG,
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VIRT_FLASH,
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VIRT_DRAM,
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VIRT_PCIE_MMIO,
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VIRT_PCIE_PIO,
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VIRT_PCIE_ECAM
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};
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enum {
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UART0_IRQ = 10,
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RTC_IRQ = 11,
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VIRTIO_IRQ = 1, /* 1 to 8 */
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VIRTIO_COUNT = 8,
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PCIE_IRQ = 0x20, /* 32 to 35 */
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VIRTIO_NDEV = 0x35 /* Arbitrary maximum number of interrupts */
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};
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#define VIRT_PLIC_NUM_SOURCES 127
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#define VIRT_PLIC_NUM_PRIORITIES 7
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#define VIRT_PLIC_PRIORITY_BASE 0x04
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#define VIRT_PLIC_PENDING_BASE 0x1000
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#define VIRT_PLIC_ENABLE_BASE 0x2000
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#define VIRT_PLIC_ENABLE_STRIDE 0x80
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#define VIRT_PLIC_CONTEXT_BASE 0x200000
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#define VIRT_PLIC_CONTEXT_STRIDE 0x1000
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#define VIRT_PLIC_SIZE(__num_context) \
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(VIRT_PLIC_CONTEXT_BASE + (__num_context) * VIRT_PLIC_CONTEXT_STRIDE)
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#define FDT_PCI_ADDR_CELLS 3
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#define FDT_PCI_INT_CELLS 1
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#define FDT_PLIC_ADDR_CELLS 0
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#define FDT_PLIC_INT_CELLS 1
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#define FDT_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + 1 + \
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FDT_PLIC_ADDR_CELLS + FDT_PLIC_INT_CELLS)
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#endif
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