2eaeb7d593
Allow TLB to be tagged with VMID. If stage-1 is only supported, VMID is set to -1 and ignored from STE and CMD_TLBI_NH* cmds. Update smmu_iotlb_insert trace event to have vmid. Signed-off-by: Mostafa Saleh <smostafa@google.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Eric Auger <eric.auger@redhat.com> Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org> Message-id: 20230516203327.2051088-8-smostafa@google.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
150 lines
4.4 KiB
C
150 lines
4.4 KiB
C
/*
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* ARM SMMU support - Internal API
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*
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* Copyright (c) 2017 Red Hat, Inc.
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* Copyright (C) 2014-2016 Broadcom Corporation
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* Written by Prem Mallappa, Eric Auger
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_ARM_SMMU_INTERNAL_H
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#define HW_ARM_SMMU_INTERNAL_H
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#define TBI0(tbi) ((tbi) & 0x1)
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#define TBI1(tbi) ((tbi) & 0x2 >> 1)
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/* PTE Manipulation */
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#define ARM_LPAE_PTE_TYPE_SHIFT 0
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#define ARM_LPAE_PTE_TYPE_MASK 0x3
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#define ARM_LPAE_PTE_TYPE_BLOCK 1
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#define ARM_LPAE_PTE_TYPE_TABLE 3
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#define ARM_LPAE_L3_PTE_TYPE_RESERVED 1
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#define ARM_LPAE_L3_PTE_TYPE_PAGE 3
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#define ARM_LPAE_PTE_VALID (1 << 0)
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#define PTE_ADDRESS(pte, shift) \
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(extract64(pte, shift, 47 - shift + 1) << shift)
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#define is_invalid_pte(pte) (!(pte & ARM_LPAE_PTE_VALID))
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#define is_reserved_pte(pte, level) \
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((level == 3) && \
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((pte & ARM_LPAE_PTE_TYPE_MASK) == ARM_LPAE_L3_PTE_TYPE_RESERVED))
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#define is_block_pte(pte, level) \
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((level < 3) && \
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((pte & ARM_LPAE_PTE_TYPE_MASK) == ARM_LPAE_PTE_TYPE_BLOCK))
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#define is_table_pte(pte, level) \
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((level < 3) && \
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((pte & ARM_LPAE_PTE_TYPE_MASK) == ARM_LPAE_PTE_TYPE_TABLE))
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#define is_page_pte(pte, level) \
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((level == 3) && \
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((pte & ARM_LPAE_PTE_TYPE_MASK) == ARM_LPAE_L3_PTE_TYPE_PAGE))
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/* access permissions */
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#define PTE_AP(pte) \
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(extract64(pte, 6, 2))
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#define PTE_APTABLE(pte) \
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(extract64(pte, 61, 2))
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#define PTE_AF(pte) \
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(extract64(pte, 10, 1))
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/*
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* TODO: At the moment all transactions are considered as privileged (EL1)
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* as IOMMU translation callback does not pass user/priv attributes.
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*/
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#define is_permission_fault(ap, perm) \
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(((perm) & IOMMU_WO) && ((ap) & 0x2))
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#define is_permission_fault_s2(s2ap, perm) \
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(!(((s2ap) & (perm)) == (perm)))
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#define PTE_AP_TO_PERM(ap) \
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(IOMMU_ACCESS_FLAG(true, !((ap) & 0x2)))
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/* Level Indexing */
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static inline int level_shift(int level, int granule_sz)
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{
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return granule_sz + (3 - level) * (granule_sz - 3);
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}
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static inline uint64_t level_page_mask(int level, int granule_sz)
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{
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return ~(MAKE_64BIT_MASK(0, level_shift(level, granule_sz)));
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}
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static inline
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uint64_t iova_level_offset(uint64_t iova, int inputsize,
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int level, int gsz)
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{
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return ((iova & MAKE_64BIT_MASK(0, inputsize)) >> level_shift(level, gsz)) &
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MAKE_64BIT_MASK(0, gsz - 3);
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}
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/* FEAT_LPA2 and FEAT_TTST are not implemented. */
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static inline int get_start_level(int sl0 , int granule_sz)
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{
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/* ARM DDI0487I.a: Table D8-12. */
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if (granule_sz == 12) {
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return 2 - sl0;
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}
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/* ARM DDI0487I.a: Table D8-22 and Table D8-31. */
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return 3 - sl0;
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}
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/*
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* Index in a concatenated first level stage-2 page table.
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* ARM DDI0487I.a: D8.2.2 Concatenated translation tables.
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*/
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static inline int pgd_concat_idx(int start_level, int granule_sz,
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dma_addr_t ipa)
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{
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uint64_t ret;
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/*
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* Get the number of bits handled by next levels, then any extra bits in
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* the address should index the concatenated tables. This relation can be
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* deduced from tables in ARM DDI0487I.a: D8.2.7-9
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*/
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int shift = level_shift(start_level - 1, granule_sz);
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ret = ipa >> shift;
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return ret;
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}
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#define SMMU_IOTLB_ASID(key) ((key).asid)
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#define SMMU_IOTLB_VMID(key) ((key).vmid)
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typedef struct SMMUIOTLBPageInvInfo {
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int asid;
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int vmid;
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uint64_t iova;
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uint64_t mask;
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} SMMUIOTLBPageInvInfo;
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typedef struct SMMUSIDRange {
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uint32_t start;
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uint32_t end;
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} SMMUSIDRange;
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#endif
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