Michael Clark db9f3fd69d
RISC-V: Add misa to DisasContext
gen methods should access state from DisasContext. Add misa
field to the DisasContext struct and remove CPURISCVState
argument from all gen methods.

Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-02-11 15:56:22 -08:00
..
2019-02-05 19:39:22 +00:00
2018-06-04 11:28:31 +01:00
2018-06-04 11:28:31 +01:00
2019-02-11 15:56:22 -08:00
2018-08-20 00:11:06 +02:00