Remove the Niagara stub implementation from sun4u.c and add a machine, compatible with Legion simulator from the OpenSPARC T1 project. The machine uses the firmware supplied with the OpenSPARC T1 project, http://download.oracle.com/technetwork/systems/opensparc/OpenSPARCT1_Arch.1.5.tar.bz2 in the directory S10image/, and is able to boot the supplied Solaris 10 image. Note that for compatibility with the naming conventions for SPARC machines the new machine name is lowercase niagara. Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net>
		
			
				
	
	
		
			178 lines
		
	
	
		
			6.4 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			178 lines
		
	
	
		
			6.4 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
/*
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 * QEMU Sun4v/Niagara System Emulator
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 *
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 * Copyright (c) 2016 Artyom Tarasenko
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu-common.h"
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#include "cpu.h"
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#include "hw/hw.h"
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#include "hw/boards.h"
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#include "hw/char/serial.h"
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#include "hw/empty_slot.h"
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#include "hw/loader.h"
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#include "hw/sparc/sparc64.h"
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#include "hw/timer/sun4v-rtc.h"
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#include "exec/address-spaces.h"
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#include "sysemu/block-backend.h"
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typedef struct NiagaraBoardState {
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    MemoryRegion hv_ram;
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    MemoryRegion partition_ram;
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    MemoryRegion nvram;
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    MemoryRegion md_rom;
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    MemoryRegion hv_rom;
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    MemoryRegion vdisk_ram;
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    MemoryRegion prom;
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} NiagaraBoardState;
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#define NIAGARA_HV_RAM_BASE 0x100000ULL
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#define NIAGARA_HV_RAM_SIZE 0x3f00000ULL /* 63 MiB */
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#define NIAGARA_PARTITION_RAM_BASE 0x80000000ULL
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#define NIAGARA_UART_BASE   0x1f10000000ULL
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#define NIAGARA_NVRAM_BASE  0x1f11000000ULL
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#define NIAGARA_NVRAM_SIZE  0x2000
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#define NIAGARA_MD_ROM_BASE 0x1f12000000ULL
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#define NIAGARA_MD_ROM_SIZE 0x2000
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#define NIAGARA_HV_ROM_BASE 0x1f12080000ULL
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#define NIAGARA_HV_ROM_SIZE 0x2000
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#define NIAGARA_IOBBASE     0x9800000000ULL
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#define NIAGARA_IOBSIZE     0x0100000000ULL
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#define NIAGARA_VDISK_BASE  0x1f40000000ULL
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#define NIAGARA_RTC_BASE    0xfff0c1fff8ULL
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#define NIAGARA_UART_BASE   0x1f10000000ULL
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/* Firmware layout
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 *
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 * |------------------|
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 * |   openboot.bin   |
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 * |------------------| PROM_ADDR + OBP_OFFSET
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 * |      q.bin       |
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 * |------------------| PROM_ADDR + Q_OFFSET
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 * |     reset.bin    |
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 * |------------------| PROM_ADDR
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 */
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#define NIAGARA_PROM_BASE   0xfff0000000ULL
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#define NIAGARA_Q_OFFSET    0x10000ULL
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#define NIAGARA_OBP_OFFSET  0x80000ULL
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#define PROM_SIZE_MAX       (4 * 1024 * 1024)
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/* Niagara hardware initialisation */
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static void niagara_init(MachineState *machine)
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{
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    NiagaraBoardState *s = g_new(NiagaraBoardState, 1);
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    DriveInfo *dinfo = drive_get_next(IF_PFLASH);
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    MemoryRegion *sysmem = get_system_memory();
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    /* init CPUs */
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    sparc64_cpu_devinit(machine->cpu_model, "Sun UltraSparc T1",
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                        NIAGARA_PROM_BASE);
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    /* set up devices */
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    memory_region_allocate_system_memory(&s->hv_ram, NULL, "sun4v-hv.ram",
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                                         NIAGARA_HV_RAM_SIZE);
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    memory_region_add_subregion(sysmem, NIAGARA_HV_RAM_BASE, &s->hv_ram);
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    memory_region_allocate_system_memory(&s->partition_ram, NULL,
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                                         "sun4v-partition.ram",
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                                         machine->ram_size);
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    memory_region_add_subregion(sysmem, NIAGARA_PARTITION_RAM_BASE,
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                                &s->partition_ram);
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    memory_region_allocate_system_memory(&s->nvram, NULL,
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                                         "sun4v.nvram", NIAGARA_NVRAM_SIZE);
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    memory_region_add_subregion(sysmem, NIAGARA_NVRAM_BASE, &s->nvram);
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    memory_region_allocate_system_memory(&s->md_rom, NULL,
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                                         "sun4v-md.rom", NIAGARA_MD_ROM_SIZE);
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    memory_region_add_subregion(sysmem, NIAGARA_MD_ROM_BASE, &s->md_rom);
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    memory_region_allocate_system_memory(&s->hv_rom, NULL,
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                                         "sun4v-hv.rom", NIAGARA_HV_ROM_SIZE);
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    memory_region_add_subregion(sysmem, NIAGARA_HV_ROM_BASE, &s->hv_rom);
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    memory_region_allocate_system_memory(&s->prom, NULL,
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                                         "sun4v.prom", PROM_SIZE_MAX);
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    memory_region_add_subregion(sysmem, NIAGARA_PROM_BASE, &s->prom);
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    rom_add_file_fixed("nvram1", NIAGARA_NVRAM_BASE, -1);
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    rom_add_file_fixed("1up-md.bin", NIAGARA_MD_ROM_BASE, -1);
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    rom_add_file_fixed("1up-hv.bin", NIAGARA_HV_ROM_BASE, -1);
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    rom_add_file_fixed("reset.bin", NIAGARA_PROM_BASE, -1);
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    rom_add_file_fixed("q.bin", NIAGARA_PROM_BASE + NIAGARA_Q_OFFSET, -1);
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    rom_add_file_fixed("openboot.bin", NIAGARA_PROM_BASE + NIAGARA_OBP_OFFSET,
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                       -1);
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    /* the virtual ramdisk is kind of initrd, but it resides
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       outside of the partition RAM */
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    if (dinfo) {
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        BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
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        int size = blk_getlength(blk);
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        if (size > 0) {
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            memory_region_allocate_system_memory(&s->vdisk_ram, NULL,
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                                                 "sun4v_vdisk.ram", size);
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            memory_region_add_subregion(get_system_memory(),
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                                        NIAGARA_VDISK_BASE, &s->vdisk_ram);
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            dinfo->is_default = 1;
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            rom_add_file_fixed(blk_bs(blk)->filename, NIAGARA_VDISK_BASE, -1);
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        } else {
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            fprintf(stderr, "qemu: could not load ram disk '%s'\n",
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                    blk_bs(blk)->filename);
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            exit(1);
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        }
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    }
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    serial_mm_init(sysmem, NIAGARA_UART_BASE, 0, NULL, 115200,
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                   serial_hds[0], DEVICE_BIG_ENDIAN);
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    empty_slot_init(NIAGARA_IOBBASE, NIAGARA_IOBSIZE);
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    sun4v_rtc_init(NIAGARA_RTC_BASE);
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}
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static void niagara_class_init(ObjectClass *oc, void *data)
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{
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    MachineClass *mc = MACHINE_CLASS(oc);
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    mc->desc = "Sun4v platform, Niagara";
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    mc->init = niagara_init;
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    mc->max_cpus = 1; /* XXX for now */
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    mc->default_boot_order = "c";
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}
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static const TypeInfo niagara_type = {
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    .name = MACHINE_TYPE_NAME("niagara"),
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    .parent = TYPE_MACHINE,
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    .class_init = niagara_class_init,
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};
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static void niagara_register_types(void)
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{
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    type_register_static(&niagara_type);
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}
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type_init(niagara_register_types)
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