4e8fb53c0b
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20211022060133.3045020-3-alistair.francis@opensource.wdc.com
169 lines
4.2 KiB
C
169 lines
4.2 KiB
C
/*
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* SiFive U series machine interface
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*
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* Copyright (c) 2017 SiFive, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_SIFIVE_U_H
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#define HW_SIFIVE_U_H
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#include "hw/dma/sifive_pdma.h"
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#include "hw/net/cadence_gem.h"
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#include "hw/riscv/riscv_hart.h"
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#include "hw/riscv/sifive_cpu.h"
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#include "hw/gpio/sifive_gpio.h"
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#include "hw/misc/sifive_u_otp.h"
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#include "hw/misc/sifive_u_prci.h"
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#include "hw/ssi/sifive_spi.h"
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#include "hw/timer/sifive_pwm.h"
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#define TYPE_RISCV_U_SOC "riscv.sifive.u.soc"
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#define RISCV_U_SOC(obj) \
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OBJECT_CHECK(SiFiveUSoCState, (obj), TYPE_RISCV_U_SOC)
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typedef struct SiFiveUSoCState {
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/*< private >*/
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DeviceState parent_obj;
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/*< public >*/
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CPUClusterState e_cluster;
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CPUClusterState u_cluster;
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RISCVHartArrayState e_cpus;
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RISCVHartArrayState u_cpus;
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DeviceState *plic;
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SiFiveUPRCIState prci;
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SIFIVEGPIOState gpio;
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SiFiveUOTPState otp;
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SiFivePDMAState dma;
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SiFiveSPIState spi0;
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SiFiveSPIState spi2;
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CadenceGEMState gem;
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SiFivePwmState pwm[2];
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uint32_t serial;
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char *cpu_type;
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} SiFiveUSoCState;
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#define TYPE_RISCV_U_MACHINE MACHINE_TYPE_NAME("sifive_u")
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#define RISCV_U_MACHINE(obj) \
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OBJECT_CHECK(SiFiveUState, (obj), TYPE_RISCV_U_MACHINE)
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typedef struct SiFiveUState {
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/*< private >*/
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MachineState parent_obj;
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/*< public >*/
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SiFiveUSoCState soc;
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void *fdt;
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int fdt_size;
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bool start_in_flash;
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uint32_t msel;
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uint32_t serial;
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} SiFiveUState;
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enum {
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SIFIVE_U_DEV_DEBUG,
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SIFIVE_U_DEV_MROM,
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SIFIVE_U_DEV_CLINT,
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SIFIVE_U_DEV_L2CC,
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SIFIVE_U_DEV_PDMA,
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SIFIVE_U_DEV_L2LIM,
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SIFIVE_U_DEV_PLIC,
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SIFIVE_U_DEV_PRCI,
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SIFIVE_U_DEV_UART0,
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SIFIVE_U_DEV_UART1,
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SIFIVE_U_DEV_GPIO,
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SIFIVE_U_DEV_QSPI0,
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SIFIVE_U_DEV_QSPI2,
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SIFIVE_U_DEV_OTP,
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SIFIVE_U_DEV_DMC,
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SIFIVE_U_DEV_FLASH0,
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SIFIVE_U_DEV_DRAM,
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SIFIVE_U_DEV_GEM,
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SIFIVE_U_DEV_GEM_MGMT,
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SIFIVE_U_DEV_PWM0,
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SIFIVE_U_DEV_PWM1
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};
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enum {
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SIFIVE_U_L2CC_IRQ0 = 1,
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SIFIVE_U_L2CC_IRQ1 = 2,
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SIFIVE_U_L2CC_IRQ2 = 3,
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SIFIVE_U_UART0_IRQ = 4,
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SIFIVE_U_UART1_IRQ = 5,
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SIFIVE_U_QSPI2_IRQ = 6,
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SIFIVE_U_GPIO_IRQ0 = 7,
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SIFIVE_U_GPIO_IRQ1 = 8,
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SIFIVE_U_GPIO_IRQ2 = 9,
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SIFIVE_U_GPIO_IRQ3 = 10,
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SIFIVE_U_GPIO_IRQ4 = 11,
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SIFIVE_U_GPIO_IRQ5 = 12,
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SIFIVE_U_GPIO_IRQ6 = 13,
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SIFIVE_U_GPIO_IRQ7 = 14,
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SIFIVE_U_GPIO_IRQ8 = 15,
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SIFIVE_U_GPIO_IRQ9 = 16,
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SIFIVE_U_GPIO_IRQ10 = 17,
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SIFIVE_U_GPIO_IRQ11 = 18,
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SIFIVE_U_GPIO_IRQ12 = 19,
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SIFIVE_U_GPIO_IRQ13 = 20,
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SIFIVE_U_GPIO_IRQ14 = 21,
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SIFIVE_U_GPIO_IRQ15 = 22,
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SIFIVE_U_PDMA_IRQ0 = 23,
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SIFIVE_U_PDMA_IRQ1 = 24,
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SIFIVE_U_PDMA_IRQ2 = 25,
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SIFIVE_U_PDMA_IRQ3 = 26,
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SIFIVE_U_PDMA_IRQ4 = 27,
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SIFIVE_U_PDMA_IRQ5 = 28,
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SIFIVE_U_PDMA_IRQ6 = 29,
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SIFIVE_U_PDMA_IRQ7 = 30,
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SIFIVE_U_PWM0_IRQ0 = 42,
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SIFIVE_U_PWM0_IRQ1 = 43,
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SIFIVE_U_PWM0_IRQ2 = 44,
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SIFIVE_U_PWM0_IRQ3 = 45,
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SIFIVE_U_PWM1_IRQ0 = 46,
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SIFIVE_U_PWM1_IRQ1 = 47,
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SIFIVE_U_PWM1_IRQ2 = 48,
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SIFIVE_U_PWM1_IRQ3 = 49,
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SIFIVE_U_QSPI0_IRQ = 51,
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SIFIVE_U_GEM_IRQ = 53
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};
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enum {
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SIFIVE_U_HFCLK_FREQ = 33333333,
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SIFIVE_U_RTCCLK_FREQ = 1000000
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};
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enum {
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MSEL_MEMMAP_QSPI0_FLASH = 1,
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MSEL_L2LIM_QSPI0_FLASH = 6,
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MSEL_L2LIM_QSPI2_SD = 11
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};
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#define SIFIVE_U_MANAGEMENT_CPU_COUNT 1
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#define SIFIVE_U_COMPUTE_CPU_COUNT 4
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#define SIFIVE_U_PLIC_NUM_SOURCES 54
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#define SIFIVE_U_PLIC_NUM_PRIORITIES 7
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#define SIFIVE_U_PLIC_PRIORITY_BASE 0x04
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#define SIFIVE_U_PLIC_PENDING_BASE 0x1000
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#define SIFIVE_U_PLIC_ENABLE_BASE 0x2000
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#define SIFIVE_U_PLIC_ENABLE_STRIDE 0x80
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#define SIFIVE_U_PLIC_CONTEXT_BASE 0x200000
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#define SIFIVE_U_PLIC_CONTEXT_STRIDE 0x1000
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#endif
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