d18b065286
The patch below fixes a bug in the VSX_CVT_FP_TO_INT and VSX_CVT_FP_TO_INT2
macros in target/ppc/fpu_helper.c where a non-NaN floating point value from the
source vector is incorrectly converted to 0, 0x80000000, or 0x8000000000000000
instead of the expected value if a preceding source floating point value from
the same source vector was a NaN.
The bug in the VSX_CVT_FP_TO_INT and VSX_CVT_FP_TO_INT2 macros in
target/ppc/fpu_helper.c was introduced with commit c3f24257e3c0.
This patch also adds a new vsx_f2i_nan test in tests/tcg/ppc64 that checks that
the VSX xvcvspsxws, xvcvspuxws, xvcvspsxds, xvcvspuxds, xvcvdpsxws, xvcvdpuxws,
xvcvdpsxds, and xvcvdpuxds instructions correctly convert non-NaN floating point
values to integer values if the source vector contains NaN floating point values.
Fixes: c3f24257e3c0 ("target/ppc: Clear fpstatus flags on helpers missing it")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1941
Signed-off-by: John Platts <john_platts@hotmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
54 lines
1.3 KiB
Makefile
54 lines
1.3 KiB
Makefile
# -*- Mode: makefile -*-
|
|
#
|
|
# ppc64 specific tweaks
|
|
|
|
VPATH += $(SRC_PATH)/tests/tcg/ppc64
|
|
|
|
config-cc.mak: Makefile
|
|
$(quiet-@)( \
|
|
$(call cc-option,-mpower8-vector, CROSS_CC_HAS_POWER8_VECTOR); \
|
|
$(call cc-option,-mpower10, CROSS_CC_HAS_POWER10)) 3> config-cc.mak
|
|
|
|
-include config-cc.mak
|
|
|
|
ifneq ($(CROSS_CC_HAS_POWER8_VECTOR),)
|
|
PPC64_TESTS=bcdsub non_signalling_xscv
|
|
endif
|
|
$(PPC64_TESTS): CFLAGS += -mpower8-vector
|
|
|
|
ifneq ($(CROSS_CC_HAS_POWER8_VECTOR),)
|
|
PPC64_TESTS += vsx_f2i_nan
|
|
endif
|
|
vsx_f2i_nan: CFLAGS += -mpower8-vector -I$(SRC_PATH)/include
|
|
|
|
PPC64_TESTS += mtfsf
|
|
PPC64_TESTS += mffsce
|
|
|
|
ifneq ($(CROSS_CC_HAS_POWER10),)
|
|
PPC64_TESTS += byte_reverse sha512-vector vector
|
|
endif
|
|
byte_reverse: CFLAGS += -mcpu=power10
|
|
run-byte_reverse: QEMU_OPTS+=-cpu POWER10
|
|
|
|
sha512-vector: CFLAGS +=-mcpu=power10 -O3
|
|
sha512-vector: sha512.c
|
|
$(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS)
|
|
|
|
run-sha512-vector: QEMU_OPTS+=-cpu POWER10
|
|
|
|
vector: CFLAGS += -mcpu=power10 -I$(SRC_PATH)/include
|
|
run-vector: QEMU_OPTS += -cpu POWER10
|
|
|
|
PPC64_TESTS += signal_save_restore_xer
|
|
PPC64_TESTS += xxspltw
|
|
PPC64_TESTS += test-aes
|
|
|
|
ifneq ($(GDB),)
|
|
# Skip for now until vsx registers sorted out
|
|
run-gdbstub-registers:
|
|
$(call skip-test, $<, "BROKEN reading VSX registers")
|
|
endif
|
|
|
|
|
|
TESTS += $(PPC64_TESTS)
|