42b3a4b7cc
Removes a whole lot of unnecessary boilerplate code. Machines don't need to be objects. The expansion of the SOC object model for the RISC-V machines will happen in the future as SiFive plans to add their FE310 and FU540 SOCs to QEMU. However, it seems that this present boilerplate is complete unnecessary. Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
84 lines
2.4 KiB
C
84 lines
2.4 KiB
C
/*
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* QEMU RISCV Hart Array
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*
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* Copyright (c) 2017 SiFive, Inc.
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*
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* Holds the state of a heterogenous array of RISC-V harts
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "hw/sysbus.h"
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#include "target/riscv/cpu.h"
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#include "hw/riscv/riscv_hart.h"
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static Property riscv_harts_props[] = {
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DEFINE_PROP_UINT32("num-harts", RISCVHartArrayState, num_harts, 1),
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DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void riscv_harts_cpu_reset(void *opaque)
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{
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RISCVCPU *cpu = opaque;
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cpu_reset(CPU(cpu));
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}
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static void riscv_harts_realize(DeviceState *dev, Error **errp)
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{
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RISCVHartArrayState *s = RISCV_HART_ARRAY(dev);
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Error *err = NULL;
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int n;
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s->harts = g_new0(RISCVCPU, s->num_harts);
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for (n = 0; n < s->num_harts; n++) {
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object_initialize(&s->harts[n], sizeof(RISCVCPU), s->cpu_type);
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s->harts[n].env.mhartid = n;
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object_property_add_child(OBJECT(s), "harts[*]", OBJECT(&s->harts[n]),
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&error_abort);
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qemu_register_reset(riscv_harts_cpu_reset, &s->harts[n]);
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object_property_set_bool(OBJECT(&s->harts[n]), true,
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"realized", &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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}
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}
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static void riscv_harts_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->props = riscv_harts_props;
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dc->realize = riscv_harts_realize;
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}
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static const TypeInfo riscv_harts_info = {
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.name = TYPE_RISCV_HART_ARRAY,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(RISCVHartArrayState),
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.class_init = riscv_harts_class_init,
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};
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static void riscv_harts_register_types(void)
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{
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type_register_static(&riscv_harts_info);
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}
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type_init(riscv_harts_register_types)
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