319 lines
11 KiB
C
319 lines
11 KiB
C
/*
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* Xilinx Zynq Baseboard System emulation.
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*
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* Copyright (c) 2010 Xilinx.
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* Copyright (c) 2012 Peter A.G. Crosthwaite (peter.croshtwaite@petalogix.com)
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* Copyright (c) 2012 Petalogix Pty Ltd.
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* Written by Haibing Ma
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu-common.h"
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#include "cpu.h"
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#include "hw/sysbus.h"
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#include "hw/arm/arm.h"
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#include "net/net.h"
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#include "exec/address-spaces.h"
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#include "sysemu/sysemu.h"
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#include "hw/boards.h"
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#include "hw/block/flash.h"
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#include "sysemu/block-backend.h"
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#include "hw/loader.h"
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#include "hw/misc/zynq-xadc.h"
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#include "hw/ssi/ssi.h"
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#include "qemu/error-report.h"
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#include "hw/sd/sd.h"
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#define NUM_SPI_FLASHES 4
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#define NUM_QSPI_FLASHES 2
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#define NUM_QSPI_BUSSES 2
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#define FLASH_SIZE (64 * 1024 * 1024)
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#define FLASH_SECTOR_SIZE (128 * 1024)
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#define IRQ_OFFSET 32 /* pic interrupts start from index 32 */
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#define MPCORE_PERIPHBASE 0xF8F00000
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#define ZYNQ_BOARD_MIDR 0x413FC090
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static const int dma_irqs[8] = {
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46, 47, 48, 49, 72, 73, 74, 75
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};
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#define BOARD_SETUP_ADDR 0x100
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#define SLCR_LOCK_OFFSET 0x004
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#define SLCR_UNLOCK_OFFSET 0x008
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#define SLCR_ARM_PLL_OFFSET 0x100
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#define SLCR_XILINX_UNLOCK_KEY 0xdf0d
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#define SLCR_XILINX_LOCK_KEY 0x767b
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#define ARMV7_IMM16(x) (extract32((x), 0, 12) | \
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extract32((x), 12, 4) << 16)
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/* Write immediate val to address r0 + addr. r0 should contain base offset
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* of the SLCR block. Clobbers r1.
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*/
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#define SLCR_WRITE(addr, val) \
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0xe3001000 + ARMV7_IMM16(extract32((val), 0, 16)), /* movw r1 ... */ \
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0xe3401000 + ARMV7_IMM16(extract32((val), 16, 16)), /* movt r1 ... */ \
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0xe5801000 + (addr)
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static void zynq_write_board_setup(ARMCPU *cpu,
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const struct arm_boot_info *info)
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{
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int n;
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uint32_t board_setup_blob[] = {
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0xe3a004f8, /* mov r0, #0xf8000000 */
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SLCR_WRITE(SLCR_UNLOCK_OFFSET, SLCR_XILINX_UNLOCK_KEY),
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SLCR_WRITE(SLCR_ARM_PLL_OFFSET, 0x00014008),
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SLCR_WRITE(SLCR_LOCK_OFFSET, SLCR_XILINX_LOCK_KEY),
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0xe12fff1e, /* bx lr */
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};
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for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) {
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board_setup_blob[n] = tswap32(board_setup_blob[n]);
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}
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rom_add_blob_fixed("board-setup", board_setup_blob,
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sizeof(board_setup_blob), BOARD_SETUP_ADDR);
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}
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static struct arm_boot_info zynq_binfo = {};
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static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq)
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{
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DeviceState *dev;
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SysBusDevice *s;
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dev = qdev_create(NULL, "cadence_gem");
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if (nd->used) {
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qemu_check_nic_model(nd, "cadence_gem");
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qdev_set_nic_properties(dev, nd);
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}
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qdev_init_nofail(dev);
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s = SYS_BUS_DEVICE(dev);
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sysbus_mmio_map(s, 0, base);
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sysbus_connect_irq(s, 0, irq);
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}
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static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq,
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bool is_qspi)
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{
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DeviceState *dev;
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SysBusDevice *busdev;
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SSIBus *spi;
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DeviceState *flash_dev;
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int i, j;
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int num_busses = is_qspi ? NUM_QSPI_BUSSES : 1;
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int num_ss = is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES;
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dev = qdev_create(NULL, is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi");
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qdev_prop_set_uint8(dev, "num-txrx-bytes", is_qspi ? 4 : 1);
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qdev_prop_set_uint8(dev, "num-ss-bits", num_ss);
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qdev_prop_set_uint8(dev, "num-busses", num_busses);
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qdev_init_nofail(dev);
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busdev = SYS_BUS_DEVICE(dev);
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sysbus_mmio_map(busdev, 0, base_addr);
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if (is_qspi) {
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sysbus_mmio_map(busdev, 1, 0xFC000000);
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}
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sysbus_connect_irq(busdev, 0, irq);
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for (i = 0; i < num_busses; ++i) {
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char bus_name[16];
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qemu_irq cs_line;
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snprintf(bus_name, 16, "spi%d", i);
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spi = (SSIBus *)qdev_get_child_bus(dev, bus_name);
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for (j = 0; j < num_ss; ++j) {
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flash_dev = ssi_create_slave(spi, "n25q128");
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cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0);
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sysbus_connect_irq(busdev, i * num_ss + j + 1, cs_line);
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}
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}
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}
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static void zynq_init(MachineState *machine)
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{
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ram_addr_t ram_size = machine->ram_size;
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const char *cpu_model = machine->cpu_model;
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const char *kernel_filename = machine->kernel_filename;
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const char *kernel_cmdline = machine->kernel_cmdline;
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const char *initrd_filename = machine->initrd_filename;
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ObjectClass *cpu_oc;
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ARMCPU *cpu;
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MemoryRegion *address_space_mem = get_system_memory();
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MemoryRegion *ext_ram = g_new(MemoryRegion, 1);
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MemoryRegion *ocm_ram = g_new(MemoryRegion, 1);
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DeviceState *dev, *carddev;
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SysBusDevice *busdev;
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DriveInfo *di;
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BlockBackend *blk;
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qemu_irq pic[64];
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int n;
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if (!cpu_model) {
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cpu_model = "cortex-a9";
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}
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cpu_oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
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cpu = ARM_CPU(object_new(object_class_get_name(cpu_oc)));
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/* By default A9 CPUs have EL3 enabled. This board does not
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* currently support EL3 so the CPU EL3 property is disabled before
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* realization.
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*/
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if (object_property_find(OBJECT(cpu), "has_el3", NULL)) {
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object_property_set_bool(OBJECT(cpu), false, "has_el3", &error_fatal);
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}
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object_property_set_int(OBJECT(cpu), ZYNQ_BOARD_MIDR, "midr",
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&error_fatal);
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object_property_set_int(OBJECT(cpu), MPCORE_PERIPHBASE, "reset-cbar",
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&error_fatal);
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object_property_set_bool(OBJECT(cpu), true, "realized", &error_fatal);
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/* max 2GB ram */
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if (ram_size > 0x80000000) {
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ram_size = 0x80000000;
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}
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/* DDR remapped to address zero. */
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memory_region_allocate_system_memory(ext_ram, NULL, "zynq.ext_ram",
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ram_size);
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memory_region_add_subregion(address_space_mem, 0, ext_ram);
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/* 256K of on-chip memory */
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memory_region_init_ram(ocm_ram, NULL, "zynq.ocm_ram", 256 << 10,
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&error_fatal);
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vmstate_register_ram_global(ocm_ram);
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memory_region_add_subregion(address_space_mem, 0xFFFC0000, ocm_ram);
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DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0);
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/* AMD */
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pflash_cfi02_register(0xe2000000, NULL, "zynq.pflash", FLASH_SIZE,
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dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
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FLASH_SECTOR_SIZE,
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FLASH_SIZE/FLASH_SECTOR_SIZE, 1,
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1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa,
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0);
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dev = qdev_create(NULL, "xilinx,zynq_slcr");
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qdev_init_nofail(dev);
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8000000);
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dev = qdev_create(NULL, "a9mpcore_priv");
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qdev_prop_set_uint32(dev, "num-cpu", 1);
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qdev_init_nofail(dev);
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busdev = SYS_BUS_DEVICE(dev);
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sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE);
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sysbus_connect_irq(busdev, 0,
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qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ));
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for (n = 0; n < 64; n++) {
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pic[n] = qdev_get_gpio_in(dev, n);
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}
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zynq_init_spi_flashes(0xE0006000, pic[58-IRQ_OFFSET], false);
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zynq_init_spi_flashes(0xE0007000, pic[81-IRQ_OFFSET], false);
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zynq_init_spi_flashes(0xE000D000, pic[51-IRQ_OFFSET], true);
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sysbus_create_simple("xlnx,ps7-usb", 0xE0002000, pic[53-IRQ_OFFSET]);
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sysbus_create_simple("xlnx,ps7-usb", 0xE0003000, pic[76-IRQ_OFFSET]);
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sysbus_create_simple("cadence_uart", 0xE0000000, pic[59-IRQ_OFFSET]);
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sysbus_create_simple("cadence_uart", 0xE0001000, pic[82-IRQ_OFFSET]);
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sysbus_create_varargs("cadence_ttc", 0xF8001000,
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pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL);
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sysbus_create_varargs("cadence_ttc", 0xF8002000,
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pic[69-IRQ_OFFSET], pic[70-IRQ_OFFSET], pic[71-IRQ_OFFSET], NULL);
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gem_init(&nd_table[0], 0xE000B000, pic[54-IRQ_OFFSET]);
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gem_init(&nd_table[1], 0xE000C000, pic[77-IRQ_OFFSET]);
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dev = qdev_create(NULL, "generic-sdhci");
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qdev_init_nofail(dev);
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xE0100000);
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[56-IRQ_OFFSET]);
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di = drive_get_next(IF_SD);
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blk = di ? blk_by_legacy_dinfo(di) : NULL;
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carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD);
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qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
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object_property_set_bool(OBJECT(carddev), true, "realized", &error_fatal);
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dev = qdev_create(NULL, "generic-sdhci");
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qdev_init_nofail(dev);
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xE0101000);
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[79-IRQ_OFFSET]);
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di = drive_get_next(IF_SD);
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blk = di ? blk_by_legacy_dinfo(di) : NULL;
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carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus"), TYPE_SD_CARD);
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qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
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object_property_set_bool(OBJECT(carddev), true, "realized", &error_fatal);
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dev = qdev_create(NULL, TYPE_ZYNQ_XADC);
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qdev_init_nofail(dev);
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8007100);
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[39-IRQ_OFFSET]);
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dev = qdev_create(NULL, "pl330");
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qdev_prop_set_uint8(dev, "num_chnls", 8);
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qdev_prop_set_uint8(dev, "num_periph_req", 4);
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qdev_prop_set_uint8(dev, "num_events", 16);
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qdev_prop_set_uint8(dev, "data_width", 64);
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qdev_prop_set_uint8(dev, "wr_cap", 8);
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qdev_prop_set_uint8(dev, "wr_q_dep", 16);
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qdev_prop_set_uint8(dev, "rd_cap", 8);
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qdev_prop_set_uint8(dev, "rd_q_dep", 16);
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qdev_prop_set_uint16(dev, "data_buffer_dep", 256);
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qdev_init_nofail(dev);
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busdev = SYS_BUS_DEVICE(dev);
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sysbus_mmio_map(busdev, 0, 0xF8003000);
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sysbus_connect_irq(busdev, 0, pic[45-IRQ_OFFSET]); /* abort irq line */
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for (n = 0; n < 8; ++n) { /* event irqs */
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sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - IRQ_OFFSET]);
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}
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zynq_binfo.ram_size = ram_size;
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zynq_binfo.kernel_filename = kernel_filename;
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zynq_binfo.kernel_cmdline = kernel_cmdline;
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zynq_binfo.initrd_filename = initrd_filename;
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zynq_binfo.nb_cpus = 1;
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zynq_binfo.board_id = 0xd32;
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zynq_binfo.loader_start = 0;
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zynq_binfo.board_setup_addr = BOARD_SETUP_ADDR;
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zynq_binfo.write_board_setup = zynq_write_board_setup;
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arm_load_kernel(ARM_CPU(first_cpu), &zynq_binfo);
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}
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static void zynq_machine_init(MachineClass *mc)
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{
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mc->desc = "Xilinx Zynq Platform Baseboard for Cortex-A9";
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mc->init = zynq_init;
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mc->block_default_type = IF_SCSI;
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mc->max_cpus = 1;
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mc->no_sdcard = 1;
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}
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DEFINE_MACHINE("xilinx-zynq-a9", zynq_machine_init)
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